drm/nve0/fifo: mask unhandled intr bits when seen, rather than all intrs

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nve0/fifo: mask unhandled intr bits when seen, rather than all intrs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
7a42f492 · Ben Skeggs · 61fdf620 · 7a42f492
Commit 7a42f492 authored Feb 23, 2014 by Ben Skeggs
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drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +2 -2

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--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
@@ -743,9 +743,9 @@ nve0_fifo_intr(struct nouveau_subdev *subdev)
 	}
 	if (stat) {
-		nv_fatal(priv, "unhandled status 0x%08x\n", stat);
+		nv_error(priv, "INTR 0x%08x\n", stat);
+		nv_mask(priv, 0x002140, stat, 0x00000000);
 		nv_wr32(priv, 0x002100, stat);
-		nv_wr32(priv, 0x002140, 0);
 	}
 }