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Commit 7a8fdb1f authored by Ville Syrjälä's avatar Ville Syrjälä
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drm/i915: Change watermark hook calling convention 

Just pass the atomic_state+crtc to the watermarks hooks. Eeasier
time for the caller when it doesn't have to think what to pass.
Reviewed-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191118164430.27265-7-ville.syrjala@linux.intel.com
parent 5b4f4e94
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Showing with 53 additions and 48 deletions
drivers/gpu/drm/i915/display/intel_display.c
View file @ 7a8fdb1f
...@@ -6189,9 +6189,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, ...@@ -6189,9 +6189,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
* we'll continue to update watermarks the old way, if flags tell * we'll continue to update watermarks the old way, if flags tell
* us to. * us to.
*/ */
if (dev_priv->display.initial_watermarks != NULL) if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(intel_state, dev_priv->display.initial_watermarks(intel_state, crtc);
pipe_config);
else if (pipe_config->update_wm_pre) else if (pipe_config->update_wm_pre)
intel_update_watermarks(crtc); intel_update_watermarks(crtc);
} }
...@@ -6539,8 +6538,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, ...@@ -6539,8 +6538,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */ /* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config); intel_disable_primary_plane(pipe_config);
if (dev_priv->display.initial_watermarks != NULL) if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, pipe_config); dev_priv->display.initial_watermarks(state, intel_crtc);
intel_enable_pipe(pipe_config); intel_enable_pipe(pipe_config);
if (pipe_config->has_pch_encoder) if (pipe_config->has_pch_encoder)
...@@ -6698,8 +6697,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, ...@@ -6698,8 +6697,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (!transcoder_is_dsi(cpu_transcoder)) if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_enable_transcoder_func(pipe_config); intel_ddi_enable_transcoder_func(pipe_config);
if (dev_priv->display.initial_watermarks != NULL) if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, pipe_config); dev_priv->display.initial_watermarks(state, intel_crtc);
if (INTEL_GEN(dev_priv) >= 11) if (INTEL_GEN(dev_priv) >= 11)
icl_pipe_mbus_enable(intel_crtc); icl_pipe_mbus_enable(intel_crtc);
...@@ -7083,7 +7082,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, ...@@ -7083,7 +7082,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */ /* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config); intel_disable_primary_plane(pipe_config);
dev_priv->display.initial_watermarks(state, pipe_config); dev_priv->display.initial_watermarks(state, intel_crtc);
intel_enable_pipe(pipe_config); intel_enable_pipe(pipe_config);
intel_crtc_vblank_on(pipe_config); intel_crtc_vblank_on(pipe_config);
...@@ -7138,9 +7137,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, ...@@ -7138,9 +7137,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */ /* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config); intel_disable_primary_plane(pipe_config);
if (dev_priv->display.initial_watermarks != NULL) if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, dev_priv->display.initial_watermarks(state, intel_crtc);
pipe_config);
else else
intel_update_watermarks(intel_crtc); intel_update_watermarks(intel_crtc);
intel_enable_pipe(pipe_config); intel_enable_pipe(pipe_config);
...@@ -14321,6 +14319,7 @@ static void commit_pipe_config(struct intel_atomic_state *state, ...@@ -14321,6 +14319,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
struct intel_crtc_state *old_crtc_state, struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state) struct intel_crtc_state *new_crtc_state)
{ {
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct drm_i915_private *dev_priv = to_i915(state->base.dev);
bool modeset = needs_modeset(new_crtc_state); bool modeset = needs_modeset(new_crtc_state);
...@@ -14344,8 +14343,7 @@ static void commit_pipe_config(struct intel_atomic_state *state, ...@@ -14344,8 +14343,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
} }
if (dev_priv->display.atomic_update_watermarks) if (dev_priv->display.atomic_update_watermarks)
dev_priv->display.atomic_update_watermarks(state, dev_priv->display.atomic_update_watermarks(state, crtc);
new_crtc_state);
} }
static void intel_update_crtc(struct intel_crtc *crtc, static void intel_update_crtc(struct intel_crtc *crtc,
...@@ -14449,8 +14447,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state, ...@@ -14449,8 +14447,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
if (!new_crtc_state->hw.active && if (!new_crtc_state->hw.active &&
!HAS_GMCH(dev_priv) && !HAS_GMCH(dev_priv) &&
dev_priv->display.initial_watermarks) dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, dev_priv->display.initial_watermarks(state, crtc);
new_crtc_state);
} }
static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state, static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
...@@ -14900,8 +14897,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) ...@@ -14900,8 +14897,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
*/ */
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (dev_priv->display.optimize_watermarks) if (dev_priv->display.optimize_watermarks)
dev_priv->display.optimize_watermarks(state, dev_priv->display.optimize_watermarks(state, crtc);
new_crtc_state);
} }
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
...@@ -16856,7 +16852,7 @@ static void sanitize_watermarks(struct drm_device *dev) ...@@ -16856,7 +16852,7 @@ static void sanitize_watermarks(struct drm_device *dev)
/* Write calculated watermark values back */ /* Write calculated watermark values back */
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
crtc_state->wm.need_postvbl_update = true; crtc_state->wm.need_postvbl_update = true;
dev_priv->display.optimize_watermarks(intel_state, crtc_state); dev_priv->display.optimize_watermarks(intel_state, crtc);
to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
} }
......
drivers/gpu/drm/i915/i915_drv.h
View file @ 7a8fdb1f
...@@ -273,11 +273,11 @@ struct drm_i915_display_funcs { ...@@ -273,11 +273,11 @@ struct drm_i915_display_funcs {
int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state); int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state); int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
void (*initial_watermarks)(struct intel_atomic_state *state, void (*initial_watermarks)(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state); struct intel_crtc *crtc);
void (*atomic_update_watermarks)(struct intel_atomic_state *state, void (*atomic_update_watermarks)(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state); struct intel_crtc *crtc);
void (*optimize_watermarks)(struct intel_atomic_state *state, void (*optimize_watermarks)(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state); struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state); int (*compute_global_watermarks)(struct intel_atomic_state *state);
void (*update_wm)(struct intel_crtc *crtc); void (*update_wm)(struct intel_crtc *crtc);
int (*modeset_calc_cdclk)(struct intel_atomic_state *state); int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
......
drivers/gpu/drm/i915/intel_pm.c
View file @ 7a8fdb1f
...@@ -1528,10 +1528,11 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv) ...@@ -1528,10 +1528,11 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
} }
static void g4x_initial_watermarks(struct intel_atomic_state *state, static void g4x_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state) struct intel_crtc *crtc)
{ {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
mutex_lock(&dev_priv->wm.wm_mutex); mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate; crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
...@@ -1540,10 +1541,11 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state, ...@@ -1540,10 +1541,11 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
} }
static void g4x_optimize_watermarks(struct intel_atomic_state *state, static void g4x_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state) struct intel_crtc *crtc)
{ {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update) if (!crtc_state->wm.need_postvbl_update)
return; return;
...@@ -1923,11 +1925,12 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state) ...@@ -1923,11 +1925,12 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
(((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
static void vlv_atomic_update_fifo(struct intel_atomic_state *state, static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state) struct intel_crtc *crtc)
{ {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_uncore *uncore = &dev_priv->uncore; struct intel_uncore *uncore = &dev_priv->uncore;
const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct vlv_fifo_state *fifo_state = const struct vlv_fifo_state *fifo_state =
&crtc_state->wm.vlv.fifo_state; &crtc_state->wm.vlv.fifo_state;
int sprite0_start, sprite1_start, fifo_size; int sprite0_start, sprite1_start, fifo_size;
...@@ -2147,10 +2150,11 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv) ...@@ -2147,10 +2150,11 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
} }
static void vlv_initial_watermarks(struct intel_atomic_state *state, static void vlv_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state) struct intel_crtc *crtc)
{ {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
mutex_lock(&dev_priv->wm.wm_mutex); mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate; crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
...@@ -2159,10 +2163,11 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state, ...@@ -2159,10 +2163,11 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
} }
static void vlv_optimize_watermarks(struct intel_atomic_state *state, static void vlv_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state) struct intel_crtc *crtc)
{ {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update) if (!crtc_state->wm.need_postvbl_update)
return; return;
...@@ -5499,11 +5504,12 @@ skl_compute_wm(struct intel_atomic_state *state) ...@@ -5499,11 +5504,12 @@ skl_compute_wm(struct intel_atomic_state *state)
} }
static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state, static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state) struct intel_crtc *crtc)
{ {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_i915_private *dev_priv = to_i915(state->base.dev); const struct intel_crtc_state *crtc_state =
struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; intel_atomic_get_new_crtc_state(state, crtc);
const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
enum pipe pipe = crtc->pipe; enum pipe pipe = crtc->pipe;
if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0) if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
...@@ -5513,10 +5519,11 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state, ...@@ -5513,10 +5519,11 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
} }
static void skl_initial_wm(struct intel_atomic_state *state, static void skl_initial_wm(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state) struct intel_crtc *crtc)
{ {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct skl_ddb_values *results = &state->wm_results; struct skl_ddb_values *results = &state->wm_results;
if ((results->dirty_pipes & BIT(crtc->pipe)) == 0) if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
...@@ -5525,7 +5532,7 @@ static void skl_initial_wm(struct intel_atomic_state *state, ...@@ -5525,7 +5532,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
mutex_lock(&dev_priv->wm.wm_mutex); mutex_lock(&dev_priv->wm.wm_mutex);
if (crtc_state->uapi.active_changed) if (crtc_state->uapi.active_changed)
skl_atomic_update_crtc_wm(state, crtc_state); skl_atomic_update_crtc_wm(state, crtc);
mutex_unlock(&dev_priv->wm.wm_mutex); mutex_unlock(&dev_priv->wm.wm_mutex);
} }
...@@ -5581,10 +5588,11 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv) ...@@ -5581,10 +5588,11 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
} }
static void ilk_initial_watermarks(struct intel_atomic_state *state, static void ilk_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state) struct intel_crtc *crtc)
{ {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
mutex_lock(&dev_priv->wm.wm_mutex); mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate; crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
...@@ -5593,10 +5601,11 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state, ...@@ -5593,10 +5601,11 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
} }
static void ilk_optimize_watermarks(struct intel_atomic_state *state, static void ilk_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state) struct intel_crtc *crtc)
{ {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update) if (!crtc_state->wm.need_postvbl_update)
return; return;
......
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