drm/amd/powerplay: implement check_fw_status function for smu11

Add function of check firmware status funtions for smu11
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h

@@ -25,6 +25,17 @@
 
 #include "amdgpu_smu.h"
 
+/* MP Apertures */
+#define MP0_Public			0x03800000
+#define MP0_SRAM			0x03900000
+#define MP1_Public			0x03b00000
+#define MP1_SRAM			0x03c00004
+
+/* address block */
+#define smnMP1_FIRMWARE_FLAGS		0x3010024
+#define smnMP0_FW_INTF			0x30101c0
+#define smnMP1_PUB_CTRL			0x3010b14
+
 void smu_v11_0_set_smu_funcs(struct smu_context *smu);
 
 #endif

drivers/gpu/drm/amd/powerplay/smu_v11_0.c

@@ -168,7 +168,18 @@ static int smu_v11_0_load_microcode(struct smu_context *smu)
 
 static int smu_v11_0_check_fw_status(struct smu_context *smu)
 {
+	struct amdgpu_device *adev = smu->adev;
+	uint32_t mp1_fw_flags;
+
+	WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2,
+		     (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
+
+	mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2);
+
+	if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
+	    MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 		return 0;
+	return -EIO;
 }
 
 static const struct smu_funcs smu_v11_0_funcs = {