Commit 7b1e6620 authored by David S. Miller's avatar David S. Miller

Tigon3: Handle posted writes correctly.

parent 4a493922
...@@ -3206,12 +3206,19 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) ...@@ -3206,12 +3206,19 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
/* Now startup only the RX cpu. */ /* Now startup only the RX cpu. */
tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
tw32(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR); tw32(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
/* Flush posted writes. */
tr32(RX_CPU_BASE + CPU_PC);
for (i = 0; i < 5; i++) { for (i = 0; i < 5; i++) {
if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR) if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
break; break;
tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
tw32(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR); tw32(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
/* Flush posted writes. */
tr32(RX_CPU_BASE + CPU_PC);
udelay(1000); udelay(1000);
} }
if (i >= 5) { if (i >= 5) {
...@@ -3224,6 +3231,9 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) ...@@ -3224,6 +3231,9 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
tw32(RX_CPU_BASE + CPU_MODE, 0x00000000); tw32(RX_CPU_BASE + CPU_MODE, 0x00000000);
/* Flush posted writes. */
tr32(RX_CPU_BASE + CPU_MODE);
return 0; return 0;
} }
......
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