Commit 80d6b466 authored by Will Deacon's avatar Will Deacon

arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD

TCR_EL1.HD is permitted to be cached in a TLB, so invalidate the local
TLB after setting the bit when detected support for the feature. Although
this isn't strictly necessary, since we can happily operate with the bit
effectively clear, the current code uses an ISB in a half-hearted attempt
to make the change effective, so let's just fix that up.

Link: https://lore.kernel.org/r/20201001110405.18617-1-will@kernel.orgReviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Reviewed-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 6a1bdb17
...@@ -1443,6 +1443,7 @@ static inline void __cpu_enable_hw_dbm(void) ...@@ -1443,6 +1443,7 @@ static inline void __cpu_enable_hw_dbm(void)
write_sysreg(tcr, tcr_el1); write_sysreg(tcr, tcr_el1);
isb(); isb();
local_flush_tlb_all();
} }
static bool cpu_has_broken_dbm(void) static bool cpu_has_broken_dbm(void)
......
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