Commit 80ea2c12 authored by Alex Deucher's avatar Alex Deucher

drm/radeon/kms: add dpm support for sumo asics (v2)

This adds dpm support for sumo asics.  This includes:
- clockgating
- powergating
- dynamic engine clock scaling
- dynamic voltage scaling

set radeon.dpm=1 to enable it.

v2: fix indention
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarJerome Glisse <jglisse@redhat.com>
parent 6596afd4
...@@ -78,7 +78,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ ...@@ -78,7 +78,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \ atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \ si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \
r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \ r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \
rv770_smc.o cypress_dpm.o btc_dpm.o rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
......
...@@ -1614,6 +1614,18 @@ static struct radeon_asic sumo_asic = { ...@@ -1614,6 +1614,18 @@ static struct radeon_asic sumo_asic = {
.set_uvd_clocks = &sumo_set_uvd_clocks, .set_uvd_clocks = &sumo_set_uvd_clocks,
.get_temperature = &sumo_get_temp, .get_temperature = &sumo_get_temp,
}, },
.dpm = {
.init = &sumo_dpm_init,
.setup_asic = &sumo_dpm_setup_asic,
.enable = &sumo_dpm_enable,
.disable = &sumo_dpm_disable,
.set_power_state = &sumo_dpm_set_power_state,
.display_configuration_changed = &sumo_dpm_display_configuration_changed,
.fini = &sumo_dpm_fini,
.get_sclk = &sumo_dpm_get_sclk,
.get_mclk = &sumo_dpm_get_mclk,
.print_power_state = &sumo_dpm_print_power_state,
},
.pflip = { .pflip = {
.pre_page_flip = &evergreen_pre_page_flip, .pre_page_flip = &evergreen_pre_page_flip,
.page_flip = &evergreen_page_flip, .page_flip = &evergreen_page_flip,
......
...@@ -542,6 +542,17 @@ int btc_dpm_enable(struct radeon_device *rdev); ...@@ -542,6 +542,17 @@ int btc_dpm_enable(struct radeon_device *rdev);
void btc_dpm_disable(struct radeon_device *rdev); void btc_dpm_disable(struct radeon_device *rdev);
int btc_dpm_set_power_state(struct radeon_device *rdev); int btc_dpm_set_power_state(struct radeon_device *rdev);
void btc_dpm_fini(struct radeon_device *rdev); void btc_dpm_fini(struct radeon_device *rdev);
int sumo_dpm_init(struct radeon_device *rdev);
int sumo_dpm_enable(struct radeon_device *rdev);
void sumo_dpm_disable(struct radeon_device *rdev);
int sumo_dpm_set_power_state(struct radeon_device *rdev);
void sumo_dpm_setup_asic(struct radeon_device *rdev);
void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
void sumo_dpm_fini(struct radeon_device *rdev);
u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
void sumo_dpm_print_power_state(struct radeon_device *rdev,
struct radeon_ps *ps);
/* /*
* cayman * cayman
......
...@@ -1046,6 +1046,9 @@ int radeon_pm_init(struct radeon_device *rdev) ...@@ -1046,6 +1046,9 @@ int radeon_pm_init(struct radeon_device *rdev)
case CHIP_JUNIPER: case CHIP_JUNIPER:
case CHIP_CYPRESS: case CHIP_CYPRESS:
case CHIP_HEMLOCK: case CHIP_HEMLOCK:
case CHIP_PALM:
case CHIP_SUMO:
case CHIP_SUMO2:
case CHIP_BARTS: case CHIP_BARTS:
case CHIP_TURKS: case CHIP_TURKS:
case CHIP_CAICOS: case CHIP_CAICOS:
......
This diff is collapsed.
/*
* Copyright 2012 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __SUMO_DPM_H__
#define __SUMO_DPM_H__
#define SUMO_MAX_HARDWARE_POWERLEVELS 5
#define SUMO_PM_NUMBER_OF_TC 15
struct sumo_pl {
u32 sclk;
u32 vddc_index;
u32 ds_divider_index;
u32 ss_divider_index;
u32 allow_gnb_slow;
u32 sclk_dpm_tdp_limit;
};
/* used for the flags field */
#define SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE (1 << 0)
#define SUMO_POWERSTATE_FLAGS_BOOST_STATE (1 << 1)
struct sumo_ps {
struct sumo_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
u32 num_levels;
/* flags */
u32 flags;
};
#define NUMBER_OF_M3ARB_PARAM_SETS 10
#define SUMO_MAX_NUMBER_VOLTAGES 4
struct sumo_disp_clock_voltage_mapping_table {
u32 num_max_voltage_levels;
u32 display_clock_frequency[SUMO_MAX_NUMBER_VOLTAGES];
};
struct sumo_vid_mapping_entry {
u16 vid_2bit;
u16 vid_7bit;
};
struct sumo_vid_mapping_table {
u32 num_entries;
struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES];
};
struct sumo_sclk_voltage_mapping_entry {
u32 sclk_frequency;
u16 vid_2bit;
u16 rsv;
};
struct sumo_sclk_voltage_mapping_table {
u32 num_max_dpm_entries;
struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS];
};
struct sumo_sys_info {
u32 bootup_sclk;
u32 min_sclk;
u32 bootup_uma_clk;
u16 bootup_nb_voltage_index;
u8 htc_tmp_lmt;
u8 htc_hyst_lmt;
struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
struct sumo_disp_clock_voltage_mapping_table disp_clk_voltage_mapping_table;
struct sumo_vid_mapping_table vid_mapping_table;
u32 csr_m3_arb_cntl_default[NUMBER_OF_M3ARB_PARAM_SETS];
u32 csr_m3_arb_cntl_uvd[NUMBER_OF_M3ARB_PARAM_SETS];
u32 csr_m3_arb_cntl_fs3d[NUMBER_OF_M3ARB_PARAM_SETS];
u32 sclk_dpm_boost_margin;
u32 sclk_dpm_throttle_margin;
u32 sclk_dpm_tdp_limit_pg;
u32 gnb_tdp_limit;
u32 sclk_dpm_tdp_limit_boost;
u32 boost_sclk;
u32 boost_vid_2bit;
bool enable_boost;
};
struct sumo_power_info {
u32 asi;
u32 pasi;
u32 bsp;
u32 bsu;
u32 pbsp;
u32 pbsu;
u32 dsp;
u32 psp;
u32 thermal_auto_throttling;
u32 uvd_m3_arbiter;
u32 fw_version;
struct sumo_sys_info sys_info;
struct sumo_pl acpi_pl;
struct sumo_pl boot_pl;
struct sumo_pl boost_pl;
struct sumo_ps current_ps;
bool disable_gfx_power_gating_in_uvd;
bool driver_nbps_policy_disable;
bool enable_alt_vddnb;
bool enable_dynamic_m3_arbiter;
bool enable_gfx_clock_gating;
bool enable_gfx_power_gating;
bool enable_mg_clock_gating;
bool enable_sclk_ds;
bool enable_auto_thermal_throttling;
bool enable_dynamic_patch_ps;
bool enable_dpm;
bool enable_boost;
};
#define SUMO_UTC_DFLT_00 0x48
#define SUMO_UTC_DFLT_01 0x44
#define SUMO_UTC_DFLT_02 0x44
#define SUMO_UTC_DFLT_03 0x44
#define SUMO_UTC_DFLT_04 0x44
#define SUMO_UTC_DFLT_05 0x44
#define SUMO_UTC_DFLT_06 0x44
#define SUMO_UTC_DFLT_07 0x44
#define SUMO_UTC_DFLT_08 0x44
#define SUMO_UTC_DFLT_09 0x44
#define SUMO_UTC_DFLT_10 0x44
#define SUMO_UTC_DFLT_11 0x44
#define SUMO_UTC_DFLT_12 0x44
#define SUMO_UTC_DFLT_13 0x44
#define SUMO_UTC_DFLT_14 0x44
#define SUMO_DTC_DFLT_00 0x48
#define SUMO_DTC_DFLT_01 0x44
#define SUMO_DTC_DFLT_02 0x44
#define SUMO_DTC_DFLT_03 0x44
#define SUMO_DTC_DFLT_04 0x44
#define SUMO_DTC_DFLT_05 0x44
#define SUMO_DTC_DFLT_06 0x44
#define SUMO_DTC_DFLT_07 0x44
#define SUMO_DTC_DFLT_08 0x44
#define SUMO_DTC_DFLT_09 0x44
#define SUMO_DTC_DFLT_10 0x44
#define SUMO_DTC_DFLT_11 0x44
#define SUMO_DTC_DFLT_12 0x44
#define SUMO_DTC_DFLT_13 0x44
#define SUMO_DTC_DFLT_14 0x44
#define SUMO_AH_DFLT 5
#define SUMO_R_DFLT0 70
#define SUMO_R_DFLT1 70
#define SUMO_R_DFLT2 70
#define SUMO_R_DFLT3 70
#define SUMO_R_DFLT4 100
#define SUMO_L_DFLT0 0
#define SUMO_L_DFLT1 20
#define SUMO_L_DFLT2 20
#define SUMO_L_DFLT3 20
#define SUMO_L_DFLT4 20
#define SUMO_VRC_DFLT 0x30033
#define SUMO_MGCGTTLOCAL0_DFLT 0
#define SUMO_MGCGTTLOCAL1_DFLT 0
#define SUMO_GICST_DFLT 19
#define SUMO_SST_DFLT 8
#define SUMO_VOLTAGEDROPT_DFLT 1
#define SUMO_GFXPOWERGATINGT_DFLT 100
/* sumo_dpm.c */
u32 sumo_get_xclk(struct radeon_device *rdev);
/* sumo_smc.c */
void sumo_initialize_m3_arb(struct radeon_device *rdev);
void sumo_smu_pg_init(struct radeon_device *rdev);
void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit);
void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev,
bool powersaving, bool force_nbps1);
void sumo_boost_state_enable(struct radeon_device *rdev, bool enable);
void sumo_enable_boost_timer(struct radeon_device *rdev);
u32 sumo_get_running_fw_version(struct radeon_device *rdev);
#endif
/*
* Copyright 2012 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <linux/firmware.h>
#include "drmP.h"
#include "radeon.h"
#include "sumod.h"
#include "sumo_dpm.h"
#include "ppsmc.h"
#include "radeon_ucode.h"
#define SUMO_SMU_SERVICE_ROUTINE_PG_INIT 1
#define SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY 27
#define SUMO_SMU_SERVICE_ROUTINE_GFX_SRV_ID_20 20
struct sumo_ps *sumo_get_ps(struct radeon_ps *rps);
struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev);
static void sumo_send_msg_to_smu(struct radeon_device *rdev, u32 id)
{
u32 gfx_int_req;
int i;
for (i = 0; i < rdev->usec_timeout; i++) {
if (RREG32(GFX_INT_STATUS) & INT_DONE)
break;
udelay(1);
}
gfx_int_req = SERV_INDEX(id) | INT_REQ;
WREG32(GFX_INT_REQ, gfx_int_req);
for (i = 0; i < rdev->usec_timeout; i++) {
if (RREG32(GFX_INT_REQ) & INT_REQ)
break;
udelay(1);
}
for (i = 0; i < rdev->usec_timeout; i++) {
if (RREG32(GFX_INT_STATUS) & INT_ACK)
break;
udelay(1);
}
for (i = 0; i < rdev->usec_timeout; i++) {
if (RREG32(GFX_INT_STATUS) & INT_DONE)
break;
udelay(1);
}
gfx_int_req &= ~INT_REQ;
WREG32(GFX_INT_REQ, gfx_int_req);
}
void sumo_initialize_m3_arb(struct radeon_device *rdev)
{
struct sumo_power_info *pi = sumo_get_pi(rdev);
u32 i;
if (!pi->enable_dynamic_m3_arbiter)
return;
for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++)
WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
pi->sys_info.csr_m3_arb_cntl_default[i]);
for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 2; i++)
WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
pi->sys_info.csr_m3_arb_cntl_uvd[i % NUMBER_OF_M3ARB_PARAM_SETS]);
for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 3; i++)
WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
pi->sys_info.csr_m3_arb_cntl_fs3d[i % NUMBER_OF_M3ARB_PARAM_SETS]);
}
static bool sumo_is_alt_vddnb_supported(struct radeon_device *rdev)
{
struct sumo_power_info *pi = sumo_get_pi(rdev);
bool return_code = false;
if (!pi->enable_alt_vddnb)
return return_code;
if ((rdev->family == CHIP_SUMO) || (rdev->family == CHIP_SUMO2)) {
if (pi->fw_version >= 0x00010C00)
return_code = true;
}
return return_code;
}
void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev,
bool powersaving, bool force_nbps1)
{
u32 param = 0;
if (!sumo_is_alt_vddnb_supported(rdev))
return;
if (powersaving)
param |= 1;
if (force_nbps1)
param |= 2;
WREG32_RCU(RCU_ALTVDDNB_NOTIFY, param);
sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY);
}
void sumo_smu_pg_init(struct radeon_device *rdev)
{
sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_PG_INIT);
}
static u32 sumo_power_of_4(u32 unit)
{
u32 ret = 1;
u32 i;
for (i = 0; i < unit; i++)
ret *= 4;
return ret;
}
void sumo_enable_boost_timer(struct radeon_device *rdev)
{
struct sumo_power_info *pi = sumo_get_pi(rdev);
u32 period, unit, timer_value;
u32 xclk = sumo_get_xclk(rdev);
unit = (RREG32_RCU(RCU_LCLK_SCALING_CNTL) & LCLK_SCALING_TIMER_PRESCALER_MASK)
>> LCLK_SCALING_TIMER_PRESCALER_SHIFT;
period = 100 * (xclk / 100 / sumo_power_of_4(unit));
timer_value = (period << 16) | (unit << 4);
WREG32_RCU(RCU_GNB_PWR_REP_TIMER_CNTL, timer_value);
WREG32_RCU(RCU_BOOST_MARGIN, pi->sys_info.sclk_dpm_boost_margin);
WREG32_RCU(RCU_THROTTLE_MARGIN, pi->sys_info.sclk_dpm_throttle_margin);
WREG32_RCU(GNB_TDP_LIMIT, pi->sys_info.gnb_tdp_limit);
WREG32_RCU(RCU_SclkDpmTdpLimitPG, pi->sys_info.sclk_dpm_tdp_limit_pg);
sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_GFX_SRV_ID_20);
}
void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit)
{
u32 regoffset = 0;
u32 shift = 0;
u32 mask = 0xFFF;
u32 sclk_dpm_tdp_limit;
switch (index) {
case 0:
regoffset = RCU_SclkDpmTdpLimit01;
shift = 16;
break;
case 1:
regoffset = RCU_SclkDpmTdpLimit01;
shift = 0;
break;
case 2:
regoffset = RCU_SclkDpmTdpLimit23;
shift = 16;
break;
case 3:
regoffset = RCU_SclkDpmTdpLimit23;
shift = 0;
break;
case 4:
regoffset = RCU_SclkDpmTdpLimit47;
shift = 16;
break;
case 7:
regoffset = RCU_SclkDpmTdpLimit47;
shift = 0;
break;
default:
break;
}
sclk_dpm_tdp_limit = RREG32_RCU(regoffset);
sclk_dpm_tdp_limit &= ~(mask << shift);
sclk_dpm_tdp_limit |= (tdp_limit << shift);
WREG32_RCU(regoffset, sclk_dpm_tdp_limit);
}
void sumo_boost_state_enable(struct radeon_device *rdev, bool enable)
{
u32 boost_disable = RREG32_RCU(RCU_GPU_BOOST_DISABLE);
boost_disable &= 0xFFFFFFFE;
boost_disable |= (enable ? 0 : 1);
WREG32_RCU(RCU_GPU_BOOST_DISABLE, boost_disable);
}
u32 sumo_get_running_fw_version(struct radeon_device *rdev)
{
return RREG32_RCU(RCU_FW_VERSION);
}
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