Commit 8437c25e authored by Russell King's avatar Russell King

ARM: omap: update clock source registration

In d7e81c26 (clocksource: Add clocksource_register_hz/khz interface) new
interfaces were added which simplify (and optimize) the selection of the
divisor shift/mult constants.  Switch over to using this new interface.
Tested-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent b460ddbb
...@@ -208,7 +208,6 @@ static struct clocksource clocksource_mpu = { ...@@ -208,7 +208,6 @@ static struct clocksource clocksource_mpu = {
.rating = 300, .rating = 300,
.read = mpu_read, .read = mpu_read,
.mask = CLOCKSOURCE_MASK(32), .mask = CLOCKSOURCE_MASK(32),
.shift = 24,
.flags = CLOCK_SOURCE_IS_CONTINUOUS, .flags = CLOCK_SOURCE_IS_CONTINUOUS,
}; };
...@@ -217,13 +216,10 @@ static void __init omap_init_clocksource(unsigned long rate) ...@@ -217,13 +216,10 @@ static void __init omap_init_clocksource(unsigned long rate)
static char err[] __initdata = KERN_ERR static char err[] __initdata = KERN_ERR
"%s: can't register clocksource!\n"; "%s: can't register clocksource!\n";
clocksource_mpu.mult
= clocksource_khz2mult(rate/1000, clocksource_mpu.shift);
setup_irq(INT_TIMER2, &omap_mpu_timer2_irq); setup_irq(INT_TIMER2, &omap_mpu_timer2_irq);
omap_mpu_timer_start(1, ~0, 1); omap_mpu_timer_start(1, ~0, 1);
if (clocksource_register(&clocksource_mpu)) if (clocksource_register_hz(&clocksource_mpu, rate))
printk(err, clocksource_mpu.name); printk(err, clocksource_mpu.name);
} }
......
...@@ -195,7 +195,6 @@ static struct clocksource clocksource_gpt = { ...@@ -195,7 +195,6 @@ static struct clocksource clocksource_gpt = {
.rating = 300, .rating = 300,
.read = clocksource_read_cycles, .read = clocksource_read_cycles,
.mask = CLOCKSOURCE_MASK(32), .mask = CLOCKSOURCE_MASK(32),
.shift = 24,
.flags = CLOCK_SOURCE_IS_CONTINUOUS, .flags = CLOCK_SOURCE_IS_CONTINUOUS,
}; };
...@@ -220,9 +219,7 @@ static void __init omap2_gp_clocksource_init(void) ...@@ -220,9 +219,7 @@ static void __init omap2_gp_clocksource_init(void)
omap_dm_timer_set_load_start(gpt, 1, 0); omap_dm_timer_set_load_start(gpt, 1, 0);
clocksource_gpt.mult = if (clocksource_register_hz(&clocksource_gpt, tick_rate))
clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
if (clocksource_register(&clocksource_gpt))
printk(err2, clocksource_gpt.name); printk(err2, clocksource_gpt.name);
} }
#endif #endif
......
...@@ -102,7 +102,6 @@ static struct clocksource clocksource_32k = { ...@@ -102,7 +102,6 @@ static struct clocksource clocksource_32k = {
.rating = 250, .rating = 250,
.read = omap_32k_read_dummy, .read = omap_32k_read_dummy,
.mask = CLOCKSOURCE_MASK(32), .mask = CLOCKSOURCE_MASK(32),
.shift = 10,
.flags = CLOCK_SOURCE_IS_CONTINUOUS, .flags = CLOCK_SOURCE_IS_CONTINUOUS,
}; };
...@@ -167,12 +166,9 @@ static int __init omap_init_clocksource_32k(void) ...@@ -167,12 +166,9 @@ static int __init omap_init_clocksource_32k(void)
if (sync_32k_ick) if (sync_32k_ick)
clk_enable(sync_32k_ick); clk_enable(sync_32k_ick);
clocksource_32k.mult = clocksource_hz2mult(32768,
clocksource_32k.shift);
offset_32k = clocksource_32k.read(&clocksource_32k); offset_32k = clocksource_32k.read(&clocksource_32k);
if (clocksource_register(&clocksource_32k)) if (clocksource_register_hz(&clocksource_32k, 32768))
printk(err, clocksource_32k.name); printk(err, clocksource_32k.name);
} }
return 0; return 0;
......
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