Commit 846fbcfe authored by Petar Jovanovic's avatar Petar Jovanovic Committed by Ralf Baechle

MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1

Define Cavium Octeon as a CPU that has support for mips32r1, mips32r2 and
mips64r1. This will affect show_cpuinfo() that will now correctly expose
mips32r1, mips32r2 and mips64r1 as supported ISAs.
Signed-off-by: default avatarPetar Jovanovic <petar.jovanovic@rt-rk.com>
Reviewed-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
Acked-by: default avatarDavid Daney <david.daney@cavium.com>
Cc: petar.jovanovic@imgtec.com
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15749/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b123718b
...@@ -46,9 +46,9 @@ ...@@ -46,9 +46,9 @@
#define cpu_has_64bits 1 #define cpu_has_64bits 1
#define cpu_has_octeon_cache 1 #define cpu_has_octeon_cache 1
#define cpu_has_saa octeon_has_saa() #define cpu_has_saa octeon_has_saa()
#define cpu_has_mips32r1 0 #define cpu_has_mips32r1 1
#define cpu_has_mips32r2 0 #define cpu_has_mips32r2 1
#define cpu_has_mips64r1 0 #define cpu_has_mips64r1 1
#define cpu_has_mips64r2 1 #define cpu_has_mips64r2 1
#define cpu_has_dsp 0 #define cpu_has_dsp 0
#define cpu_has_dsp2 0 #define cpu_has_dsp2 0
......
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