Commit 8507bb00 authored by David Howells's avatar David Howells Committed by Linus Torvalds

FRV: ARCH_KMALLOC_MINALIGN was already defined

ARCH_KMALLOC_MINALIGN was already defined in asm/mem-layout.h and so shouldn't
have been added to asm/cache.h as well, but rather altered in place.

The commit that added it to asm/cache.h was:

	commit 69dcf3db
	Author: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
	Date:   Mon May 24 14:32:54 2010 -0700

	    frv: set ARCH_KMALLOC_MINALIGN

	    Architectures that handle DMA-non-coherent memory need to set
	    ARCH_KMALLOC_MINALIGN to make sure that kmalloc'ed buffer is
	    DMA-safe: the buffer doesn't share a cache with the others.
Signed-off-by: default avatarDavid Howells <dhowells@redhat.com>
cc: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 29d03fa1
...@@ -17,8 +17,6 @@ ...@@ -17,8 +17,6 @@
#define L1_CACHE_SHIFT (CONFIG_FRV_L1_CACHE_SHIFT) #define L1_CACHE_SHIFT (CONFIG_FRV_L1_CACHE_SHIFT)
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
#define __cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES))) #define __cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES)))
#define ____cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES))) #define ____cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES)))
......
...@@ -35,8 +35,8 @@ ...@@ -35,8 +35,8 @@
* the slab must be aligned such that load- and store-double instructions don't * the slab must be aligned such that load- and store-double instructions don't
* fault if used * fault if used
*/ */
#define ARCH_KMALLOC_MINALIGN 8 #define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
#define ARCH_SLAB_MINALIGN 8 #define ARCH_SLAB_MINALIGN L1_CACHE_BYTES
/*****************************************************************************/ /*****************************************************************************/
/* /*
......
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