Commit 8bb3d7e7 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher

drm/amd/display: used optimum VSTARTUP instead of MaxVStartup

[Description]
Features that are desirable for minimizing the Global Sync Period:
DRR and lateflip
Signed-off-by: default avatarCharlene Liu <charlene.liu@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 09104d15
...@@ -1671,6 +1671,8 @@ int dcn20_populate_dml_pipes_from_context( ...@@ -1671,6 +1671,8 @@ int dcn20_populate_dml_pipes_from_context(
/* Unknown link capabilities, so assume max */ /* Unknown link capabilities, so assume max */
pipes[pipe_cnt].dout.dp_lanes = 4; pipes[pipe_cnt].dout.dp_lanes = 4;
} }
pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.display_color_depth; pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.display_color_depth;
switch (res_ctx->pipe_ctx[i].stream->signal) { switch (res_ctx->pipe_ctx[i].stream->signal) {
...@@ -1749,6 +1751,8 @@ int dcn20_populate_dml_pipes_from_context( ...@@ -1749,6 +1751,8 @@ int dcn20_populate_dml_pipes_from_context(
pipes[pipe_cnt].pipe.scale_taps.vtaps = 1; pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
pipes[pipe_cnt].pipe.src.is_hsplit = 0; pipes[pipe_cnt].pipe.src.is_hsplit = 0;
pipes[pipe_cnt].pipe.dest.odm_combine = 0; pipes[pipe_cnt].pipe.dest.odm_combine = 0;
pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total;
pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total;
} else { } else {
struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
......
...@@ -2698,9 +2698,13 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer ...@@ -2698,9 +2698,13 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
VStartupMargin = dml_min(VStartupMargin, Margin); VStartupMargin = dml_min(VStartupMargin, Margin);
} }
if (mode_lib->vba.UseMaximumVStartup) if (mode_lib->vba.UseMaximumVStartup) {
if (mode_lib->vba.VTotal_Max[k] == mode_lib->vba.VTotal[k]) {
//only use max vstart if it is not drr or lateflip.
mode_lib->vba.VStartup[k] = mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]; mode_lib->vba.VStartup[k] = mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]];
} }
}
}
} }
} }
......
...@@ -284,6 +284,8 @@ struct vba_vars_st { ...@@ -284,6 +284,8 @@ struct vba_vars_st {
unsigned int VTAPsChroma[DC__NUM_DPP__MAX]; unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
unsigned int HTotal[DC__NUM_DPP__MAX]; unsigned int HTotal[DC__NUM_DPP__MAX];
unsigned int VTotal[DC__NUM_DPP__MAX]; unsigned int VTotal[DC__NUM_DPP__MAX];
unsigned int VTotal_Max[DC__NUM_DPP__MAX];
unsigned int VTotal_Min[DC__NUM_DPP__MAX];
int DPPPerPlane[DC__NUM_DPP__MAX]; int DPPPerPlane[DC__NUM_DPP__MAX];
double PixelClock[DC__NUM_DPP__MAX]; double PixelClock[DC__NUM_DPP__MAX];
double PixelClockBackEnd[DC__NUM_DPP__MAX]; double PixelClockBackEnd[DC__NUM_DPP__MAX];
......
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