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Commit 8bf752eb authored by Jeb J. Cramer's avatar Jeb J. Cramer Committed by Jeff Garzik
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[E1000] Whitespace changes 

* Miscellaneous whitespace changes
parent 85beee79
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Showing with 124 additions and 115 deletions
drivers/net/e1000/e1000_ethtool.c
View file @ 8bf752eb
......@@ -308,8 +308,8 @@ e1000_ethtool_gwol(struct e1000_adapter *adapter, struct ethtool_wolinfo *wol)
/* Fall Through */
default:
wol->supported = WAKE_UCAST | WAKE_MCAST
| WAKE_BCAST | WAKE_MAGIC;
wol->supported = WAKE_UCAST | WAKE_MCAST |
WAKE_BCAST | WAKE_MAGIC;
wol->wolopts = 0;
if(adapter->wol & E1000_WUFC_EX)
......@@ -343,7 +343,7 @@ e1000_ethtool_swol(struct e1000_adapter *adapter, struct ethtool_wolinfo *wol)
/* Fall Through */
default:
if(wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_PHY))
if(wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
return -EOPNOTSUPP;
adapter->wol = 0;
......
drivers/net/e1000/e1000_hw.c
View file @ 8bf752eb
......@@ -241,7 +241,7 @@ e1000_reset_hw(struct e1000_hw *hw)
/* Delay to allow any outstanding PCI transactions to complete before
* resetting the device
*/
*/
msec_delay(10);
/* Issue a global reset to the MAC. This will reset the chip's
......@@ -312,8 +312,8 @@ e1000_reset_hw(struct e1000_hw *hw)
* Performs basic configuration of the adapter.
*
* hw - Struct containing variables accessed by shared code
*
* Assumes that the controller has previously been reset and is in a
*
* Assumes that the controller has previously been reset and is in a
* post-reset uninitialized state. Initializes the receive address registers,
* multicast table, and VLAN filter table. Calls routines to setup link
* configuration and flow control settings. Clears all on-chip counters. Leaves
......@@ -338,7 +338,7 @@ e1000_init_hw(struct e1000_hw *hw)
DEBUGOUT("Error Initializing Identification LED\n");
return ret_val;
}
/* Set the Media Type and exit with error if it is not valid. */
if(hw->mac_type != e1000_82543) {
/* tbi_compatibility is only valid on 82543 */
......@@ -441,13 +441,13 @@ e1000_init_hw(struct e1000_hw *hw)
/******************************************************************************
* Configures flow control and link settings.
*
*
* hw - Struct containing variables accessed by shared code
*
*
* Determines which flow control settings to use. Calls the apropriate media-
* specific link configuration function. Configures the flow control settings.
* Assuming the adapter has a valid link partner, a valid link should be
* established. Assumes the hardware has previously been reset and the
* established. Assumes the hardware has previously been reset and the
* transmitter and receiver are not enabled.
*****************************************************************************/
int32_t
......@@ -475,7 +475,7 @@ e1000_setup_link(struct e1000_hw *hw)
if(hw->fc == e1000_fc_default) {
if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
hw->fc = e1000_fc_none;
else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
EEPROM_WORD0F_ASM_DIR)
hw->fc = e1000_fc_tx_pause;
else
......@@ -504,7 +504,7 @@ e1000_setup_link(struct e1000_hw *hw)
* or e1000_phy_setup() is called.
*/
if(hw->mac_type == e1000_82543) {
ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
SWDPIO__EXT_SHIFT);
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
}
......@@ -530,7 +530,7 @@ e1000_setup_link(struct e1000_hw *hw)
* these registers will be set to a default threshold that may be
* adjusted later by the driver's runtime code. However, if the
* ability to transmit pause frames in not enabled, then these
* registers will be set to 0.
* registers will be set to 0.
*/
if(!(hw->fc & e1000_fc_tx_pause)) {
E1000_WRITE_REG(hw, FCRTL, 0);
......@@ -559,7 +559,7 @@ e1000_setup_link(struct e1000_hw *hw)
* link. Assumes the hardware has been previously reset and the transmitter
* and receiver are not enabled.
*****************************************************************************/
static int32_t
static int32_t
e1000_setup_fiber_link(struct e1000_hw *hw)
{
uint32_t ctrl;
......@@ -571,29 +571,29 @@ e1000_setup_fiber_link(struct e1000_hw *hw)
DEBUGFUNC("e1000_setup_fiber_link");
/* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
* set when the optics detect a signal. On older adapters, it will be
/* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
* set when the optics detect a signal. On older adapters, it will be
* cleared when there is a signal
*/
ctrl = E1000_READ_REG(hw, CTRL);
if(hw->mac_type > e1000_82544) signal = E1000_CTRL_SWDPIN1;
else signal = 0;
/* Take the link out of reset */
ctrl &= ~(E1000_CTRL_LRST);
e1000_config_collision_dist(hw);
/* Check for a software override of the flow control settings, and setup
* the device accordingly. If auto-negotiation is enabled, then software
* will have to set the "PAUSE" bits to the correct value in the Tranmsit
* Config Word Register (TXCW) and re-start auto-negotiation. However, if
* auto-negotiation is disabled, then software will have to manually
* auto-negotiation is disabled, then software will have to manually
* configure the two flow control enable bits in the CTRL register.
*
* The possible values of the "fc" parameter are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames, but
* 1: Rx flow control is enabled (we can receive pause frames, but
* not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames but we do
* not support receiving pause frames).
......@@ -605,8 +605,8 @@ e1000_setup_fiber_link(struct e1000_hw *hw)
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
break;
case e1000_fc_rx_pause:
/* RX Flow control is enabled and TX Flow control is disabled by a
* software over-ride. Since there really isn't a way to advertise
/* RX Flow control is enabled and TX Flow control is disabled by a
* software over-ride. Since there really isn't a way to advertise
* that we are capable of RX Pause ONLY, we will advertise that we
* support both symmetric and asymmetric RX PAUSE. Later, we will
* disable the adapter's ability to send PAUSE frames.
......@@ -614,7 +614,7 @@ e1000_setup_fiber_link(struct e1000_hw *hw)
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
break;
case e1000_fc_tx_pause:
/* TX Flow control is enabled, and RX Flow control is disabled, by a
/* TX Flow control is enabled, and RX Flow control is disabled, by a
* software over-ride.
*/
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
......@@ -645,8 +645,8 @@ e1000_setup_fiber_link(struct e1000_hw *hw)
msec_delay(1);
/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
* indication in the Device Status Register. Time-out if a link isn't
* seen in 500 milliseconds seconds (Auto-negotiation should complete in
* indication in the Device Status Register. Time-out if a link isn't
* seen in 500 milliseconds seconds (Auto-negotiation should complete in
* less than 500 milliseconds even if the other end is doing it in SW).
*/
if((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
......@@ -657,7 +657,7 @@ e1000_setup_fiber_link(struct e1000_hw *hw)
if(status & E1000_STATUS_LU) break;
}
if(i == (LINK_UP_TIMEOUT / 10)) {
/* AutoNeg failed to achieve a link, so we'll call
/* AutoNeg failed to achieve a link, so we'll call
* e1000_check_for_link. This routine will force the link up if we
* detect a signal. This will allow us to communicate with
* non-autonegotiating link partners.
......@@ -1266,7 +1266,7 @@ if (hw->phy_type == e1000_phy_m88) {
}
if(i == 0) { /* We didn't get link */
/* Reset the DSP and wait again for link. */
ret_val = e1000_phy_reset_dsp(hw);
if(ret_val < 0) {
DEBUGOUT("Error Resetting PHY DSP\n");
......@@ -1417,7 +1417,7 @@ if (hw->phy_type == e1000_phy_igp) {
/******************************************************************************
* Forces the MAC's flow control settings.
*
*
* hw - Struct containing variables accessed by shared code
*
* Sets the TFCE and RFCE bits in the device control register to reflect
......@@ -1484,7 +1484,7 @@ e1000_force_mac_fc(struct e1000_hw *hw)
/******************************************************************************
* Configures flow control settings after link is established
*
*
* hw - Struct containing variables accessed by shared code
*
* Should be called immediately after a valid link has been established.
......@@ -1706,9 +1706,9 @@ e1000_check_for_link(struct e1000_hw *hw)
uint16_t lp_capability;
DEBUGFUNC("e1000_check_for_link");
/* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
* set when the optics detect a signal. On older adapters, it will be
/* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
* set when the optics detect a signal. On older adapters, it will be
* cleared when there is a signal
*/
if(hw->mac_type > e1000_82544) signal = E1000_CTRL_SWDPIN1;
......@@ -1773,7 +1773,7 @@ e1000_check_for_link(struct e1000_hw *hw)
}
}
/* Configure Flow Control now that Auto-Neg has completed. First, we
/* Configure Flow Control now that Auto-Neg has completed. First, we
* need to restore the desired flow control settings because we may
* have had to re-autoneg with a different link partner.
*/
......@@ -1802,7 +1802,7 @@ e1000_check_for_link(struct e1000_hw *hw)
NWAY_LPAR_100TX_HD_CAPS |
NWAY_LPAR_100TX_FD_CAPS |
NWAY_LPAR_100T4_CAPS)) {
/* If our link partner advertises anything in addition to
/* If our link partner advertises anything in addition to
* gigabit, we do not need to enable TBI compatibility.
*/
if(hw->tbi_compatibility_on) {
......@@ -2006,7 +2006,7 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw,
uint32_t mask;
/* We need to shift "count" number of bits out to the PHY. So, the value
* in the "data" parameter will be shifted out to the PHY one bit at a
* in the "data" parameter will be shifted out to the PHY one bit at a
* time. In order to do this, "data" must be broken down into bits.
*/
mask = 0x01;
......@@ -2043,7 +2043,7 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw,
*
* hw - Struct containing variables accessed by shared code
*
* Bits are shifted in in MSB to LSB order.
* Bits are shifted in in MSB to LSB order.
******************************************************************************/
static uint16_t
e1000_shift_in_mdi_bits(struct e1000_hw *hw)
......@@ -2058,7 +2058,7 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
* These two bits are ignored by us and thrown away. Bits are "shifted in"
* by raising the input to the Management Data Clock (setting the MDC bit),
* and then reading the value of the MDIO bit.
*/
*/
ctrl = E1000_READ_REG(hw, CTRL);
/* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
......@@ -2118,7 +2118,7 @@ e1000_read_phy_reg(struct e1000_hw *hw,
* PHY to retrieve the desired data.
*/
mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
(phy_addr << E1000_MDIC_PHY_SHIFT) |
(phy_addr << E1000_MDIC_PHY_SHIFT) |
(E1000_MDIC_OP_READ));
E1000_WRITE_REG(hw, MDIC, mdic);
......@@ -2156,7 +2156,7 @@ e1000_read_phy_reg(struct e1000_hw *hw,
* READ operation is performed. These two bits are thrown away
* followed by a shift in of 16 bits which contains the desired data.
*/
mdic = ((reg_addr) | (phy_addr << 5) |
mdic = ((reg_addr) | (phy_addr << 5) |
(PHY_OP_READ << 10) | (PHY_SOF << 12));
e1000_shift_out_mdi_bits(hw, mdic, 14);
......@@ -2200,7 +2200,7 @@ e1000_write_phy_reg(struct e1000_hw *hw,
*/
mdic = (((uint32_t) phy_data) |
(reg_addr << E1000_MDIC_REG_SHIFT) |
(phy_addr << E1000_MDIC_PHY_SHIFT) |
(phy_addr << E1000_MDIC_PHY_SHIFT) |
(E1000_MDIC_OP_WRITE));
E1000_WRITE_REG(hw, MDIC, mdic);
......@@ -2218,12 +2218,12 @@ e1000_write_phy_reg(struct e1000_hw *hw,
} else {
/* We'll need to use the SW defined pins to shift the write command
* out to the PHY. We first send a preamble to the PHY to signal the
* beginning of the MII instruction. This is done by sending 32
* beginning of the MII instruction. This is done by sending 32
* consecutive "1" bits.
*/
e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
/* Now combine the remaining required fields that will indicate a
/* Now combine the remaining required fields that will indicate a
* write operation. We use this method instead of calling the
* e1000_shift_out_mdi_bits routine for each field in the command. The
* format of a MII write instruction is as follows:
......@@ -2236,6 +2236,7 @@ e1000_write_phy_reg(struct e1000_hw *hw,
e1000_shift_out_mdi_bits(hw, mdic, 32);
}
return 0;
}
......@@ -2393,7 +2394,7 @@ e1000_phy_reset_dsp(struct e1000_hw *hw)
{
int32_t ret_val = -E1000_ERR_PHY;
DEBUGFUNC("e1000_phy_reset_dsp");
do {
if(e1000_write_phy_reg(hw, 29, 0x001d) < 0) break;
if(e1000_write_phy_reg(hw, 30, 0x00c1) < 0) break;
......@@ -3125,7 +3126,7 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
if(checksum == (uint16_t) EEPROM_SUM) {
return 0;
} else {
DEBUGOUT("EEPROM Checksum Invalid\n");
DEBUGOUT("EEPROM Checksum Invalid\n");
return -E1000_ERR_EEPROM;
}
}
......@@ -3431,7 +3432,7 @@ e1000_read_mac_addr(struct e1000_hw * hw)
/******************************************************************************
* Initializes receive address filters.
*
* hw - Struct containing variables accessed by shared code
* hw - Struct containing variables accessed by shared code
*
* Places the MAC address in receive address register 0 and clears the rest
* of the receive addresss registers. Clears the multicast table. Assumes
......@@ -3476,7 +3477,7 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
*
* The given list replaces any existing list. Clears the last 15 receive
* address registers and the multicast table. Uses receive address registers
* for the first 15 multicast addresses, and hashes the rest into the
* for the first 15 multicast addresses, and hashes the rest into the
* multicast table.
*****************************************************************************/
void
......@@ -3525,7 +3526,7 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
/* Place this multicast address in the RAR if there is room, *
* else put it in the MTA
* else put it in the MTA
*/
if(rar_used_count < E1000_RAR_ENTRIES) {
e1000_rar_set(hw,
......@@ -3543,7 +3544,7 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
* Hashes an address to determine its location in the multicast table
*
* hw - Struct containing variables accessed by shared code
* mc_addr - the multicast address to hash
* mc_addr - the multicast address to hash
*****************************************************************************/
uint32_t
e1000_hash_mc_addr(struct e1000_hw *hw,
......@@ -3552,7 +3553,7 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
uint32_t hash_value = 0;
/* The portion of the address that is used for the hash table is
* determined by the mc_filter_type setting.
* determined by the mc_filter_type setting.
*/
switch (hw->mc_filter_type) {
/* [0] [1] [2] [3] [4] [5]
......@@ -3595,12 +3596,12 @@ e1000_mta_set(struct e1000_hw *hw,
uint32_t mta;
uint32_t temp;
/* The MTA is a register array of 128 32-bit registers.
* It is treated like an array of 4096 bits. We want to set
/* The MTA is a register array of 128 32-bit registers.
* It is treated like an array of 4096 bits. We want to set
* bit BitArray[hash_value]. So we figure out what register
* the bit is in, read it, OR in the new bit, then write
* back the new value. The register is determined by the
* upper 7 bits of the hash value and the bit within that
* back the new value. The register is determined by the
* upper 7 bits of the hash value and the bit within that
* register are determined by the lower 5 bits of the value.
*/
hash_reg = (hash_value >> 5) & 0x7F;
......@@ -3638,7 +3639,7 @@ e1000_rar_set(struct e1000_hw *hw,
uint32_t rar_low, rar_high;
/* HW expects these in little endian so we reverse the byte order
* from network order (big endian) to little endian
* from network order (big endian) to little endian
*/
rar_low = ((uint32_t) addr[0] |
((uint32_t) addr[1] << 8) |
......@@ -3764,9 +3765,9 @@ int32_t
e1000_setup_led(struct e1000_hw *hw)
{
uint32_t ledctl;
DEBUGFUNC("e1000_setup_led");
switch(hw->device_id) {
case E1000_DEV_ID_82542:
case E1000_DEV_ID_82543GC_FIBER:
......@@ -3784,7 +3785,7 @@ e1000_setup_led(struct e1000_hw *hw)
hw->ledctl_default = ledctl;
/* Turn off LED0 */
ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
E1000_LEDCTL_LED0_BLINK |
E1000_LEDCTL_LED0_BLINK |
E1000_LEDCTL_LED0_MODE_MASK);
ledctl |= (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED0_MODE_SHIFT);
E1000_WRITE_REG(hw, LEDCTL, ledctl);
......@@ -3849,7 +3850,7 @@ e1000_cleanup_led(struct e1000_hw *hw)
}
return 0;
}
/******************************************************************************
* Turns on the software controllable LED
*
......@@ -3957,7 +3958,7 @@ e1000_led_off(struct e1000_hw *hw)
}
/******************************************************************************
* Clears all hardware statistics counters.
* Clears all hardware statistics counters.
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
......@@ -4076,7 +4077,7 @@ e1000_update_adaptive(struct e1000_hw *hw)
DEBUGFUNC("e1000_update_adaptive");
if(hw->adaptive_ifs) {
if((hw->collision_delta * hw->ifs_ratio) >
if((hw->collision_delta * hw->ifs_ratio) >
hw->tx_packet_delta) {
if(hw->tx_packet_delta > MIN_NUM_XMITS) {
hw->in_ifs_mode = TRUE;
......@@ -4089,7 +4090,7 @@ e1000_update_adaptive(struct e1000_hw *hw)
}
}
} else {
if((hw->in_ifs_mode == TRUE) &&
if((hw->in_ifs_mode == TRUE) &&
(hw->tx_packet_delta <= MIN_NUM_XMITS)) {
hw->current_ifs_val = 0;
hw->in_ifs_mode = FALSE;
......@@ -4103,7 +4104,7 @@ e1000_update_adaptive(struct e1000_hw *hw)
/******************************************************************************
* Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
*
*
* hw - Struct containing variables accessed by shared code
* frame_len - The length of the frame in question
* mac_addr - The Ethernet destination address of the frame in question
......@@ -4131,16 +4132,16 @@ e1000_tbi_adjust_stats(struct e1000_hw *hw,
carry_bit = 0x80000000 & stats->gorcl;
stats->gorcl += frame_len;
/* If the high bit of Gorcl (the low 32 bits of the Good Octets
* Received Count) was one before the addition,
* AND it is zero after, then we lost the carry out,
* Received Count) was one before the addition,
* AND it is zero after, then we lost the carry out,
* need to add one to Gorch (Good Octets Received Count High).
* This could be simplified if all environments supported
* This could be simplified if all environments supported
* 64-bit integers.
*/
if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
stats->gorch++;
/* Is this a broadcast or multicast? Check broadcast first,
* since the test for a multicast frame will test positive on
* since the test for a multicast frame will test positive on
* a broadcast frame.
*/
if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
......
drivers/net/e1000/e1000_hw.h
View file @ 8bf752eb
......@@ -33,6 +33,7 @@
#ifndef _E1000_HW_H_
#define _E1000_HW_H_
#include "e1000_osdep.h"
/* Forward declarations of structures used by the shared code */
......@@ -290,6 +291,7 @@ uint32_t e1000_io_read(struct e1000_hw *hw, uint32_t port);
uint32_t e1000_read_reg_io(struct e1000_hw *hw, uint32_t offset);
void e1000_io_write(struct e1000_hw *hw, uint32_t port, uint32_t value);
void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
#define E1000_READ_REG_IO(a, reg) \
e1000_read_reg_io((a), E1000_##reg)
#define E1000_WRITE_REG_IO(a, reg, val) \
......@@ -360,7 +362,7 @@ void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
/* This defines the bits that are set in the Interrupt Mask
* Set/Read Register. Each bit is documented below:
* o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
* o RXSEQ = Receive Sequence Error
* o RXSEQ = Receive Sequence Error
*/
#define POLL_IMS_ENABLE_MASK ( \
E1000_IMS_RXDMT0 | \
......@@ -585,7 +587,7 @@ struct e1000_ffvt_entry {
/* Register Set. (82543, 82544)
*
* Registers are defined to be 32 bits and should be accessed as 32 bit values.
* These registers are physically located on the NIC, but are mapped into the
* These registers are physically located on the NIC, but are mapped into the
* host memory address space.
*
* RW - register is both readable and writable
......@@ -1374,7 +1376,7 @@ struct e1000_hw {
#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
* Filtering */
#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
......@@ -1555,26 +1557,26 @@ struct e1000_hw {
/* The number of bits that we need to shift right to move the "pause"
* bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
* in the TXCW register
* in the TXCW register
*/
#define PAUSE_SHIFT 5
/* The number of bits that we need to shift left to move the "SWDPIO"
* bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
* in the CTRL register
* in the CTRL register
*/
#define SWDPIO_SHIFT 17
/* The number of bits that we need to shift left to move the "SWDPIO_EXT"
* bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
* Extended CTRL register.
* in the CTRL register
* in the CTRL register
*/
#define SWDPIO__EXT_SHIFT 4
/* The number of bits that we need to shift left to move the "ILOS"
* bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
* in the CTRL register
* in the CTRL register
*/
#define ILOS_SHIFT 3
......@@ -1592,7 +1594,7 @@ struct e1000_hw {
/* TBI_ACCEPT macro definition:
*
* This macro requires:
* adapter = a pointer to struct e1000_hw
* adapter = a pointer to struct e1000_hw
* status = the 8 bit status field of the RX descriptor with EOP set
* error = the 8 bit error field of the RX descriptor with EOP set
* length = the sum of all the length fields of the RX descriptors that
......@@ -1601,7 +1603,7 @@ struct e1000_hw {
* max_frame_length = the maximum frame length we want to accept.
* min_frame_length = the minimum frame length we want to accept.
*
* This macro is a conditional that should be used in the interrupt
* This macro is a conditional that should be used in the interrupt
* handler's Rx processing routine when RxErrors have been detected.
*
* Typical use:
......@@ -1748,7 +1750,7 @@ struct e1000_hw {
#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
#define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */
#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
/* Next Page TX Register */
#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
......@@ -1759,7 +1761,7 @@ struct e1000_hw {
* 0 = cannot comply with msg
*/
#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
* 0 = sending last NP
*/
......@@ -1768,13 +1770,13 @@ struct e1000_hw {
#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
* of different NP
*/
#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
* 0 = cannot comply with msg
*/
#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
* 0 = sending last NP
* 0 = sending last NP
*/
/* 1000BASE-T Control Register */
......@@ -1821,20 +1823,20 @@ struct e1000_hw {
#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
* 0=CLK125 toggling
*/
#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
/* Manual MDI configuration */
#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
* 100BASE-TX/10BASE-T:
* 100BASE-TX/10BASE-T:
* MDI Mode
*/
#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
* all speeds.
#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
* all speeds.
*/
#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
/* 1=Enable Extended 10BASE-T distance
* (Lower 10BASE-T RX Threshold)
* 0=Normal 10BASE-T RX Threshold */
......@@ -1875,12 +1877,12 @@ struct e1000_hw {
#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
* Will assert lost lock and bring
* link down if idle not seen
* within 1ms in 1000BASE-T
* within 1ms in 1000BASE-T
*/
/* Number of times we will attempt to autonegotiate before downshifting if we
* are the master */
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
......
drivers/net/e1000/e1000_main.c
View file @ 8bf752eb
......@@ -189,6 +189,7 @@ struct notifier_block e1000_notifier_reboot = {
.priority = 0
};
/* Exported from other modules */
extern void e1000_check_options(struct e1000_adapter *adapter);
......@@ -554,6 +555,7 @@ e1000_remove(struct pci_dev *pdev)
e1000_phy_hw_reset(&adapter->hw);
iounmap(adapter->hw.hw_addr);
pci_release_regions(pdev);
......@@ -589,7 +591,7 @@ e1000_sw_init(struct e1000_adapter *adapter)
adapter->rx_buffer_len = E1000_RXBUFFER_2048;
hw->max_frame_size = netdev->mtu +
ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
/* identify the MAC */
......@@ -810,7 +812,7 @@ e1000_configure_tx(struct e1000_adapter *adapter)
tctl &= ~E1000_TCTL_CT;
tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
......@@ -880,8 +882,8 @@ e1000_setup_rctl(struct e1000_adapter *adapter)
rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
(adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
(adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
if(adapter->hw.tbi_compatibility_on == 1)
rctl |= E1000_RCTL_SBP;
......@@ -1374,7 +1376,7 @@ e1000_tso(struct e1000_adapter *adapter, struct sk_buff *skb, int tx_flags)
int i;
uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
uint16_t ipcse, tucse, mss;
if(skb_shinfo(skb)->tso_size) {
hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
mss = skb_shinfo(skb)->tso_size;
......@@ -1394,7 +1396,7 @@ e1000_tso(struct e1000_adapter *adapter, struct sk_buff *skb, int tx_flags)
i = adapter->tx_ring.next_to_use;
context_desc = E1000_CONTEXT_DESC(adapter->tx_ring, i);
context_desc->lower_setup.ip_fields.ipcss = ipcss;
context_desc->lower_setup.ip_fields.ipcso = ipcso;
context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
......@@ -2535,6 +2537,7 @@ e1000_notify_reboot(struct notifier_block *nb, unsigned long event, void *p)
return NOTIFY_DONE;
}
static int
e1000_suspend(struct pci_dev *pdev, uint32_t state)
{
......
drivers/net/e1000/e1000_param.c
View file @ 8bf752eb
......@@ -169,7 +169,7 @@ E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");
*
* Valid Range: 0-65535
*
* Default Value: 0/128
* Default Value: 0
*/
E1000_PARAM(RxIntDelay, "Receive Interrupt Delay");
......@@ -309,7 +309,7 @@ e1000_check_options(struct e1000_adapter *adapter)
.name = "Transmit Descriptors",
.err = "using default of " __MODULE_STRING(DEFAULT_TXD),
.def = DEFAULT_TXD,
.arg = { .r = { .min = MIN_TXD }}
.arg = { .r { .min = MIN_TXD }}
};
struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
e1000_mac_type mac_type = adapter->hw.mac_type;
......@@ -362,7 +362,8 @@ e1000_check_options(struct e1000_adapter *adapter)
.name = "Flow Control",
.err = "reading default settings from EEPROM",
.def = e1000_fc_default,
.arg = { .l = { .nr = ARRAY_SIZE(fc_list), .p = fc_list }}
.arg = { .l = { .nr = ARRAY_SIZE(fc_list),
.p = fc_list }}
};
int fc = FlowControl[bd];
......@@ -370,58 +371,57 @@ e1000_check_options(struct e1000_adapter *adapter)
adapter->hw.fc = adapter->hw.original_fc = fc;
}
{ /* Transmit Interrupt Delay */
char *tidv = "using default of " __MODULE_STRING(DEFAULT_TIDV);
struct e1000_option opt = {
.type = range_option,
.name = "Transmit Interrupt Delay",
.arg = { .r = { .min = MIN_TXDELAY, .max = MAX_TXDELAY }}
.err = "using default of " __MODULE_STRING(DEFAULT_TIDV),
.def = DEFAULT_TIDV,
.arg = { .r = { .min = MIN_TXDELAY,
.max = MAX_TXDELAY }}
};
opt.def = DEFAULT_TIDV;
opt.err = tidv;
adapter->tx_int_delay = TxIntDelay[bd];
e1000_validate_option(&adapter->tx_int_delay, &opt);
}
{ /* Transmit Absolute Interrupt Delay */
char *tadv = "using default of " __MODULE_STRING(DEFAULT_TADV);
struct e1000_option opt = {
.type = range_option,
.name = "Transmit Absolute Interrupt Delay",
.arg = { .r = { .min = MIN_TXABSDELAY, .max = MAX_TXABSDELAY }}
.err = "using default of " __MODULE_STRING(DEFAULT_TADV),
.def = DEFAULT_TADV,
.arg = { .r = { .min = MIN_TXABSDELAY,
.max = MAX_TXABSDELAY }}
};
opt.def = DEFAULT_TADV;
opt.err = tadv;
adapter->tx_abs_int_delay = TxAbsIntDelay[bd];
e1000_validate_option(&adapter->tx_abs_int_delay, &opt);
}
{ /* Receive Interrupt Delay */
char *rdtr = "using default of " __MODULE_STRING(DEFAULT_RDTR);
struct e1000_option opt = {
.type = range_option,
.name = "Receive Interrupt Delay",
.arg = { .r = { .min = MIN_RXDELAY, .max = MAX_RXDELAY }}
.err = "using default of " __MODULE_STRING(DEFAULT_RDTR),
.def = DEFAULT_RDTR,
.arg = { .r = { .min = MIN_RXDELAY,
.max = MAX_RXDELAY }}
};
opt.def = DEFAULT_RDTR;
opt.err = rdtr;
adapter->rx_int_delay = RxIntDelay[bd];
e1000_validate_option(&adapter->rx_int_delay, &opt);
}
{ /* Receive Absolute Interrupt Delay */
char *radv = "using default of " __MODULE_STRING(DEFAULT_RADV);
struct e1000_option opt = {
.type = range_option,
.name = "Receive Absolute Interrupt Delay",
.arg = { .r = { .min = MIN_RXABSDELAY, .max = MAX_RXABSDELAY }}
.err = "using default of " __MODULE_STRING(DEFAULT_RADV),
.def = DEFAULT_RADV,
.arg = { .r = { .min = MIN_RXABSDELAY,
.max = MAX_RXABSDELAY }}
};
opt.def = DEFAULT_RADV;
opt.err = radv;
adapter->rx_abs_int_delay = RxAbsIntDelay[bd];
e1000_validate_option(&adapter->rx_abs_int_delay, &opt);
}
switch(adapter->hw.media_type) {
case e1000_media_type_fiber:
e1000_check_fiber_options(adapter);
......@@ -486,7 +486,8 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
.name = "Speed",
.err = "parameter ignored",
.def = 0,
.arg = { .l = { .nr = ARRAY_SIZE(speed_list), .p = speed_list }}
.arg = { .l = { .nr = ARRAY_SIZE(speed_list),
.p = speed_list }}
};
speed = Speed[bd];
......@@ -502,7 +503,8 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
.name = "Duplex",
.err = "parameter ignored",
.def = 0,
.arg = { .l = { .nr = ARRAY_SIZE(dplx_list), .p = dplx_list }}
.arg = { .l = { .nr = ARRAY_SIZE(dplx_list),
.p = dplx_list }}
};
dplx = Duplex[bd];
......@@ -554,7 +556,8 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
.name = "AutoNeg",
.err = "parameter ignored",
.def = AUTONEG_ADV_DEFAULT,
.arg = { .l = { .nr = ARRAY_SIZE(an_list), .p = an_list }}
.arg = { .l = { .nr = ARRAY_SIZE(an_list),
.p = an_list }}
};
int an = AutoNeg[bd];
......
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