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nexedi
linux
Commits
8f3fb748
Commit
8f3fb748
authored
Jul 10, 2003
by
Linus Torvalds
Browse files
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Plain Diff
Update radeon driver from DRI CVS: add more commands.
(version 1.8.0 -> 1.9.0)
parent
fb4b152a
Changes
5
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Showing
5 changed files
with
35 additions
and
37 deletions
+35
-37
drivers/char/drm/radeon.h
drivers/char/drm/radeon.h
+1
-1
drivers/char/drm/radeon_drm.h
drivers/char/drm/radeon_drm.h
+4
-1
drivers/char/drm/radeon_drv.c
drivers/char/drm/radeon_drv.c
+8
-5
drivers/char/drm/radeon_drv.h
drivers/char/drm/radeon_drv.h
+4
-0
drivers/char/drm/radeon_state.c
drivers/char/drm/radeon_state.c
+18
-30
No files found.
drivers/char/drm/radeon.h
View file @
8f3fb748
...
@@ -51,7 +51,7 @@
...
@@ -51,7 +51,7 @@
#define DRIVER_DATE "20020828"
#define DRIVER_DATE "20020828"
#define DRIVER_MAJOR 1
#define DRIVER_MAJOR 1
#define DRIVER_MINOR
8
#define DRIVER_MINOR
9
#define DRIVER_PATCHLEVEL 0
#define DRIVER_PATCHLEVEL 0
/* Interface history:
/* Interface history:
...
...
drivers/char/drm/radeon_drm.h
View file @
8f3fb748
...
@@ -141,7 +141,10 @@
...
@@ -141,7 +141,10 @@
#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
#define R200_EMIT_PP_CUBIC_FACES_5 71
#define R200_EMIT_PP_CUBIC_FACES_5 71
#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
#define RADEON_MAX_STATE_PACKETS 73
#define RADEON_EMIT_PP_TEX_SIZE_0 73
#define RADEON_EMIT_PP_TEX_SIZE_1 74
#define RADEON_EMIT_PP_TEX_SIZE_2 75
#define RADEON_MAX_STATE_PACKETS 76
/* Commands understood by cmd_buffer ioctl. More can be added but
/* Commands understood by cmd_buffer ioctl. More can be added but
...
...
drivers/char/drm/radeon_drv.c
View file @
8f3fb748
/* radeon_drv.c -- ATI Radeon driver -*- linux-c -*-
/**
* Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
* \file radeon_drv.c
* ATI Radeon driver
*
*
* \author Gareth Hughes <gareth@valinux.com>
*/
/*
* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
* All Rights Reserved.
* All Rights Reserved.
*
*
...
@@ -22,11 +27,9 @@
...
@@ -22,11 +27,9 @@
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors:
* Gareth Hughes <gareth@valinux.com>
*/
*/
#include <linux/config.h>
#include <linux/config.h>
#include "radeon.h"
#include "radeon.h"
#include "drmP.h"
#include "drmP.h"
...
...
drivers/char/drm/radeon_drv.h
View file @
8f3fb748
...
@@ -669,6 +669,10 @@ extern void radeon_do_release(drm_device_t *dev);
...
@@ -669,6 +669,10 @@ extern void radeon_do_release(drm_device_t *dev);
#define R200_RE_POINTSIZE 0x2648
#define R200_RE_POINTSIZE 0x2648
#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
#define RADEON_PP_TEX_SIZE_0 0x1d04
/* NPOT */
#define RADEON_PP_TEX_SIZE_1 0x1d0c
#define RADEON_PP_TEX_SIZE_2 0x1d14
#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
...
...
drivers/char/drm/radeon_state.c
View file @
8f3fb748
...
@@ -292,6 +292,9 @@ static struct {
...
@@ -292,6 +292,9 @@ static struct {
{
R200_PP_CUBIC_OFFSET_F1_4
,
5
,
"R200_PP_CUBIC_OFFSET_F1_4"
},
{
R200_PP_CUBIC_OFFSET_F1_4
,
5
,
"R200_PP_CUBIC_OFFSET_F1_4"
},
{
R200_PP_CUBIC_FACES_5
,
1
,
"R200_PP_CUBIC_FACES_5"
},
{
R200_PP_CUBIC_FACES_5
,
1
,
"R200_PP_CUBIC_FACES_5"
},
{
R200_PP_CUBIC_OFFSET_F1_5
,
5
,
"R200_PP_CUBIC_OFFSET_F1_5"
},
{
R200_PP_CUBIC_OFFSET_F1_5
,
5
,
"R200_PP_CUBIC_OFFSET_F1_5"
},
{
RADEON_PP_TEX_SIZE_0
,
2
,
"RADEON_PP_TEX_SIZE_0"
},
{
RADEON_PP_TEX_SIZE_1
,
2
,
"RADEON_PP_TEX_SIZE_1"
},
{
RADEON_PP_TEX_SIZE_2
,
2
,
"RADEON_PP_TEX_SIZE_1"
},
};
};
...
@@ -885,15 +888,14 @@ typedef struct {
...
@@ -885,15 +888,14 @@ typedef struct {
static
void
radeon_cp_dispatch_vertex
(
drm_device_t
*
dev
,
static
void
radeon_cp_dispatch_vertex
(
drm_device_t
*
dev
,
drm_buf_t
*
buf
,
drm_buf_t
*
buf
,
drm_radeon_tcl_prim_t
*
prim
,
drm_radeon_tcl_prim_t
*
prim
)
drm_clip_rect_t
*
boxes
,
int
nbox
)
{
{
drm_radeon_private_t
*
dev_priv
=
dev
->
dev_private
;
drm_radeon_private_t
*
dev_priv
=
dev
->
dev_private
;
drm_
clip_rect_t
box
;
drm_
radeon_sarea_t
*
sarea_priv
=
dev_priv
->
sarea_priv
;
int
offset
=
dev_priv
->
agp_buffers_offset
+
buf
->
offset
+
prim
->
start
;
int
offset
=
dev_priv
->
agp_buffers_offset
+
buf
->
offset
+
prim
->
start
;
int
numverts
=
(
int
)
prim
->
numverts
;
int
numverts
=
(
int
)
prim
->
numverts
;
int
nbox
=
sarea_priv
->
nbox
;
int
i
=
0
;
int
i
=
0
;
RING_LOCALS
;
RING_LOCALS
;
...
@@ -913,10 +915,8 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
...
@@ -913,10 +915,8 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
do
{
do
{
/* Emit the next cliprect */
/* Emit the next cliprect */
if
(
i
<
nbox
)
{
if
(
i
<
nbox
)
{
if
(
DRM_COPY_FROM_USER_UNCHECKED
(
&
box
,
&
boxes
[
i
],
sizeof
(
box
)
))
radeon_emit_clip_rect
(
dev_priv
,
return
;
&
sarea_priv
->
boxes
[
i
]
);
radeon_emit_clip_rect
(
dev_priv
,
&
box
);
}
}
/* Emit the vertex buffer rendering commands */
/* Emit the vertex buffer rendering commands */
...
@@ -995,18 +995,17 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
...
@@ -995,18 +995,17 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
static
void
radeon_cp_dispatch_indices
(
drm_device_t
*
dev
,
static
void
radeon_cp_dispatch_indices
(
drm_device_t
*
dev
,
drm_buf_t
*
elt_buf
,
drm_buf_t
*
elt_buf
,
drm_radeon_tcl_prim_t
*
prim
,
drm_radeon_tcl_prim_t
*
prim
)
drm_clip_rect_t
*
boxes
,
int
nbox
)
{
{
drm_radeon_private_t
*
dev_priv
=
dev
->
dev_private
;
drm_radeon_private_t
*
dev_priv
=
dev
->
dev_private
;
drm_
clip_rect_t
box
;
drm_
radeon_sarea_t
*
sarea_priv
=
dev_priv
->
sarea_priv
;
int
offset
=
dev_priv
->
agp_buffers_offset
+
prim
->
offset
;
int
offset
=
dev_priv
->
agp_buffers_offset
+
prim
->
offset
;
u32
*
data
;
u32
*
data
;
int
dwords
;
int
dwords
;
int
i
=
0
;
int
i
=
0
;
int
start
=
prim
->
start
+
RADEON_INDEX_PRIM_OFFSET
;
int
start
=
prim
->
start
+
RADEON_INDEX_PRIM_OFFSET
;
int
count
=
(
prim
->
finish
-
start
)
/
sizeof
(
u16
);
int
count
=
(
prim
->
finish
-
start
)
/
sizeof
(
u16
);
int
nbox
=
sarea_priv
->
nbox
;
DRM_DEBUG
(
"hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d
\n
"
,
DRM_DEBUG
(
"hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d
\n
"
,
prim
->
prim
,
prim
->
prim
,
...
@@ -1045,12 +1044,9 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
...
@@ -1045,12 +1044,9 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
(
count
<<
RADEON_NUM_VERTICES_SHIFT
)
);
(
count
<<
RADEON_NUM_VERTICES_SHIFT
)
);
do
{
do
{
if
(
i
<
nbox
)
{
if
(
i
<
nbox
)
if
(
DRM_COPY_FROM_USER_UNCHECKED
(
&
box
,
&
boxes
[
i
],
sizeof
(
box
)
))
radeon_emit_clip_rect
(
dev_priv
,
return
;
&
sarea_priv
->
boxes
[
i
]
);
radeon_emit_clip_rect
(
dev_priv
,
&
box
);
}
radeon_cp_dispatch_indirect
(
dev
,
elt_buf
,
radeon_cp_dispatch_indirect
(
dev
,
elt_buf
,
prim
->
start
,
prim
->
start
,
...
@@ -1450,9 +1446,7 @@ int radeon_cp_vertex( DRM_IOCTL_ARGS )
...
@@ -1450,9 +1446,7 @@ int radeon_cp_vertex( DRM_IOCTL_ARGS )
prim
.
numverts
=
vertex
.
count
;
prim
.
numverts
=
vertex
.
count
;
prim
.
vc_format
=
dev_priv
->
sarea_priv
->
vc_format
;
prim
.
vc_format
=
dev_priv
->
sarea_priv
->
vc_format
;
radeon_cp_dispatch_vertex
(
dev
,
buf
,
&
prim
,
radeon_cp_dispatch_vertex
(
dev
,
buf
,
&
prim
);
dev_priv
->
sarea_priv
->
boxes
,
dev_priv
->
sarea_priv
->
nbox
);
}
}
if
(
vertex
.
discard
)
{
if
(
vertex
.
discard
)
{
...
@@ -1550,9 +1544,7 @@ int radeon_cp_indices( DRM_IOCTL_ARGS )
...
@@ -1550,9 +1544,7 @@ int radeon_cp_indices( DRM_IOCTL_ARGS )
prim
.
numverts
=
RADEON_MAX_VB_VERTS
;
/* duh */
prim
.
numverts
=
RADEON_MAX_VB_VERTS
;
/* duh */
prim
.
vc_format
=
dev_priv
->
sarea_priv
->
vc_format
;
prim
.
vc_format
=
dev_priv
->
sarea_priv
->
vc_format
;
radeon_cp_dispatch_indices
(
dev
,
buf
,
&
prim
,
radeon_cp_dispatch_indices
(
dev
,
buf
,
&
prim
);
dev_priv
->
sarea_priv
->
boxes
,
dev_priv
->
sarea_priv
->
nbox
);
if
(
elts
.
discard
)
{
if
(
elts
.
discard
)
{
radeon_cp_discard_buffer
(
dev
,
buf
);
radeon_cp_discard_buffer
(
dev
,
buf
);
}
}
...
@@ -1769,16 +1761,12 @@ int radeon_cp_vertex2( DRM_IOCTL_ARGS )
...
@@ -1769,16 +1761,12 @@ int radeon_cp_vertex2( DRM_IOCTL_ARGS )
tclprim
.
offset
=
prim
.
numverts
*
64
;
tclprim
.
offset
=
prim
.
numverts
*
64
;
tclprim
.
numverts
=
RADEON_MAX_VB_VERTS
;
/* duh */
tclprim
.
numverts
=
RADEON_MAX_VB_VERTS
;
/* duh */
radeon_cp_dispatch_indices
(
dev
,
buf
,
&
tclprim
,
radeon_cp_dispatch_indices
(
dev
,
buf
,
&
tclprim
);
sarea_priv
->
boxes
,
sarea_priv
->
nbox
);
}
else
{
}
else
{
tclprim
.
numverts
=
prim
.
numverts
;
tclprim
.
numverts
=
prim
.
numverts
;
tclprim
.
offset
=
0
;
/* not used */
tclprim
.
offset
=
0
;
/* not used */
radeon_cp_dispatch_vertex
(
dev
,
buf
,
&
tclprim
,
radeon_cp_dispatch_vertex
(
dev
,
buf
,
&
tclprim
);
sarea_priv
->
boxes
,
sarea_priv
->
nbox
);
}
}
if
(
sarea_priv
->
nbox
==
1
)
if
(
sarea_priv
->
nbox
==
1
)
...
...
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