drm/amd/display: Remove DCE12 guards

Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

@@ -1987,9 +1987,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
 	case CHIP_POLARIS12:
 	case CHIP_TONGA:
 	case CHIP_FIJI:
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	case CHIP_VEGA10:
-#endif
 #if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)
 		return amdgpu_dc != 0;
 #else

drivers/gpu/drm/amd/display/Kconfig

@@ -17,13 +17,6 @@ config DRM_AMD_DC_PRE_VEGA
 	  by default. This includes Polaris, Carrizo, Tonga, Bonaire,
 	  and Hawaii.
 
-config DRM_AMD_DC_DCE12_0
-        bool "Vega10 family"
-        depends on DRM_AMD_DC
-        help
-         Choose this option if you want to have
-         VG family for display engine.
-
 config DEBUG_KERNEL_DC
 	bool "Enable kgdb break in DC"
 	depends on DRM_AMD_DC

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

@@ -1123,9 +1123,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 	case CHIP_POLARIS11:
 	case CHIP_POLARIS10:
 	case CHIP_POLARIS12:
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	case CHIP_VEGA10:
-#endif
 		if (dce110_register_irq_handlers(dm->adev)) {
 			DRM_ERROR("DM: Failed to initialize IRQ\n");
 			return -1;
@@ -1392,13 +1390,11 @@ static int dm_early_init(void *handle)
 		adev->mode_info.num_hpd = 6;
 		adev->mode_info.num_dig = 6;
 		break;
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	case CHIP_VEGA10:
 		adev->mode_info.num_crtc = 6;
 		adev->mode_info.num_hpd = 6;
 		adev->mode_info.num_dig = 6;
 		break;
-#endif
 	default:
 		DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
 		return -EINVAL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c

@@ -402,7 +402,6 @@ bool dm_pp_notify_wm_clock_changes(
 	return false;
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 bool dm_pp_notify_wm_clock_changes_soc15(
 	const struct dc_context *ctx,
 	struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
@@ -410,7 +409,6 @@ bool dm_pp_notify_wm_clock_changes_soc15(
 	/* TODO: to be implemented */
 	return false;
 }
-#endif
 
 bool dm_pp_apply_power_level_change_request(
 	const struct dc_context *ctx,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c

@@ -523,7 +523,6 @@ static void fill_plane_attributes_from_fb(
 	surface->tiling_info.gfx8.pipe_config =
 			AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
 
-#if defined (CONFIG_DRM_AMD_DC_DCE12_0)
 	if (adev->asic_type == CHIP_VEGA10) {
 		/* Fill GFX9 params */
 		surface->tiling_info.gfx9.num_pipes =
@@ -540,7 +539,6 @@ static void fill_plane_attributes_from_fb(
 			AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
 		surface->tiling_info.gfx9.shaderEnable = 1;
 	}
-#endif
 
 
 	surface->plane_size.grph.surface_size.x = 0;

drivers/gpu/drm/amd/display/dc/Makefile

@@ -4,10 +4,7 @@
 
 DC_LIBS = basics bios calcs dce gpio i2caux irq virtual
 
-ifdef CONFIG_DRM_AMD_DC_DCE12_0
 DC_LIBS += dce120
-endif
-
 DC_LIBS += dce112
 DC_LIBS += dce110
 DC_LIBS += dce100

drivers/gpu/drm/amd/display/dc/bios/Makefile

@@ -4,9 +4,7 @@
 
 BIOS = bios_parser.o bios_parser_interface.o  bios_parser_helper.o command_table.o command_table_helper.o
 
-ifdef CONFIG_DRM_AMD_DC_DCE12_0
 BIOS += command_table2.o command_table_helper2.o bios_parser2.o
-endif
 
 AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
 
@@ -26,6 +24,4 @@ AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce110/command_table_helper_dce110.o
 
 AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper_dce112.o
 
-ifdef CONFIG_DRM_AMD_DC_DCE12_0
 AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper2_dce112.o
-endif

drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c

@@ -29,9 +29,7 @@
 #include "bios_parser_interface.h"
 #include "bios_parser.h"
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #include "bios_parser2.h"
-#endif
 
 
 struct dc_bios *dal_bios_parser_create(
@@ -40,17 +38,11 @@ struct dc_bios *dal_bios_parser_create(
 {
 	struct dc_bios *bios = NULL;
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	bios = firmware_parser_create(init, dce_version);
 
+	/* Fall back to old bios parser for older asics */
 	if (bios == NULL)
-		/* TODO: remove dce_version from bios_parser.
-		 * cannot remove today because dal enum to bp enum translation is dce specific
-		 */
-		bios = bios_parser_create(init, dce_version);
-#else
 		bios = bios_parser_create(init, dce_version);
-#endif
 
 	return bios;
 }

drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c

@@ -53,11 +53,9 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
 	case DCE_VERSION_11_2:
 		*h = dal_cmd_tbl_helper_dce112_get_table2();
 		return true;
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	case DCE_VERSION_12_0:
 		*h = dal_cmd_tbl_helper_dce112_get_table2();
 		return true;
-#endif
 
 	default:
 		/* Unsupported DCE */

drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c

@@ -50,10 +50,8 @@ static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asi
 			return BW_CALCS_VERSION_POLARIS11;
 		return BW_CALCS_VERSION_INVALID;
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	case FAMILY_AI:
 		return BW_CALCS_VERSION_VEGA10;
-#endif
 
 	default:
 		return BW_CALCS_VERSION_INVALID;
@@ -2435,7 +2433,6 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
 		dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
 		dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
 		break;
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	case BW_CALCS_VERSION_VEGA10:
 		vbios.memory_type = bw_def_hbm;
 		vbios.dram_channel_width_in_bits = 128;
@@ -2546,7 +2543,6 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
 		dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
 		dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
 		break;
-#endif
 	default:
 		break;
 	}

drivers/gpu/drm/amd/display/dc/core/dc.c

@@ -1815,7 +1815,6 @@ void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink
 	}
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
 {
 	int i;
@@ -1842,5 +1841,4 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
 	return true;
 
 }
-#endif
 

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

@@ -142,10 +142,8 @@ void pre_surface_trace(
 				surface->rotation,
 				surface->stereo_format);
 
-#if defined (CONFIG_DRM_AMD_DC_DCE12_0)
 		SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
 				surface->tiling_info.gfx9.swizzle);
-#endif
 
 		SURFACE_TRACE("\n");
 	}
@@ -228,10 +226,8 @@ void update_surface_trace(
 					update->plane_info->tiling_info.gfx8.array_mode,
 					update->plane_info->visible);
 
-			#if defined (CONFIG_DRM_AMD_DC_DCE12_0)
 			SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
 					update->plane_info->tiling_info.gfx9.swizzle);
-			#endif
 		}
 
 		if (update->scaling_info) {

drivers/gpu/drm/amd/display/dc/core/dc_link.c

@@ -1217,7 +1217,6 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
 				pipe_ctx->dis_clk->funcs->set_min_clocks_state(
 					pipe_ctx->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL);
 		} else {
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 			uint32_t dp_phyclk_in_khz;
 			const struct clocks_value clocks_value =
 					pipe_ctx->dis_clk->cur_clocks_value;
@@ -1235,7 +1234,6 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
 						false,
 						true);
 			}
-#endif
 		}
 	}
 

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

@@ -39,9 +39,7 @@
 #include "dce100/dce100_resource.h"
 #include "dce110/dce110_resource.h"
 #include "dce112/dce112_resource.h"
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #include "dce120/dce120_resource.h"
-#endif
 
 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
 {
@@ -68,11 +66,9 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
 			dc_version = DCE_VERSION_11_2;
 		}
 		break;
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	case FAMILY_AI:
 		dc_version = DCE_VERSION_12_0;
 		break;
-#endif
 	default:
 		dc_version = DCE_VERSION_UNKNOWN;
 		break;
@@ -105,12 +101,10 @@ struct resource_pool *dc_create_resource_pool(
 		res_pool = dce112_create_resource_pool(
 			num_virtual_links, dc);
 		break;
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	case DCE_VERSION_12_0:
 		res_pool = dce120_create_resource_pool(
 			num_virtual_links, dc);
 		break;
-#endif
 	default:
 		break;
 	}

drivers/gpu/drm/amd/display/dc/dc.h

@@ -55,9 +55,7 @@ struct dc_caps {
 struct dc_dcc_surface_param {
 	enum surface_pixel_format format;
 	struct dc_size surface_size;
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	enum swizzle_mode_values swizzle_mode;
-#endif
 	enum dc_scan_direction scan;
 };
 
@@ -146,9 +144,7 @@ struct dc_debug {
 	bool disable_stutter;
 	bool disable_dcc;
 	bool disable_dfs_bypass;
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	bool disable_pplib_clock_request;
-#endif
 	bool disable_clock_gate;
 	bool disable_dmcu;
 	bool force_abm_enable;
@@ -163,7 +159,6 @@ struct dc {
 	struct dc_debug debug;
 };
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 enum frame_buffer_mode {
 	FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
 	FRAME_BUFFER_MODE_ZFB_ONLY,
@@ -178,7 +173,6 @@ struct dchub_init_data {
 	uint64_t zfb_size_in_byte;
 	enum frame_buffer_mode fb_mode;
 };
-#endif
 
 struct dc_init_data {
 	struct hw_asic_id asic_id;
@@ -200,9 +194,7 @@ struct dc *dc_create(const struct dc_init_data *init_params);
 
 void dc_destroy(struct dc **dc);
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data);
-#endif
 
 /*******************************************************************************
  * Surface Interfaces

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

@@ -259,7 +259,6 @@ enum tile_mode_values {
 	DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
 };
 
-#if defined (CONFIG_DRM_AMD_DC_DCE12_0)
 enum swizzle_mode_values {
 	DC_SW_LINEAR = 0,
 	DC_SW_256B_S = 1,
@@ -287,7 +286,6 @@ enum swizzle_mode_values {
 	DC_SW_VAR_R_X = 31,
 	DC_SW_MAX
 };
-#endif
 
 union dc_tiling_info {
 
@@ -353,7 +351,6 @@ union dc_tiling_info {
 		enum array_mode_values array_mode;
 	} gfx8;
 
-#if defined (CONFIG_DRM_AMD_DC_DCE12_0)
 	struct {
 		unsigned int num_pipes;
 		unsigned int num_banks;
@@ -368,7 +365,6 @@ union dc_tiling_info {
 		bool rb_aligned;
 		bool pipe_aligned;
 	} gfx9;
-#endif
 };
 
 /* Rotation angle */

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

@@ -585,9 +585,7 @@ static uint32_t dce110_get_pix_clk_dividers(
 			pll_settings, pix_clk_params);
 		break;
 	case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	case DCE_VERSION_12_0:
-#endif
 		dce112_get_pix_clk_dividers_helper(clk_src,
 				pll_settings, pix_clk_params);
 		break;
@@ -871,9 +869,7 @@ static bool dce110_program_pix_clk(
 
 		break;
 	case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	case DCE_VERSION_12_0:
-#endif
 		if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
 			bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
 							pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c

@@ -80,7 +80,6 @@ static struct state_dependent_clocks dce112_max_clks_by_state[] = {
 /*ClocksStatePerformance*/
 { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } };
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 static struct state_dependent_clocks dce120_max_clks_by_state[] = {
 /*ClocksStateInvalid - should not be used*/
 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
@@ -92,7 +91,6 @@ static struct state_dependent_clocks dce120_max_clks_by_state[] = {
 { .display_clk_khz = 670000, .pixel_clk_khz = 600000 },
 /*ClocksStatePerformance*/
 { .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } };
-#endif
 
 /* Starting point for each divider range.*/
 enum dce_divider_range_start {
@@ -497,7 +495,6 @@ static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce)
 	}
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 static bool dce_apply_clock_voltage_request(
 	struct display_clock *clk,
 	enum dm_pp_clock_type clocks_type,
@@ -592,7 +589,6 @@ static const struct display_clock_funcs dce120_funcs = {
 	.apply_clock_voltage_request = dce_apply_clock_voltage_request,
 	.set_clock = dce112_set_clock
 };
-#endif
 
 static const struct display_clock_funcs dce112_funcs = {
 	.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,
@@ -734,7 +730,6 @@ struct display_clock *dce112_disp_clk_create(
 	return &clk_dce->base;
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 struct display_clock *dce120_disp_clk_create(
 		struct dc_context *ctx,
 		const struct dce_disp_clk_registers *regs,
@@ -770,7 +765,6 @@ struct display_clock *dce120_disp_clk_create(
 
 	return &clk_dce->base;
 }
-#endif
 
 void dce_disp_clk_destroy(struct display_clock **disp_clk)
 {

drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h

@@ -45,13 +45,11 @@
 	CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
 	CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define CLK_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
 	CLK_SF(DCCG_DFS_DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
 	CLK_SF(DCCG_DFS_DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \
 	CLK_SF(DCCG_DFS_MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
 	CLK_SF(DCCG_DFS_MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
-#endif
 
 #define CLK_REG_FIELD_LIST(type) \
 	type DPREFCLK_SRC_SEL; \
@@ -126,10 +124,8 @@ struct dce_disp_clk {
 	int gpu_pll_ss_divider;
 
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	/* max disp_clk from PPLIB for max validation display clock*/
 	int max_displ_clk_in_khz;
-#endif
 };
 
 
@@ -151,13 +147,11 @@ struct display_clock *dce112_disp_clk_create(
 	const struct dce_disp_clk_shift *clk_shift,
 	const struct dce_disp_clk_mask *clk_mask);
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 struct display_clock *dce120_disp_clk_create(
 	struct dc_context *ctx,
 	const struct dce_disp_clk_registers *regs,
 	const struct dce_disp_clk_shift *clk_shift,
 	const struct dce_disp_clk_mask *clk_mask);
-#endif
 
 void dce_disp_clk_destroy(struct display_clock **disp_clk);
 

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h

@@ -186,13 +186,11 @@ struct dce_hwseq_registers {
 	HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
 	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\
 	HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\
 	HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\
 	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
 	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
-#endif
 
 #define HWSEQ_REG_FIED_LIST(type) \
 	type DCFE_CLOCK_ENABLE; \

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h

@@ -31,12 +31,10 @@
 #define TO_DCE110_LINK_ENC(link_encoder)\
 	container_of(link_encoder, struct dce110_link_encoder, base)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 /* Not found regs in dce120 spec
  * BIOS_SCRATCH_2
  * DP_DPHY_INTERNAL_CTRL
  */
-#endif
 
 #define AUX_REG_LIST(id)\
 	SRI(AUX_CONTROL, DP_AUX, id), \
@@ -86,14 +84,12 @@
 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
 	SR(DCI_MEM_PWR_STATUS)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
-	#define LE_DCE120_REG_LIST(id)\
+#define LE_DCE120_REG_LIST(id)\
 	LE_COMMON_REG_LIST_BASE(id), \
 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
 	SR(DCI_MEM_PWR_STATUS)
-#endif
 
-	#define LE_DCE80_REG_LIST(id)\
+#define LE_DCE80_REG_LIST(id)\
 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
 	LE_COMMON_REG_LIST_BASE(id)
 

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

@@ -187,7 +187,7 @@ static void program_nbp_watermark(struct mem_input *mi,
 		REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
 				NB_PSTATE_CHANGE_WATERMARK, nbp_wm);
 	}
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
+
 	if (REG(DPG_PIPE_LOW_POWER_CONTROL)) {
 		REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
 				PSTATE_CHANGE_WATERMARK_MASK, wm_select);
@@ -200,7 +200,6 @@ static void program_nbp_watermark(struct mem_input *mi,
 		REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL,
 				PSTATE_CHANGE_WATERMARK, nbp_wm);
 	}
-#endif
 }
 
 static void program_stutter_watermark(struct mem_input *mi,
@@ -210,12 +209,10 @@ static void program_stutter_watermark(struct mem_input *mi,
 	REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
 		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select);
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	if (REG(DPG_PIPE_STUTTER_CONTROL2))
 		REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2,
 				STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark);
 	else
-#endif
 		REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,
 				STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark);
 }
@@ -254,7 +251,6 @@ void dce_mem_input_program_display_marks(struct mem_input *mi,
 static void program_tiling(struct mem_input *mi,
 	const union dc_tiling_info *info)
 {
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	if (mi->masks->GRPH_SW_MODE) { /* GFX9 */
 		REG_UPDATE_6(GRPH_CONTROL,
 				GRPH_SW_MODE, info->gfx9.swizzle,
@@ -268,7 +264,7 @@ static void program_tiling(struct mem_input *mi,
 		GRPH_Z, 0);
 		 */
 	}
-#endif
+
 	if (mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */
 		REG_UPDATE_9(GRPH_CONTROL,
 				GRPH_NUM_BANKS, info->gfx8.num_banks,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

@@ -58,14 +58,12 @@
 	MI_DCE11_2_REG_LIST(id),\
 	MI_DCE_PTE_REG_LIST(id)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define MI_DCE12_REG_LIST(id)\
 	MI_DCE_BASE_REG_LIST(id),\
 	MI_DCE_PTE_REG_LIST(id),\
 	SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\
 	SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\
 	SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id)
-#endif
 
 struct dce_mem_input_registers {
 	/* DCP */
@@ -172,7 +170,6 @@ struct dce_mem_input_registers {
 	MI_DCE11_2_MASK_SH_LIST(mask_sh),\
 	MI_DCP_PTE_MASK_SH_LIST(mask_sh, )
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\
 	SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\
 	SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\
@@ -195,7 +192,6 @@ struct dce_mem_input_registers {
 	MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\
 	MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\
 	MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_)
-#endif
 
 #define MI_REG_FIELD_LIST(type) \
 	type GRPH_ENABLE; \

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

@@ -107,13 +107,11 @@ enum dce110_opp_reg_type {
 	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \
 	SRI(CONTROL, FMT_MEMORY, id)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define OPP_DCE_120_REG_LIST(id) \
 	OPP_COMMON_REG_LIST_BASE(id), \
 	SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
 	SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \
 	SRI(CONTROL, FMT_MEMORY, id)
-#endif
 
 #define OPP_SF(reg_name, field_name, post_fix)\
 	.field_name = reg_name ## __ ## field_name ## post_fix
@@ -205,7 +203,6 @@ enum dce110_opp_reg_type {
 	OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\
 	OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\
 	OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
 	OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
@@ -267,7 +264,6 @@ enum dce110_opp_reg_type {
 	OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\
 	OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\
 	OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh)
-#endif
 
 #define OPP_REG_FIELD_LIST(type) \
 	type DCP_REGAMMA_MEM_PWR_DIS; \

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

@@ -187,7 +187,6 @@
 #define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\
 	SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\
 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
 	SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
@@ -267,7 +266,6 @@
 	SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
 	SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
 	SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh)
-#endif
 
 #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
 	SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
@@ -294,7 +292,6 @@
 	SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
 	SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define SE_COMMON_MASK_SH_LIST_DCE120(mask_sh)\
 	SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
@@ -307,7 +304,6 @@
 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
 	SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\
 	SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
-#endif
 
 struct dce_stream_encoder_shift {
 	uint8_t AFMT_GENERIC_INDEX;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.h

@@ -153,7 +153,6 @@
 	XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
 	XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh)
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
 	XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \
 	XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \
@@ -219,7 +218,6 @@
 	XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
 	XFM_SF(DCFE0_DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
 	XFM_SF(SCL0_SCL_MODE, SCL_PSCL_EN, mask_sh)
-#endif
 
 #define XFM_REG_FIELD_LIST(type) \
 	type OUT_CLAMP_MIN_B_CB; \

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

@@ -1427,8 +1427,6 @@ static void apply_min_clocks(
 			return;
 		}
 
-		/* TODOFPGA */
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 		/* TODO: This is incorrect. Figure out how to fix. */
 		pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
 				pipe_ctx->dis_clk,
@@ -1451,7 +1449,6 @@ static void apply_min_clocks(
 				pre_mode_set,
 				false);
 		return;
-#endif
 	}
 
 	/* get the required state based on state dependent clocks:
@@ -1468,7 +1465,6 @@ static void apply_min_clocks(
 		pipe_ctx->dis_clk->funcs->set_min_clocks_state(
 			pipe_ctx->dis_clk, *clocks_state);
 	} else {
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 		pipe_ctx->dis_clk->funcs->apply_clock_voltage_request(
 				pipe_ctx->dis_clk,
 				DM_PP_CLOCK_TYPE_DISPLAY_CLK,
@@ -1489,7 +1485,6 @@ static void apply_min_clocks(
 				req_clocks.pixel_clk_khz,
 				pre_mode_set,
 				false);
-#endif
 	}
 }
 

drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c

@@ -409,9 +409,7 @@ static struct mem_input_funcs dce110_mem_input_funcs = {
 			dce_mem_input_program_surface_config,
 	.mem_input_is_flip_pending =
 			dce110_mem_input_is_flip_pending,
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	.mem_input_update_dchub = NULL
-#endif
 };
 /*****************************************/
 /* Constructor, Destructor               */

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h

@@ -108,9 +108,7 @@ struct dce110_timing_generator {
 	uint32_t min_h_front_porch;
 	uint32_t min_h_back_porch;
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	/* DCE 12 */
-#endif
 	uint32_t min_h_sync_width;
 	uint32_t min_v_sync_width;
 	uint32_t min_v_blank;

drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c

@@ -909,6 +909,7 @@ static bool construct(
 {
 	unsigned int i;
 	struct dc_context *ctx = dc->ctx;
+	struct irq_service_init_data irq_init_data;
 
 	ctx->dc_bios->regs = &bios_regs;
 
@@ -997,15 +998,10 @@ static bool construct(
 		goto res_create_fail;
 	}
 
-	{
-	#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
-		struct irq_service_init_data init_data;
-		init_data.ctx = dc->ctx;
-		pool->base.irqs = dal_irq_service_dce120_create(&init_data);
+	irq_init_data.ctx = dc->ctx;
+	pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data);
 	if (!pool->base.irqs)
 		goto irqs_create_fail;
-	#endif
-	}
 
 	for (i = 0; i < pool->base.pipe_count; i++) {
 		pool->base.timing_generators[i] =

drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c

@@ -54,9 +54,7 @@ static struct mem_input_funcs dce80_mem_input_funcs = {
 			dce_mem_input_program_surface_config,
 	.mem_input_is_flip_pending =
 			dce110_mem_input_is_flip_pending,
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	.mem_input_update_dchub = NULL
-#endif
 };
 
 /*****************************************/

drivers/gpu/drm/amd/display/dc/dm_services.h

@@ -192,7 +192,6 @@ unsigned int generic_reg_wait(const struct dc_context *ctx,
 	unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
 	const char *func_name);
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 
 /* These macros need to be used with soc15 registers in order to retrieve
  * the actual offset.
@@ -274,7 +273,6 @@ static inline bool wait_reg_func(
 		20000,\
 		200000)
 
-#endif
 /**************************************
  * Power Play (PP) interfaces
  **************************************/
@@ -337,11 +335,9 @@ bool dm_pp_notify_wm_clock_changes(
 	const struct dc_context *ctx,
 	struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 bool dm_pp_notify_wm_clock_changes_soc15(
 	const struct dc_context *ctx,
 	struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
-#endif
 
 /* DAL calls this function to notify PP about completion of Mode Set.
  * For PP it means that current DCE clocks are those which were returned

drivers/gpu/drm/amd/display/dc/dm_services_types.h

@@ -141,7 +141,6 @@ struct dm_pp_wm_sets_with_clock_ranges {
 	struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS];
 };
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 struct dm_pp_clock_range_for_dmif_wm_set_soc15 {
 	enum dm_pp_wm_set_id wm_set_id;
 	uint32_t wm_min_dcfclk_clk_in_khz;
@@ -166,7 +165,6 @@ struct dm_pp_wm_sets_with_clock_ranges_soc15 {
 	struct dm_pp_clock_range_for_mcif_wm_set_soc15
 		wm_mcif_clocks_ranges[MAX_WM_SETS];
 };
-#endif
 
 #define MAX_DISPLAY_CONFIGS 6
 

drivers/gpu/drm/amd/display/dc/gpio/Makefile

@@ -31,13 +31,11 @@ AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE110)
 ###############################################################################
 # DCE 12x
 ###############################################################################
-ifdef CONFIG_DRM_AMD_DC_DCE12_0
 GPIO_DCE120 = hw_translate_dce120.o hw_factory_dce120.o
 
 AMD_DAL_GPIO_DCE120 = $(addprefix $(AMDDALPATH)/dc/gpio/dce120/,$(GPIO_DCE120))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120)
-endif
 
 ###############################################################################
 # Diagnostics on FPGA

drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c

@@ -44,9 +44,7 @@
 
 #include "dce110/hw_factory_dce110.h"
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #include "dce120/hw_factory_dce120.h"
-#endif
 
 #include "diagnostics/hw_factory_diag.h"
 
@@ -76,11 +74,9 @@ bool dal_hw_factory_init(
 	case DCE_VERSION_11_2:
 		dal_hw_factory_dce110_init(factory);
 		return true;
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	case DCE_VERSION_12_0:
 		dal_hw_factory_dce120_init(factory);
 		return true;
-#endif
 	default:
 		ASSERT_CRITICAL(false);
 		return false;

drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c

@@ -42,9 +42,7 @@
 
 #include "dce80/hw_translate_dce80.h"
 #include "dce110/hw_translate_dce110.h"
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #include "dce120/hw_translate_dce120.h"
-#endif
 #include "diagnostics/hw_translate_diag.h"
 
 /*
@@ -70,11 +68,9 @@ bool dal_hw_translate_init(
 	case DCE_VERSION_11_2:
 		dal_hw_translate_dce110_init(translate);
 		return true;
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	case DCE_VERSION_12_0:
 		dal_hw_translate_dce120_init(translate);
 		return true;
-#endif
 	default:
 		BREAK_TO_DEBUGGER();
 		return false;

drivers/gpu/drm/amd/display/dc/i2caux/Makefile

@@ -50,13 +50,11 @@ AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE112)
 ###############################################################################
 # DCE 120 family
 ###############################################################################
-ifdef CONFIG_DRM_AMD_DC_DCE12_0
 I2CAUX_DCE120 = i2caux_dce120.o
 
 AMD_DAL_I2CAUX_DCE120 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce120/,$(I2CAUX_DCE120))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE120)
-endif
 
 ###############################################################################
 # Diagnostics on FPGA

drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c

@@ -57,9 +57,7 @@
 
 #include "dce112/i2caux_dce112.h"
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #include "dce120/i2caux_dce120.h"
-#endif
 
 #include "diagnostics/i2caux_diag.h"
 
@@ -84,10 +82,8 @@ struct i2caux *dal_i2caux_create(
 		return dal_i2caux_dce110_create(ctx);
 	case DCE_VERSION_10_0:
 		return dal_i2caux_dce100_create(ctx);
-	#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	case DCE_VERSION_12_0:
 		return dal_i2caux_dce120_create(ctx);
-	#endif
 	default:
 		BREAK_TO_DEBUGGER();
 		return NULL;

drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h

@@ -40,9 +40,7 @@ enum bw_calcs_version {
 	BW_CALCS_VERSION_POLARIS10,
 	BW_CALCS_VERSION_POLARIS11,
 	BW_CALCS_VERSION_STONEY,
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	BW_CALCS_VERSION_VEGA10
-#endif
 };
 
 /*******************************************************************************

drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h

@@ -28,7 +28,6 @@
 
 #include "dm_services_types.h"
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 struct clocks_value {
 	int dispclk_in_khz;
 	int max_pixelclk_in_khz;
@@ -38,7 +37,6 @@ struct clocks_value {
 	bool pixelclk_notify_pplib_done;
 	bool phyclk_notigy_pplib_done;
 };
-#endif
 
 /* Structure containing all state-dependent clocks
  * (dependent on "enum clocks_state") */
@@ -53,9 +51,7 @@ struct display_clock {
 
 	enum dm_pp_clocks_state max_clks_state;
 	enum dm_pp_clocks_state cur_min_clks_state;
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	struct clocks_value cur_clocks_value;
-#endif
 };
 
 struct display_clock_funcs {
@@ -71,14 +67,12 @@ struct display_clock_funcs {
 
 	int (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	bool (*apply_clock_voltage_request)(
 		struct display_clock *disp_clk,
 		enum dm_pp_clock_type clocks_type,
 		int clocks_in_khz,
 		bool pre_mode_set,
 		bool update_dp_phyclk);
-#endif
 };
 
 #endif /* __DISPLAY_CLOCK_H__ */

drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h

@@ -100,10 +100,8 @@ struct mem_input_funcs {
 
 	bool (*mem_input_is_flip_pending)(struct mem_input *mem_input);
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	void (*mem_input_update_dchub)(struct mem_input *mem_input,
 			struct dchub_init_data *dh_data);
-#endif
 };
 
 #endif

drivers/gpu/drm/amd/display/dc/irq/Makefile

@@ -30,11 +30,9 @@ AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE11)
 ###############################################################################
 # DCE 12x
 ###############################################################################
-ifdef CONFIG_DRM_AMD_DC_DCE12_0
 IRQ_DCE12 = irq_service_dce120.o
 
 AMD_DAL_IRQ_DCE12 = $(addprefix $(AMDDALPATH)/dc/irq/dce120/,$(IRQ_DCE12))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12)
-endif
 

drivers/gpu/drm/amd/display/dc/irq/irq_service.c

@@ -33,9 +33,7 @@
 
 #include "dce80/irq_service_dce80.h"
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #include "dce120/irq_service_dce120.h"
-#endif
 
 #include "reg_helper.h"
 #include "irq_service.h"

drivers/gpu/drm/amd/display/include/dal_asic_id.h

@@ -123,9 +123,7 @@
 #define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
 #define FAMILY_CZ 135 /* Carrizo */
 
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 #define FAMILY_AI 141
-#endif
 
 #define	FAMILY_UNKNOWN 0xFF
 

drivers/gpu/drm/amd/display/include/dal_types.h

@@ -38,9 +38,7 @@ enum dce_version {
 	DCE_VERSION_10_0,
 	DCE_VERSION_11_0,
 	DCE_VERSION_11_2,
-#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
 	DCE_VERSION_12_0,
-#endif
 	DCE_VERSION_MAX,
 };