Commit 930a784d authored by Oscar Mateo's avatar Oscar Mateo Committed by Chris Wilson

drm/i915: Use a mask when applying WaProgramL3SqcReg1Default

Otherwise we are blasting other bits in GEN8_L3SQCREG1 that might be important
(although we probably aren't at the moment because 0 seems to be the default
for all the other bits).

v2: Extra parentheses (Michel)

Fixes: 050fc465 ("drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf")
Fixes: 450174fe ("drm/i915/chv: Tune L3 SQC credits based on actual latencies")
Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: default avatarMichel Thierry <michel.thierry@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1508271945-14961-1-git-send-email-oscar.mateo@intel.comSigned-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent d6242aeb
...@@ -7041,6 +7041,7 @@ enum { ...@@ -7041,6 +7041,7 @@ enum {
*/ */
#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19) #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14) #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
#define GEN7_L3CNTLREG1 _MMIO(0xB01C) #define GEN7_L3CNTLREG1 _MMIO(0xB01C)
#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
......
...@@ -1253,9 +1253,12 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) ...@@ -1253,9 +1253,12 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
} }
/* WaProgramL3SqcReg1DefaultForPerf:bxt */ /* WaProgramL3SqcReg1DefaultForPerf:bxt */
if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | u32 val = I915_READ(GEN8_L3SQCREG1);
L3_HIGH_PRIO_CREDITS(2)); val &= ~L3_PRIO_CREDITS_MASK;
val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
I915_WRITE(GEN8_L3SQCREG1, val);
}
/* WaToEnableHwFixForPushConstHWBug:bxt */ /* WaToEnableHwFixForPushConstHWBug:bxt */
if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
......
...@@ -8484,14 +8484,17 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, ...@@ -8484,14 +8484,17 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
int high_prio_credits) int high_prio_credits)
{ {
u32 misccpctl; u32 misccpctl;
u32 val;
/* WaTempDisableDOPClkGating:bdw */ /* WaTempDisableDOPClkGating:bdw */
misccpctl = I915_READ(GEN7_MISCCPCTL); misccpctl = I915_READ(GEN7_MISCCPCTL);
I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
I915_WRITE(GEN8_L3SQCREG1, val = I915_READ(GEN8_L3SQCREG1);
L3_GENERAL_PRIO_CREDITS(general_prio_credits) | val &= ~L3_PRIO_CREDITS_MASK;
L3_HIGH_PRIO_CREDITS(high_prio_credits)); val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
I915_WRITE(GEN8_L3SQCREG1, val);
/* /*
* Wait at least 100 clocks before re-enabling clock gating. * Wait at least 100 clocks before re-enabling clock gating.
......
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