Commit 938e1426 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

Pull i2c fixes from Wolfram Sang:
 "Two bugfixes, one v4.16 regression fix, and two documentation fixes"

* 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
  i2c: designware: Consider SCL GPIO optional
  i2c: busses: i2c-sirf: Fix spelling: "formular" -> "formula".
  i2c: bcm2835: Set up the rising/falling edge delays
  i2c: i801: Add missing documentation entries for Braswell and Kaby Lake
  i2c: designware: must wait for enable
parents 170e07bf d1fa7452
...@@ -28,8 +28,10 @@ Supported adapters: ...@@ -28,8 +28,10 @@ Supported adapters:
* Intel Wildcat Point (PCH) * Intel Wildcat Point (PCH)
* Intel Wildcat Point-LP (PCH) * Intel Wildcat Point-LP (PCH)
* Intel BayTrail (SOC) * Intel BayTrail (SOC)
* Intel Braswell (SOC)
* Intel Sunrise Point-H (PCH) * Intel Sunrise Point-H (PCH)
* Intel Sunrise Point-LP (PCH) * Intel Sunrise Point-LP (PCH)
* Intel Kaby Lake-H (PCH)
* Intel DNV (SOC) * Intel DNV (SOC)
* Intel Broxton (SOC) * Intel Broxton (SOC)
* Intel Lewisburg (PCH) * Intel Lewisburg (PCH)
......
...@@ -123,8 +123,10 @@ config I2C_I801 ...@@ -123,8 +123,10 @@ config I2C_I801
Wildcat Point (PCH) Wildcat Point (PCH)
Wildcat Point-LP (PCH) Wildcat Point-LP (PCH)
BayTrail (SOC) BayTrail (SOC)
Braswell (SOC)
Sunrise Point-H (PCH) Sunrise Point-H (PCH)
Sunrise Point-LP (PCH) Sunrise Point-LP (PCH)
Kaby Lake-H (PCH)
DNV (SOC) DNV (SOC)
Broxton (SOC) Broxton (SOC)
Lewisburg (PCH) Lewisburg (PCH)
......
...@@ -50,6 +50,9 @@ ...@@ -50,6 +50,9 @@
#define BCM2835_I2C_S_CLKT BIT(9) #define BCM2835_I2C_S_CLKT BIT(9)
#define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */ #define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */
#define BCM2835_I2C_FEDL_SHIFT 16
#define BCM2835_I2C_REDL_SHIFT 0
#define BCM2835_I2C_CDIV_MIN 0x0002 #define BCM2835_I2C_CDIV_MIN 0x0002
#define BCM2835_I2C_CDIV_MAX 0xFFFE #define BCM2835_I2C_CDIV_MAX 0xFFFE
...@@ -81,7 +84,7 @@ static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg) ...@@ -81,7 +84,7 @@ static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg)
static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev) static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev)
{ {
u32 divider; u32 divider, redl, fedl;
divider = DIV_ROUND_UP(clk_get_rate(i2c_dev->clk), divider = DIV_ROUND_UP(clk_get_rate(i2c_dev->clk),
i2c_dev->bus_clk_rate); i2c_dev->bus_clk_rate);
...@@ -100,6 +103,22 @@ static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev) ...@@ -100,6 +103,22 @@ static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev)
bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider); bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider);
/*
* Number of core clocks to wait after falling edge before
* outputting the next data bit. Note that both FEDL and REDL
* can't be greater than CDIV/2.
*/
fedl = max(divider / 16, 1u);
/*
* Number of core clocks to wait after rising edge before
* sampling the next incoming data bit.
*/
redl = max(divider / 4, 1u);
bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DEL,
(fedl << BCM2835_I2C_FEDL_SHIFT) |
(redl << BCM2835_I2C_REDL_SHIFT));
return 0; return 0;
} }
......
...@@ -209,7 +209,7 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) ...@@ -209,7 +209,7 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
i2c_dw_disable_int(dev); i2c_dw_disable_int(dev);
/* Enable the adapter */ /* Enable the adapter */
__i2c_dw_enable(dev, true); __i2c_dw_enable_and_wait(dev, true);
/* Clear and enable interrupts */ /* Clear and enable interrupts */
dw_readl(dev, DW_IC_CLR_INTR); dw_readl(dev, DW_IC_CLR_INTR);
...@@ -644,7 +644,7 @@ static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev) ...@@ -644,7 +644,7 @@ static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
gpio = devm_gpiod_get(dev->dev, "scl", GPIOD_OUT_HIGH); gpio = devm_gpiod_get(dev->dev, "scl", GPIOD_OUT_HIGH);
if (IS_ERR(gpio)) { if (IS_ERR(gpio)) {
r = PTR_ERR(gpio); r = PTR_ERR(gpio);
if (r == -ENOENT) if (r == -ENOENT || r == -ENOSYS)
return 0; return 0;
return r; return r;
} }
......
...@@ -58,6 +58,7 @@ ...@@ -58,6 +58,7 @@
* Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
* Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
* BayTrail (SOC) 0x0f12 32 hard yes yes yes * BayTrail (SOC) 0x0f12 32 hard yes yes yes
* Braswell (SOC) 0x2292 32 hard yes yes yes
* Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
* Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
* DNV (SOC) 0x19df 32 hard yes yes yes * DNV (SOC) 0x19df 32 hard yes yes yes
......
...@@ -341,7 +341,7 @@ static int i2c_sirfsoc_probe(struct platform_device *pdev) ...@@ -341,7 +341,7 @@ static int i2c_sirfsoc_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, adap); platform_set_drvdata(pdev, adap);
init_completion(&siic->done); init_completion(&siic->done);
/* Controller Initalisation */ /* Controller initialisation */
writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL); writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
...@@ -369,7 +369,7 @@ static int i2c_sirfsoc_probe(struct platform_device *pdev) ...@@ -369,7 +369,7 @@ static int i2c_sirfsoc_probe(struct platform_device *pdev)
* but they start to affect the speed when clock is set to faster * but they start to affect the speed when clock is set to faster
* frequencies. * frequencies.
* Through the actual tests, use the different user_div value(which * Through the actual tests, use the different user_div value(which
* in the divider formular 'Fio / (Fi2c * user_div)') to adapt * in the divider formula 'Fio / (Fi2c * user_div)') to adapt
* the different ranges of i2c bus clock frequency, to make the SCL * the different ranges of i2c bus clock frequency, to make the SCL
* more accurate. * more accurate.
*/ */
......
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