Commit 965ec741 authored by Rickard Strandqvist's avatar Rickard Strandqvist Committed by John W. Linville

rtlwifi/rtl8192c[eu]: Fix media status register mask

bt_msr & 0xfc will never match 0x3. Fix this by using a mask that actually matches the available types.
Signed-off-by: default avatarRickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Reviewed-by: default avatarPeter Wu <peter@lekensteyn.nl>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 8a607208
...@@ -1206,7 +1206,7 @@ static int _rtl92ce_set_media_status(struct ieee80211_hw *hw, ...@@ -1206,7 +1206,7 @@ static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
rtl_write_byte(rtlpriv, (MSR), bt_msr); rtl_write_byte(rtlpriv, (MSR), bt_msr);
rtlpriv->cfg->ops->led_control(hw, ledaction); rtlpriv->cfg->ops->led_control(hw, ledaction);
if ((bt_msr & 0xfc) == MSR_AP) if ((bt_msr & MSR_MASK) == MSR_AP)
rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
else else
rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
......
...@@ -375,6 +375,7 @@ ...@@ -375,6 +375,7 @@
#define MSR_ADHOC 0x01 #define MSR_ADHOC 0x01
#define MSR_INFRA 0x02 #define MSR_INFRA 0x02
#define MSR_AP 0x03 #define MSR_AP 0x03
#define MSR_MASK 0x03
#define RRSR_RSC_OFFSET 21 #define RRSR_RSC_OFFSET 21
#define RRSR_SHORT_OFFSET 23 #define RRSR_SHORT_OFFSET 23
......
...@@ -1360,7 +1360,7 @@ static int _rtl92cu_set_media_status(struct ieee80211_hw *hw, ...@@ -1360,7 +1360,7 @@ static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
} }
rtl_write_byte(rtlpriv, (MSR), bt_msr); rtl_write_byte(rtlpriv, (MSR), bt_msr);
rtlpriv->cfg->ops->led_control(hw, ledaction); rtlpriv->cfg->ops->led_control(hw, ledaction);
if ((bt_msr & 0xfc) == MSR_AP) if ((bt_msr & MSR_MASK) == MSR_AP)
rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
else else
rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
......
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