Commit 9708fb63 authored by Wadim Egorov's avatar Wadim Egorov Committed by David S. Miller

net: phy: dp83867: Add binding for the CLK_OUT pin muxing option

The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Signed-off-by: default avatarWadim Egorov <w.egorov@phytec.de>
Signed-off-by: default avatarDaniel Schultz <d.schultz@phytec.de>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 37c64cf6
...@@ -75,6 +75,8 @@ ...@@ -75,6 +75,8 @@
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
/* CFG4 bits */ /* CFG4 bits */
#define DP83867_CFG4_PORT_MIRROR_EN BIT(0) #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
...@@ -92,6 +94,7 @@ struct dp83867_private { ...@@ -92,6 +94,7 @@ struct dp83867_private {
int io_impedance; int io_impedance;
int port_mirroring; int port_mirroring;
bool rxctrl_strap_quirk; bool rxctrl_strap_quirk;
int clk_output_sel;
}; };
static int dp83867_ack_interrupt(struct phy_device *phydev) static int dp83867_ack_interrupt(struct phy_device *phydev)
...@@ -160,6 +163,14 @@ static int dp83867_of_init(struct phy_device *phydev) ...@@ -160,6 +163,14 @@ static int dp83867_of_init(struct phy_device *phydev)
dp83867->io_impedance = -EINVAL; dp83867->io_impedance = -EINVAL;
/* Optional configuration */ /* Optional configuration */
ret = of_property_read_u32(of_node, "ti,clk-output-sel",
&dp83867->clk_output_sel);
if (ret || dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK)
/* Keep the default value if ti,clk-output-sel is not set
* or too high
*/
dp83867->clk_output_sel = DP83867_CLK_O_SEL_REF_CLK;
if (of_property_read_bool(of_node, "ti,max-output-impedance")) if (of_property_read_bool(of_node, "ti,max-output-impedance"))
dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
else if (of_property_read_bool(of_node, "ti,min-output-impedance")) else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
...@@ -295,6 +306,14 @@ static int dp83867_config_init(struct phy_device *phydev) ...@@ -295,6 +306,14 @@ static int dp83867_config_init(struct phy_device *phydev)
if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
dp83867_config_port_mirroring(phydev); dp83867_config_port_mirroring(phydev);
/* Clock output selection if muxing property is set */
if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG);
val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val);
}
return 0; return 0;
} }
......
...@@ -42,4 +42,18 @@ ...@@ -42,4 +42,18 @@
#define DP83867_RGMIIDCTL_3_75_NS 0xe #define DP83867_RGMIIDCTL_3_75_NS 0xe
#define DP83867_RGMIIDCTL_4_00_NS 0xf #define DP83867_RGMIIDCTL_4_00_NS 0xf
/* IO_MUX_CFG - Clock output selection */
#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0
#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1
#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2
#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3
#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4
#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5
#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6
#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7
#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8
#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9
#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA
#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB
#define DP83867_CLK_O_SEL_REF_CLK 0xC
#endif #endif
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