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Commit 98ebe7d3 authored by Ralf Bächle's avatar Ralf Bächle Committed by Linus Torvalds
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[PATCH] Momentum update 

This adds the board support code for Momentum's Ocelot series of boards.
parent 2a8d04d7
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arch/mips/momentum/ocelot_c/Makefile 0 → 100644
View file @ 98ebe7d3
#
# Makefile for Momentum Computer's Ocelot-C and -CS boards.
#
obj-y += mv-irq.o cpci-irq.o uart-irq.o int-handler.o irq.o \
pci-irq.o prom.o reset.o setup.o
obj-$(CONFIG_KGDB) += dbg_io.o
arch/mips/momentum/ocelot_c/cpci-irq.c 0 → 100644
View file @ 98ebe7d3
/*
* Copyright 2002 Momentum Computer
* Author: mdharm@momenco.com
*
* arch/mips/momentum/ocelot_c/cpci-irq.c
* Interrupt routines for cpci. Interrupt numbers are assigned from
* CPCI_IRQ_BASE to CPCI_IRQ_BASE+8 (8 interrupt sources).
*
* Note that the high-level software will need to be careful about using
* these interrupts. If this board is asserting a cPCI interrupt, it will
* also see the asserted interrupt. Care must be taken to avoid an
* interrupt flood.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <asm/ptrace.h>
#include <linux/config.h>
#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <asm/io.h>
#include "ocelot_c_fpga.h"
#define CPCI_IRQ_BASE 8
static inline int ls1bit8(unsigned int x)
{
int b = 7, s;
s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
return b;
}
/* mask off an interrupt -- 0 is enable, 1 is disable */
static inline void mask_cpci_irq(unsigned int irq)
{
uint32_t value;
value = OCELOT_FPGA_READ(INTMASK);
value |= 1 << (irq - CPCI_IRQ_BASE);
OCELOT_FPGA_WRITE(value, INTMASK);
/* read the value back to assure that it's really been written */
value = OCELOT_FPGA_READ(INTMASK);
}
/* unmask an interrupt -- 0 is enable, 1 is disable */
static inline void unmask_cpci_irq(unsigned int irq)
{
uint32_t value;
value = OCELOT_FPGA_READ(INTMASK);
value &= ~(1 << (irq - CPCI_IRQ_BASE));
OCELOT_FPGA_WRITE(value, INTMASK);
/* read the value back to assure that it's really been written */
value = OCELOT_FPGA_READ(INTMASK);
}
/*
* Enables the IRQ in the FPGA
*/
static void enable_cpci_irq(unsigned int irq)
{
unmask_cpci_irq(irq);
}
/*
* Initialize the IRQ in the FPGA
*/
static unsigned int startup_cpci_irq(unsigned int irq)
{
unmask_cpci_irq(irq);
return 0;
}
/*
* Disables the IRQ in the FPGA
*/
static void disable_cpci_irq(unsigned int irq)
{
mask_cpci_irq(irq);
}
/*
* Masks and ACKs an IRQ
*/
static void mask_and_ack_cpci_irq(unsigned int irq)
{
mask_cpci_irq(irq);
}
/*
* End IRQ processing
*/
static void end_cpci_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
unmask_cpci_irq(irq);
}
/*
* Interrupt handler for interrupts coming from the FPGA chip.
* It could be built in ethernet ports etc...
*/
void ll_cpci_irq(struct pt_regs *regs)
{
unsigned int irq_src, irq_mask;
/* read the interrupt status registers */
irq_src = OCELOT_FPGA_READ(INTSTAT);
irq_mask = OCELOT_FPGA_READ(INTMASK);
/* mask for just the interrupts we want */
irq_src &= ~irq_mask;
do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE, regs);
}
#define shutdown_cpci_irq disable_cpci_irq
struct hw_interrupt_type cpci_irq_type = {
"CPCI/FPGA",
startup_cpci_irq,
shutdown_cpci_irq,
enable_cpci_irq,
disable_cpci_irq,
mask_and_ack_cpci_irq,
end_cpci_irq,
NULL
};
void cpci_irq_init(void)
{
int i;
/* Reset irq handlers pointers to NULL */
for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 2;
irq_desc[i].handler = &cpci_irq_type;
}
}
arch/mips/momentum/ocelot_c/dbg_io.c 0 → 100644
View file @ 98ebe7d3
#include <linux/config.h>
#if defined(CONFIG_KGDB)
#include <asm/serial.h> /* For the serial port location and base baud */
/* --- CONFIG --- */
typedef unsigned char uint8;
typedef unsigned int uint32;
/* --- END OF CONFIG --- */
#define UART16550_BAUD_2400 2400
#define UART16550_BAUD_4800 4800
#define UART16550_BAUD_9600 9600
#define UART16550_BAUD_19200 19200
#define UART16550_BAUD_38400 38400
#define UART16550_BAUD_57600 57600
#define UART16550_BAUD_115200 115200
#define UART16550_PARITY_NONE 0
#define UART16550_PARITY_ODD 0x08
#define UART16550_PARITY_EVEN 0x18
#define UART16550_PARITY_MARK 0x28
#define UART16550_PARITY_SPACE 0x38
#define UART16550_DATA_5BIT 0x0
#define UART16550_DATA_6BIT 0x1
#define UART16550_DATA_7BIT 0x2
#define UART16550_DATA_8BIT 0x3
#define UART16550_STOP_1BIT 0x0
#define UART16550_STOP_2BIT 0x4
/* ----------------------------------------------------- */
/* === CONFIG === */
/* [jsun] we use the second serial port for kdb */
#define BASE OCELOT_SERIAL1_BASE
#define MAX_BAUD OCELOT_BASE_BAUD
/* === END OF CONFIG === */
#define REG_OFFSET 4
/* register offset */
#define OFS_RCV_BUFFER 0
#define OFS_TRANS_HOLD 0
#define OFS_SEND_BUFFER 0
#define OFS_INTR_ENABLE (1*REG_OFFSET)
#define OFS_INTR_ID (2*REG_OFFSET)
#define OFS_DATA_FORMAT (3*REG_OFFSET)
#define OFS_LINE_CONTROL (3*REG_OFFSET)
#define OFS_MODEM_CONTROL (4*REG_OFFSET)
#define OFS_RS232_OUTPUT (4*REG_OFFSET)
#define OFS_LINE_STATUS (5*REG_OFFSET)
#define OFS_MODEM_STATUS (6*REG_OFFSET)
#define OFS_RS232_INPUT (6*REG_OFFSET)
#define OFS_SCRATCH_PAD (7*REG_OFFSET)
#define OFS_DIVISOR_LSB (0*REG_OFFSET)
#define OFS_DIVISOR_MSB (1*REG_OFFSET)
/* memory-mapped read/write of the port */
#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
/* disable interrupts */
UART16550_WRITE(OFS_INTR_ENABLE, 0);
/* set up buad rate */
{
uint32 divisor;
/* set DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
/* set divisor */
divisor = MAX_BAUD / baud;
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
/* clear DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
}
/* set data format */
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
}
static int remoteDebugInitialized = 0;
uint8 getDebugChar(void)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_38400,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
return UART16550_READ(OFS_RCV_BUFFER);
}
int putDebugChar(uint8 byte)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_38400,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
UART16550_WRITE(OFS_SEND_BUFFER, byte);
return 1;
}
#endif
arch/mips/momentum/ocelot_c/int-handler.S 0 → 100644
View file @ 98ebe7d3
/*
* Copyright 2002 Momentum Computer Inc.
* Author: Matthew Dharm <mdharm@momenco.com>
*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* First-level interrupt dispatcher for Ocelot-CS board.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#define __ASSEMBLY__
#include <linux/config.h>
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include "ocelot_c_fpga.h"
/*
* First level interrupt dispatcher for Ocelot-CS board
*/
.align 5
NESTED(ocelot_handle_int, PT_SIZE, sp)
SAVE_ALL
CLI
.set at
mfc0 t0, CP0_CAUSE
mfc0 t2, CP0_STATUS
and t0, t2
andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */
bnez t1, ll_sw0_irq
andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */
bnez t1, ll_sw1_irq
andi t1, t0, STATUSF_IP2 /* int0 hardware line */
bnez t1, ll_scsi_irq
andi t1, t0, STATUSF_IP3 /* int1 hardware line */
bnez t1, ll_uart_decode_irq
andi t1, t0, STATUSF_IP4 /* int2 hardware line */
bnez t1, ll_pmc_irq
andi t1, t0, STATUSF_IP5 /* int3 hardware line */
bnez t1, ll_cpci_decode_irq
andi t1, t0, STATUSF_IP6 /* int4 hardware line */
bnez t1, ll_mv64340_decode_irq
andi t1, t0, STATUSF_IP7 /* cpu timer */
bnez t1, ll_cputimer_irq
.set reorder
/* wrong alarm or masked ... */
j spurious_interrupt
nop
END(ocelot_handle_int)
.align 5
ll_sw0_irq:
li a0, 0
move a1, sp
jal do_IRQ
j ret_from_irq
ll_sw1_irq:
li a0, 1
move a1, sp
jal do_IRQ
j ret_from_irq
ll_scsi_irq:
li a0, 2
move a1, sp
jal do_IRQ
j ret_from_irq
ll_uart_decode_irq:
move a0, sp
jal ll_uart_irq
j ret_from_irq
ll_pmc_irq:
li a0, 4
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpci_decode_irq:
move a0, sp
jal ll_cpci_irq
j ret_from_irq
ll_mv64340_decode_irq:
move a0, sp
jal ll_mv64340_irq
j ret_from_irq
ll_cputimer_irq:
li a0, 7
move a1, sp
jal do_IRQ
j ret_from_irq
arch/mips/momentum/ocelot_c/irq.c 0 → 100644
View file @ 98ebe7d3
/*
* Copyright (C) 2000 RidgeRun, Inc.
* Author: RidgeRun, Inc.
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
*
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
* Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <asm/bitops.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
static spinlock_t irq_lock = SPIN_LOCK_UNLOCKED;
/* Function for careful CP0 interrupt mask access */
static inline void modify_cp0_intmask(unsigned clr_mask_in, unsigned set_mask_in)
{
unsigned long status;
unsigned clr_mask;
unsigned set_mask;
/* do the low 8 bits first */
clr_mask = 0xff & clr_mask_in;
set_mask = 0xff & set_mask_in;
status = read_c0_status();
status &= ~((clr_mask & 0xFF) << 8);
status |= (set_mask & 0xFF) << 8;
write_c0_status(status);
}
static inline void mask_irq(unsigned int irq)
{
modify_cp0_intmask(irq, 0);
}
static inline void unmask_irq(unsigned int irq)
{
modify_cp0_intmask(0, irq);
}
static void enable_cp7000_irq(unsigned int irq)
{
unsigned long flags;
spin_lock_irqsave(&irq_lock, flags);
unmask_irq(1 << irq);
spin_unlock_irqrestore(&irq_lock, flags);
}
static unsigned int startup_cp7000_irq(unsigned int irq)
{
enable_cp7000_irq(irq);
return 0; /* never anything pending */
}
static void disable_cp7000_irq(unsigned int irq)
{
unsigned long flags;
spin_lock_irqsave(&irq_lock, flags);
mask_irq(1 << irq);
spin_unlock_irqrestore(&irq_lock, flags);
}
#define shutdown_cp7000_irq disable_cp7000_irq
static void mask_and_ack_cp7000_irq(unsigned int irq)
{
mask_irq(1 << irq);
}
static void end_cp7000_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
unmask_irq(1 << irq);
}
static struct hw_interrupt_type cp7000_hpcdma_irq_type = {
#ifdef CONFIG_CPU_SR71000
"SR71000",
#else
"RM7000",
#endif
startup_cp7000_irq,
shutdown_cp7000_irq,
enable_cp7000_irq,
disable_cp7000_irq,
mask_and_ack_cp7000_irq,
end_cp7000_irq,
NULL
};
extern asmlinkage void ocelot_handle_int(void);
extern void mv64340_irq_init(void);
extern void uart_irq_init(void);
extern void cpci_irq_init(void);
static struct irqaction cascade_fpga =
{ no_action, SA_INTERRUPT, 0, "cascade via FPGA", NULL, NULL };
static struct irqaction cascade_mv64340 =
{ no_action, SA_INTERRUPT, 0, "cascade via MV64340", NULL, NULL };
void __init init_IRQ(void)
{
int i;
/*
* Clear all of the interrupts while we change the able around a bit.
* int-handler is not on bootstrap
*/
clear_c0_status(ST0_IM | ST0_BEV);
__cli();
/* Sets the first-level interrupt dispatcher. */
set_except_vector(0, ocelot_handle_int);
init_generic_irq();
/* set up handler for first 8 IRQs as the CPU */
for (i = 0; i < 8; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = &cp7000_hpcdma_irq_type;
}
/* set up the cascading interrupts */
setup_irq(3, &cascade_fpga);
setup_irq(5, &cascade_fpga);
setup_irq(6, &cascade_mv64340);
mv64340_irq_init();
uart_irq_init();
cpci_irq_init();
#ifdef CONFIG_KGDB
printk("start kgdb ...\n");
set_debug_traps();
breakpoint(); /* you may move this line to whereever you want :-) */
#endif
#ifdef CONFIG_GDB_CONSOLE
register_gdb_console();
#endif
}
arch/mips/momentum/ocelot_c/mv-irq.c 0 → 100644
View file @ 98ebe7d3
/*
* Copyright 2002 Momentum Computer
* Author: mdharm@momenco.com
*
* arch/mips/momentum/ocelot_c/mv-irq.c
* Interrupt routines for mv64340. Interrupt numbers are assigned from
* MV64340_IRQ_BASE to MV64340_IRQ_BASE+64.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <asm/ptrace.h>
#include <linux/config.h>
#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <asm/io.h>
#include <asm/mv64340.h>
#define MV64340_IRQ_BASE 16
static inline int ls1bit32(unsigned int x)
{
int b = 31, s;
s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
s = 1; if (x << 1 == 0) s = 0; b -= s;
return b;
}
/* mask off an interrupt -- 1 is enable, 0 is disable */
static inline void mask_mv64340_irq(unsigned int irq)
{
uint32_t value;
if (irq < (MV64340_IRQ_BASE + 32)) {
MV_READ(MV64340_INTERRUPT0_MASK_0_LOW, &value);
value &= ~(1 << (irq - MV64340_IRQ_BASE));
MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value);
} else {
MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH, &value);
value &= ~(1 << (irq - (MV64340_IRQ_BASE - 32)));
MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value);
}
}
/* unmask an interrupt -- 1 is enable, 0 is disable */
static inline void unmask_mv64340_irq(unsigned int irq)
{
uint32_t value;
if (irq < (MV64340_IRQ_BASE + 32)) {
MV_READ(MV64340_INTERRUPT0_MASK_0_LOW, &value);
value |= 1 << (irq - MV64340_IRQ_BASE);
MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value);
} else {
MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH, &value);
value |= 1 << (irq - (MV64340_IRQ_BASE - 32));
MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value);
}
}
/*
* Enables the IRQ on Marvell Chip
*/
static void enable_mv64340_irq(unsigned int irq)
{
unmask_mv64340_irq(irq);
}
/*
* Initialize the IRQ on Marvell Chip
*/
static unsigned int startup_mv64340_irq(unsigned int irq)
{
unmask_mv64340_irq(irq);
return 0;
}
/*
* Disables the IRQ on Marvell Chip
*/
static void disable_mv64340_irq(unsigned int irq)
{
mask_mv64340_irq(irq);
}
/*
* Masks and ACKs an IRQ
*/
static void mask_and_ack_mv64340_irq(unsigned int irq)
{
mask_mv64340_irq(irq);
}
/*
* End IRQ processing
*/
static void end_mv64340_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
unmask_mv64340_irq(irq);
}
/*
* Interrupt handler for interrupts coming from the Marvell chip.
* It could be built in ethernet ports etc...
*/
void ll_mv64340_irq(struct pt_regs *regs)
{
unsigned int irq_src_low, irq_src_high;
unsigned int irq_mask_low, irq_mask_high;
/* read the interrupt status registers */
MV_READ(MV64340_INTERRUPT0_MASK_0_LOW, &irq_mask_low);
MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH, &irq_mask_high);
MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_LOW, &irq_src_low);
MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_HIGH, &irq_src_high);
/* mask for just the interrupts we want */
irq_src_low &= irq_mask_low;
irq_src_high &= irq_mask_high;
if (irq_src_low)
do_IRQ(ls1bit32(irq_src_low) + MV64340_IRQ_BASE, regs);
else
do_IRQ(ls1bit32(irq_src_high) + MV64340_IRQ_BASE + 32, regs);
}
#define shutdown_mv64340_irq disable_mv64340_irq
struct hw_interrupt_type mv64340_irq_type = {
"MV-64340",
startup_mv64340_irq,
shutdown_mv64340_irq,
enable_mv64340_irq,
disable_mv64340_irq,
mask_and_ack_mv64340_irq,
end_mv64340_irq,
NULL
};
void mv64340_irq_init(void)
{
int i;
/* Reset irq handlers pointers to NULL */
for (i = MV64340_IRQ_BASE; i < (MV64340_IRQ_BASE + 64); i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 2;
irq_desc[i].handler = &mv64340_irq_type;
}
}
arch/mips/momentum/ocelot_c/ocelot_c_fpga.h 0 → 100644
View file @ 98ebe7d3
/*
* Ocelot-C Board Register Definitions
*
* (C) 2002 Momentum Computer Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __OCELOT_C_FPGA_H__
#define __OCELOT_C_FPGA_H__
#define OCELOT_C_CS0_ADDR (0xfc000000)
#define OCELOT_C_REG_BOARDREV 0x0
#define OCELOT_C_REG_FPGA_REV 0x1
#define OCELOT_C_REG_FPGA_TYPE 0x2
#define OCELOT_C_REG_RESET_STATUS 0x3
#define OCELOT_C_REG_BOARD_STATUS 0x4
#define OCELOT_C_REG_CPCI_ID 0x5
#define OCELOT_C_REG_SET 0x6
#define OCELOT_C_REG_CLR 0x7
#define OCELOT_C_REG_EEPROM_MODE 0x9
#define OCELOT_C_REG_INTMASK 0xa
#define OCELOT_C_REG_INTSTAT 0xb
#define OCELOT_C_REG_UART_INTMASK 0xc
#define OCELOT_C_REG_UART_INTSTAT 0xd
#define OCELOT_C_REG_INTSET 0xe
#define OCELOT_C_REG_INTCLR 0xf
#define OCELOT_FPGA_WRITE(x, y) writeb(x, OCELOT_C_CS0_ADDR + OCELOT_C_REG_##y)
#define OCELOT_FPGA_READ(x) readb(OCELOT_C_CS0_ADDR + OCELOT_C_REG_##x)
#endif
arch/mips/momentum/ocelot_c/pci-irq.c 0 → 100644
View file @ 98ebe7d3
/*
* Copyright 2002 Momentum Computer Inc.
* Author: Matthew Dharm <mdharm@momenco.com>
*
* Based on work for the Linux port to the Ocelot board, which is
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* arch/mips/momentum/ocelot_g/pci.c
* Board-specific PCI routines for mv64340 controller.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/version.h>
#include <linux/init.h>
#include <asm/pci.h>
void __init mv64340_board_pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_bus *current_bus = bus;
struct pci_dev *devices;
struct list_head *devices_link;
u16 cmd;
/* loop over all known devices on this bus */
list_for_each(devices_link, &(current_bus->devices)) {
devices = pci_dev_b(devices_link);
if (devices == NULL)
continue;
if ((current_bus->number == 0) &&
(PCI_SLOT(devices->devfn) == 1) &&
(PCI_FUNC(devices->devfn) == 0)) {
/* LSI 53C10101R SCSI (A) */
devices->irq = 2;
} else if ((current_bus->number == 0) &&
(PCI_SLOT(devices->devfn) == 1) &&
(PCI_FUNC(devices->devfn) == 1)) {
/* LSI 53C10101R SCSI (B) */
devices->irq = 2;
} else if ((current_bus->number == 1) &&
(PCI_SLOT(devices->devfn) == 1)) {
/* Intel 21555 bridge */
devices->irq = 12;
} else if ((current_bus->number == 1) &&
(PCI_SLOT(devices->devfn) == 2)) {
/* PMC Slot */
devices->irq = 4;
} else {
/* We don't have assign interrupts for other devices. */
devices->irq = 0xff;
}
/* Assign an interrupt number for the device */
bus->ops->write_byte(devices, PCI_INTERRUPT_LINE, devices->irq);
/* enable master for everything but the MV-64340 */
if (((current_bus->number != 0) && (current_bus->number != 1))
|| (PCI_SLOT(devices->devfn) != 0)) {
bus->ops->read_word(devices, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER;
bus->ops->write_word(devices, PCI_COMMAND, cmd);
}
}
}
arch/mips/momentum/ocelot_c/prom.c 0 → 100644
View file @ 98ebe7d3
/*
* Copyright 2002 Momentum Computer Inc.
* Author: Matthew Dharm <mdharm@momenco.com>
*
* Based on Ocelot Linux port, which is
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/mv64340.h>
#include "ocelot_c_fpga.h"
struct callvectors {
int (*open) (char*, int, int);
int (*close) (int);
int (*read) (int, void*, int);
int (*write) (int, void*, int);
off_t (*lseek) (int, off_t, int);
int (*printf) (const char*, ...);
void (*cacheflush) (void);
char* (*gets) (char*);
};
struct callvectors* debug_vectors;
char arcs_cmdline[CL_SIZE];
extern unsigned long mv64340_base;
extern unsigned long cpu_clock;
#ifdef CONFIG_MV64340_ETH
extern unsigned char prom_mac_addr_base[6];
#endif
const char *get_system_type(void)
{
#ifdef CONFIG_CPU_SR71000
return "Momentum Ocelot-CS";
#else
return "Momentum Ocelot-C";
#endif
}
#ifdef CONFIG_MV64340_ETH
static void burn_clocks(void)
{
int i;
/* this loop should burn at least 1us -- this should be plenty */
for (i = 0; i < 0x10000; i++)
;
}
static u8 exchange_bit(u8 val, u8 cs)
{
/* place the data */
OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
burn_clocks();
/* turn the clock on */
OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
burn_clocks();
/* turn the clock off and read-strobe */
OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
/* return the data */
return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
}
void get_mac(char dest[6])
{
u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
int i,j;
for (i = 0; i < 12; i++)
exchange_bit(read_opcode[i], 1);
for (j = 0; j < 6; j++) {
dest[j] = 0;
for (i = 0; i < 8; i++) {
dest[j] <<= 1;
dest[j] |= exchange_bit(0, 1);
}
}
/* turn off CS */
exchange_bit(0,0);
}
#endif
/* [jsun@junsun.net] PMON passes arguments in C main() style */
void __init prom_init(int argc, char **arg, char** env, struct callvectors *cv)
{
int i;
/* save the PROM vectors for debugging use */
debug_vectors = cv;
/* arg[0] is "g", the rest is boot parameters */
arcs_cmdline[0] = '\0';
for (i = 1; i < argc; i++) {
if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
>= sizeof(arcs_cmdline))
break;
strcat(arcs_cmdline, arg[i]);
strcat(arcs_cmdline, " ");
}
mips_machgroup = MACH_GROUP_MOMENCO;
mips_machtype = MACH_MOMENCO_OCELOT_C;
while (*env) {
if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
mv64340_base = simple_strtol(*env + strlen("gtbase="),
NULL, 16);
}
if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
cpu_clock = simple_strtol(*env + strlen("cpuclock="),
NULL, 10);
}
env++;
}
#ifdef CONFIG_MV64340_ETH
/* get the base MAC address for on-board ethernet ports */
get_mac(prom_mac_addr_base);
#endif
debug_vectors->printf("Booting Linux kernel...\n");
}
void __init prom_free_prom_memory(void)
{
}
void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
{
}
arch/mips/momentum/ocelot_c/reset.c 0 → 100644
View file @ 98ebe7d3
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Copyright (C) 1997, 2001 Ralf Baechle
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* Copyright (C) 2002 Momentum Computer Inc.
* Author: Matthew Dharm <mdharm@momenco.com>
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/system.h>
#include <linux/delay.h>
void momenco_ocelot_restart(char *command)
{
/* base address of timekeeper portion of part */
void *nvram = (void*) 0xfc807000;
/* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
writeb(0x84, nvram + 0xff7);
/* wait for the watchdog to go off */
mdelay(100+(1000/16));
/* if the watchdog fails for some reason, let people know */
printk(KERN_NOTICE "Watchdog reset failed\n");
}
void momenco_ocelot_halt(void)
{
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
while (1)
__asm__(".set\tmips3\n\t"
"wait\n\t"
".set\tmips0");
}
void momenco_ocelot_power_off(void)
{
momenco_ocelot_halt();
}
arch/mips/momentum/ocelot_c/setup.c 0 → 100644
View file @ 98ebe7d3
/*
* BRIEF MODULE DESCRIPTION
* Momentum Computer Ocelot-C and -CS board dependent boot routines
*
* Copyright (C) 1996, 1997, 2001 Ralf Baechle
* Copyright (C) 2000 RidgeRun, Inc.
* Copyright (C) 2001 Red Hat, Inc.
* Copyright (C) 2002 Momentum Computer
*
* Author: Matthew Dharm, Momentum Computer
* mdharm@momenco.com
*
* Author: RidgeRun, Inc.
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/bcd.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mc146818rtc.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/timex.h>
#include <linux/vmalloc.h>
#include <asm/time.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pci.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/reboot.h>
#include <asm/mc146818rtc.h>
#include <linux/version.h>
#include <linux/bootmem.h>
#include <linux/blk.h>
#include <asm/mv64340.h>
#include "ocelot_c_fpga.h"
unsigned long mv64340_base;
unsigned long cpu_clock;
/* These functions are used for rebooting or halting the machine*/
extern void momenco_ocelot_restart(char *command);
extern void momenco_ocelot_halt(void);
extern void momenco_ocelot_power_off(void);
void momenco_time_init(void);
static char reset_reason;
#define ENTRYLO(x) ((pte_val(mk_pte_phys((x), PAGE_KERNEL_UNCACHED)) >> 6)|1)
/* setup code for a handoff from a version 2 PMON 2000 PROM */
void PMON_v2_setup(void)
{
/* Some wired TLB entries for the MV64340 and perhiperals. The
MV64340 is going to be hit on every IRQ anyway - there's
absolutely no point in letting it be a random TLB entry, as
it'll just cause needless churning of the TLB. And we use
the other half for the serial port, which is just a PITA
otherwise :)
Device Physical Virtual
MV64340 Internal Regs 0xf4000000 0xf4000000
Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
NVRAM (CS1) 0xfc800000 0xfc800000
UARTs (CS2) 0xfd000000 0xfd000000
Internal SRAM 0xfe000000 0xfe000000
M-Systems DOC (CS3) 0xff000000 0xff000000
*/
/* marvell and extra space */
add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
/* fpga, rtc, and uart */
add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M);
/* m-sys and internal SRAM */
add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
mv64340_base = 0xf4000000;
}
unsigned long m48t37y_get_time(void)
{
unsigned char* rtc_base = (unsigned char*)0xfc800000;
unsigned int year, month, day, hour, min, sec;
/* stop the update */
rtc_base[0x7ff8] = 0x40;
year = BCD2BIN(rtc_base[0x7fff]);
year += BCD2BIN(rtc_base[0x7ff1]) * 100;
month = BCD2BIN(rtc_base[0x7ffe]);
day = BCD2BIN(rtc_base[0x7ffd]);
hour = BCD2BIN(rtc_base[0x7ffb]);
min = BCD2BIN(rtc_base[0x7ffa]);
sec = BCD2BIN(rtc_base[0x7ff9]);
/* start the update */
rtc_base[0x7ff8] = 0x00;
return mktime(year, month, day, hour, min, sec);
}
int m48t37y_set_time(unsigned long sec)
{
unsigned char* rtc_base = (unsigned char*)0xfc800000;
struct rtc_time tm;
/* convert to a more useful format -- note months count from 0 */
to_tm(sec, &tm);
tm.tm_mon += 1;
/* enable writing */
rtc_base[0x7ff8] = 0x80;
/* year */
rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
/* month */
rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
/* day */
rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
/* hour/min/sec */
rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
/* day of week -- not really used, but let's keep it up-to-date */
rtc_base[0x7ffc] = CONV_BIN2BCD(tm.tm_wday + 1);
/* disable writing */
rtc_base[0x7ff8] = 0x00;
return 0;
}
void momenco_timer_setup(struct irqaction *irq)
{
setup_irq(7, irq);
}
void momenco_time_init(void)
{
#ifdef CONFIG_CPU_SR71000
mips_counter_frequency = cpu_clock;
#elif defined(CONFIG_CPU_RM7000)
mips_counter_frequency = cpu_clock / 2;
#else
#error Unknown CPU for this board
#endif
board_timer_setup = momenco_timer_setup;
rtc_get_time = m48t37y_get_time;
rtc_set_time = m48t37y_set_time;
}
void __init momenco_ocelot_c_setup(void)
{
unsigned int tmpword;
board_time_init = momenco_time_init;
_machine_restart = momenco_ocelot_restart;
_machine_halt = momenco_ocelot_halt;
_machine_power_off = momenco_ocelot_power_off;
/*
* initrd_start = (ulong)ocelot_initrd_start;
* initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
* initrd_below_start_ok = 1;
*/
/* do handoff reconfiguration */
PMON_v2_setup();
/* shut down ethernet ports, just to be sure our memory doesn't get
* corrupted by random ethernet traffic.
*/
MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
do {}
while (MV_READ_DATA(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
do {}
while (MV_READ_DATA(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
do {}
while (MV_READ_DATA(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
do {}
while (MV_READ_DATA(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), MV_READ_DATA(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), MV_READ_DATA(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
/* Turn off the Bit-Error LED */
OCELOT_FPGA_WRITE(0x80, CLR);
tmpword = OCELOT_FPGA_READ(BOARDREV);
#ifdef CONFIG_CPU_SR71000
if (tmpword < 26)
printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n",
'A'+tmpword);
else
printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n",
tmpword);
#else
if (tmpword < 26)
printk("Momenco Ocelot-C: Board Assembly Rev. %c\n",
'A'+tmpword);
else
printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n",
tmpword);
#endif
tmpword = OCELOT_FPGA_READ(FPGA_REV);
printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
tmpword = OCELOT_FPGA_READ(RESET_STATUS);
printk("Reset reason: 0x%x\n", tmpword);
switch (tmpword) {
case 0x1:
printk(" - Power-up reset\n");
break;
case 0x2:
printk(" - Push-button reset\n");
break;
case 0x4:
printk(" - cPCI bus reset\n");
break;
case 0x8:
printk(" - Watchdog reset\n");
break;
case 0x10:
printk(" - Software reset\n");
break;
default:
printk(" - Unknown reset cause\n");
}
reset_reason = tmpword;
OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
tmpword = OCELOT_FPGA_READ(CPCI_ID);
printk("cPCI ID register: 0x%02x\n", tmpword);
printk(" - Slot number: %d\n", tmpword & 0x1f);
printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
printk("Board Status register: 0x%02x\n", tmpword);
printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
switch(tmpword &3) {
case 3:
/* 512MiB */
add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM);
break;
case 2:
/* 256MiB */
add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
break;
case 1:
/* 128MiB */
add_memory_region(0x0, 0x80<<20, BOOT_MEM_RAM);
break;
case 0:
/* 1GiB -- needs CONFIG_HIGHMEM */
add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM);
break;
}
}
/* This needs to be one of the first initcalls, because no I/O port access
can work before this */
static int io_base_ioremap(void)
{
/* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
void *io_remap_range = ioremap(0xc0000000, 0x30000000);
if (!io_remap_range) {
panic("Could not ioremap I/O port range");
}
printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range);
set_io_port_base(io_remap_range - 0xc0000000);
return 0;
}
module_init(io_base_ioremap);
arch/mips/momentum/ocelot_c/uart-irq.c 0 → 100644
View file @ 98ebe7d3
/*
* Copyright 2002 Momentum Computer
* Author: mdharm@momenco.com
*
* arch/mips/momentum/ocelot_c/uart-irq.c
* Interrupt routines for UARTs. Interrupt numbers are assigned from
* 80 to 81 (2 interrupt sources).
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <asm/ptrace.h>
#include <linux/config.h>
#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <asm/io.h>
#include <asm/irq.h>
#include "ocelot_c_fpga.h"
static inline int ls1bit8(unsigned int x)
{
int b = 7, s;
s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
return b;
}
/* mask off an interrupt -- 0 is enable, 1 is disable */
static inline void mask_uart_irq(unsigned int irq)
{
uint8_t value;
value = OCELOT_FPGA_READ(UART_INTMASK);
value |= 1 << (irq - 74);
OCELOT_FPGA_WRITE(value, UART_INTMASK);
/* read the value back to assure that it's really been written */
value = OCELOT_FPGA_READ(UART_INTMASK);
}
/* unmask an interrupt -- 0 is enable, 1 is disable */
static inline void unmask_uart_irq(unsigned int irq)
{
uint8_t value;
value = OCELOT_FPGA_READ(UART_INTMASK);
value &= ~(1 << (irq - 74));
OCELOT_FPGA_WRITE(value, UART_INTMASK);
/* read the value back to assure that it's really been written */
value = OCELOT_FPGA_READ(UART_INTMASK);
}
/*
* Enables the IRQ in the FPGA
*/
static void enable_uart_irq(unsigned int irq)
{
unmask_uart_irq(irq);
}
/*
* Initialize the IRQ in the FPGA
*/
static unsigned int startup_uart_irq(unsigned int irq)
{
unmask_uart_irq(irq);
return 0;
}
/*
* Disables the IRQ in the FPGA
*/
static void disable_uart_irq(unsigned int irq)
{
mask_uart_irq(irq);
}
/*
* Masks and ACKs an IRQ
*/
static void mask_and_ack_uart_irq(unsigned int irq)
{
mask_uart_irq(irq);
}
/*
* End IRQ processing
*/
static void end_uart_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
unmask_uart_irq(irq);
}
/*
* Interrupt handler for interrupts coming from the FPGA chip.
*/
void ll_uart_irq(struct pt_regs *regs)
{
unsigned int irq_src, irq_mask;
/* read the interrupt status registers */
irq_src = OCELOT_FPGA_READ(UART_INTSTAT);
irq_mask = OCELOT_FPGA_READ(UART_INTMASK);
/* mask for just the interrupts we want */
irq_src &= ~irq_mask;
do_IRQ(ls1bit8(irq_src) + 74, regs);
}
#define shutdown_uart_irq disable_uart_irq
struct hw_interrupt_type uart_irq_type = {
"UART/FPGA",
startup_uart_irq,
shutdown_uart_irq,
enable_uart_irq,
disable_uart_irq,
mask_and_ack_uart_irq,
end_uart_irq,
NULL
};
void uart_irq_init(void)
{
/* Reset irq handlers pointers to NULL */
irq_desc[80].status = IRQ_DISABLED;
irq_desc[80].action = 0;
irq_desc[80].depth = 2;
irq_desc[80].handler = &uart_irq_type;
irq_desc[81].status = IRQ_DISABLED;
irq_desc[81].action = 0;
irq_desc[81].depth = 2;
irq_desc[81].handler = &uart_irq_type;
}
arch/mips/momentum/ocelot_g/Makefile 0 → 100644
View file @ 98ebe7d3
#
# Makefile for Momentum Computer's Ocelot-G board.
#
obj-y += gt-irq.o pci-irq.o int-handler.o irq.o prom.o \
reset.o setup.o
obj-$(CONFIG_KGDB) += dbg_io.o
EXTRA_AFLAGS := $(CFLAGS)
arch/mips/momentum/ocelot_g/dbg_io.c 0 → 100644
View file @ 98ebe7d3
#include <linux/config.h>
#if defined(CONFIG_KGDB)
#include <asm/serial.h> /* For the serial port location and base baud */
/* --- CONFIG --- */
typedef unsigned char uint8;
typedef unsigned int uint32;
/* --- END OF CONFIG --- */
#define UART16550_BAUD_2400 2400
#define UART16550_BAUD_4800 4800
#define UART16550_BAUD_9600 9600
#define UART16550_BAUD_19200 19200
#define UART16550_BAUD_38400 38400
#define UART16550_BAUD_57600 57600
#define UART16550_BAUD_115200 115200
#define UART16550_PARITY_NONE 0
#define UART16550_PARITY_ODD 0x08
#define UART16550_PARITY_EVEN 0x18
#define UART16550_PARITY_MARK 0x28
#define UART16550_PARITY_SPACE 0x38
#define UART16550_DATA_5BIT 0x0
#define UART16550_DATA_6BIT 0x1
#define UART16550_DATA_7BIT 0x2
#define UART16550_DATA_8BIT 0x3
#define UART16550_STOP_1BIT 0x0
#define UART16550_STOP_2BIT 0x4
/* ----------------------------------------------------- */
/* === CONFIG === */
/* [jsun] we use the second serial port for kdb */
#define BASE OCELOT_SERIAL1_BASE
#define MAX_BAUD OCELOT_BASE_BAUD
/* === END OF CONFIG === */
#define REG_OFFSET 4
/* register offset */
#define OFS_RCV_BUFFER 0
#define OFS_TRANS_HOLD 0
#define OFS_SEND_BUFFER 0
#define OFS_INTR_ENABLE (1*REG_OFFSET)
#define OFS_INTR_ID (2*REG_OFFSET)
#define OFS_DATA_FORMAT (3*REG_OFFSET)
#define OFS_LINE_CONTROL (3*REG_OFFSET)
#define OFS_MODEM_CONTROL (4*REG_OFFSET)
#define OFS_RS232_OUTPUT (4*REG_OFFSET)
#define OFS_LINE_STATUS (5*REG_OFFSET)
#define OFS_MODEM_STATUS (6*REG_OFFSET)
#define OFS_RS232_INPUT (6*REG_OFFSET)
#define OFS_SCRATCH_PAD (7*REG_OFFSET)
#define OFS_DIVISOR_LSB (0*REG_OFFSET)
#define OFS_DIVISOR_MSB (1*REG_OFFSET)
/* memory-mapped read/write of the port */
#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
/* disable interrupts */
UART16550_WRITE(OFS_INTR_ENABLE, 0);
/* set up buad rate */
{
uint32 divisor;
/* set DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
/* set divisor */
divisor = MAX_BAUD / baud;
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
/* clear DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
}
/* set data format */
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
}
static int remoteDebugInitialized = 0;
uint8 getDebugChar(void)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_38400,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
return UART16550_READ(OFS_RCV_BUFFER);
}
int putDebugChar(uint8 byte)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_38400,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
UART16550_WRITE(OFS_SEND_BUFFER, byte);
return 1;
}
#endif
arch/mips/momentum/ocelot_g/gt-irq.c 0 → 100644
View file @ 98ebe7d3
/*
*
* Copyright 2002 Momentum Computer
* Author: mdharm@momenco.com
*
* arch/mips/momentum/ocelot_g/gt_irq.c
* Interrupt routines for gt64240. Currently it only handles timer irq.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <asm/ptrace.h>
#include <linux/config.h>
#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <asm/io.h>
#include "gt64240.h"
unsigned long bus_clock;
/*
* These are interrupt handlers for the GT on-chip interrupts. They
* all come in to the MIPS on a single interrupt line, and have to
* be handled and ack'ed differently than other MIPS interrupts.
*/
#if CURRENTLY_UNUSED
struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];
void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr);
/*
* Hooks IRQ handler to the system. When the system is interrupted
* the interrupt service routine is called.
*
* Inputs :
* int_cause - The interrupt cause number. In EVB64120 two parameters
* are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
* bit_num - Indicates which bit number in the cause register
* isr_ptr - Pointer to the interrupt service routine
*/
void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr)
{
irq_handlers[int_cause][bit_num].routine = isr_ptr;
}
/*
* Enables the IRQ on Galileo Chip
*
* Inputs :
* int_cause - The interrupt cause number. In EVB64120 two parameters
* are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
* bit_num - Indicates which bit number in the cause register
*
* Outputs :
* 1 if succesful, 0 if failure
*/
int enable_galileo_irq(int int_cause, int bit_num)
{
if (int_cause == INT_CAUSE_MAIN)
SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num));
else if (int_cause == INT_CAUSE_HIGH)
SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
(1 << bit_num));
else
return 0;
return 1;
}
/*
* Disables the IRQ on Galileo Chip
*
* Inputs :
* int_cause - The interrupt cause number. In EVB64120 two parameters
* are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
* bit_num - Indicates which bit number in the cause register
*
* Outputs :
* 1 if succesful, 0 if failure
*/
int disable_galileo_irq(int int_cause, int bit_num)
{
if (int_cause == INT_CAUSE_MAIN)
RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER,
(1 << bit_num));
else if (int_cause == INT_CAUSE_HIGH)
RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
(1 << bit_num));
else
return 0;
return 1;
}
#endif /* UNUSED */
/*
* Interrupt handler for interrupts coming from the Galileo chip via P0_INT#.
*
* We route the timer interrupt to P0_INT# (IRQ 6), and that's all this
* routine can handle, for now.
*
* In the future, we'll route more interrupts to this pin, and that's why
* we keep this particular structure in the function.
*/
static void gt64240_p0int_irq(int irq, void *dev_id, struct pt_regs *regs)
{
uint32_t irq_src, irq_src_mask;
int handled;
/* get the low interrupt cause register */
GT_READ(LOW_INTERRUPT_CAUSE_REGISTER, &irq_src);
/* get the mask register for this pin */
GT_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, &irq_src_mask);
/* mask off only the interrupts we're interested in */
irq_src = irq_src & irq_src_mask;
handled = 0;
/* Check for timer interrupt */
if (irq_src & 0x00000100) {
handled = 1;
irq_src &= ~0x00000100;
/* Clear any pending cause bits */
GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
/* handle the timer call */
do_timer(regs);
}
if (irq_src) {
printk(KERN_INFO
"UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n",
irq_src);
}
}
/*
* Interrupt handler for interrupts coming from the Galileo chip.
* It could be built in ethernet ports etc...
*/
static void gt64240_irq(int irq, void *dev_id, struct pt_regs *regs)
{
unsigned int irq_src, int_high_src, irq_src_mask,
int_high_src_mask;
int handled;
#if 0
GT_READ(GT_INTRCAUSE_OFS, &irq_src);
GT_READ(GT_INTRMASK_OFS, &irq_src_mask);
GT_READ(GT_HINTRCAUSE_OFS, &int_high_src);
GT_READ(GT_HINTRMASK_OFS, &int_high_src_mask);
#endif
irq_src = irq_src & irq_src_mask;
int_high_src = int_high_src & int_high_src_mask;
handled = 0;
/* Execute all interrupt handlers */
/* Check for timer interrupt */
if (irq_src & 0x00000800) {
handled = 1;
irq_src &= ~0x00000800;
// RESET_REG_BITS (INTERRUPT_CAUSE_REGISTER,BIT8);
do_timer(regs);
}
if (irq_src) {
printk(KERN_INFO
"Other Galileo interrupt received irq_src %x\n",
irq_src);
#if CURRENTLY_UNUSED
for (count = 0; count < MAX_CAUSE_REG_WIDTH; count++) {
if (irq_src & (1 << count)) {
if (irq_handlers[INT_CAUSE_MAIN][count].
routine) {
queue_task(&irq_handlers
[INT_CAUSE_MAIN][count],
&tq_immediate);
mark_bh(IMMEDIATE_BH);
handled = 1;
}
}
}
#endif /* UNUSED */
}
#if 0
GT_WRITE(GT_INTRCAUSE_OFS, 0);
GT_WRITE(GT_HINTRCAUSE_OFS, 0);
#endif
#undef GALILEO_I2O
#ifdef GALILEO_I2O
/*
* Future I2O support. We currently attach I2O interrupt handlers to
* the Galileo interrupt (int 4) and handle them in do_IRQ.
*/
if (isInBoundDoorBellInterruptSet()) {
printk(KERN_INFO "I2O doorbell interrupt received.\n");
handled = 1;
}
if (isInBoundPostQueueInterruptSet()) {
printk(KERN_INFO "I2O Queue interrupt received.\n");
handled = 1;
}
/*
* This normally would be outside of the ifdef, but since we're
* handling I2O outside of this handler, this printk shows up every
* time we get a valid I2O interrupt. So turn this off for now.
*/
if (handled == 0) {
if (counter < 50) {
printk("Spurious Galileo interrupt...\n");
counter++;
}
}
#endif
}
/*
* Initializes timer using galileo's built in timer.
*/
/*
* This will ignore the standard MIPS timer interrupt handler
* that is passed in as *irq (=irq0 in ../kernel/time.c).
* We will do our own timer interrupt handling.
*/
void gt64240_time_init(void)
{
extern irq_desc_t irq_desc[NR_IRQS];
static struct irqaction timer;
/* Stop the timer -- we'll use timer #0 */
GT_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0);
/* Load timer value for 100 Hz */
GT_WRITE(TIMER_COUNTER0, bus_clock / 100);
/*
* Create the IRQ structure entry for the timer. Since we're too early
* in the boot process to use the "request_irq()" call, we'll hard-code
* the values to the correct interrupt line.
*/
timer.handler = &gt64240_p0int_irq;
timer.flags = SA_SHIRQ | SA_INTERRUPT;
timer.name = "timer";
timer.dev_id = NULL;
timer.next = NULL;
timer.mask = 0;
irq_desc[6].action = &timer;
enable_irq(6);
/* Clear any pending cause bits */
GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
/* Enable the interrupt for timer 0 */
GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1);
/* Enable the timer interrupt for GT-64240 pin P0_INT# */
GT_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100);
/* Configure and start the timer */
GT_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3);
}
void gt64240_irq_init(void)
{
#if CURRENTLY_UNUSED
int i, j;
/* Reset irq handlers pointers to NULL */
for (i = 0; i < MAX_CAUSE_REGS; i++) {
for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) {
irq_handlers[i][j].next = NULL;
irq_handlers[i][j].sync = 0;
irq_handlers[i][j].routine = NULL;
irq_handlers[i][j].data = NULL;
}
}
#endif
}
arch/mips/momentum/ocelot_g/gt64240.h 0 → 100644
View file @ 98ebe7d3
/* gt64240r.h - GT-64240 Internal registers definition file */
/* Copyright - Galileo technology. */
#ifndef __INCgt64240rh
#define __INCgt64240rh
#define GTREG(v) (((v) & 0xff) << 24) | (((v) & 0xff00) << 8) | \
(((v) >> 24) & 0xff) | (((v) >> 8) & 0xff00)
#if 0
#define GTREG_SHORT(X) (((X) << 8) | ((X) >> 8))
#define LONG_GTREG(X) ((l64) \
(((X)&0x00000000000000ffULL) << 56) | \
(((X)&0x000000000000ff00ULL) << 40) | \
(((X)&0x0000000000ff0000ULL) << 24) | \
(((X)&0x00000000ff000000ULL) << 8) | \
(((X)&0x000000ff00000000ULL) >> 8) | \
(((X)&0x0000ff0000000000ULL) >> 24) | \
(((X)&0x00ff000000000000ULL) >> 40) | \
(((X)&0xff00000000000000ULL) >> 56))
#endif
#include "gt64240_dep.h"
/****************************************/
/* CPU Control Registers */
/****************************************/
#define CPU_CONFIGURATION 0x000
#define CPU_MODE 0x120
#define CPU_READ_RESPONSE_CROSSBAR_LOW 0x170
#define CPU_READ_RESPONSE_CROSSBAR_HIGH 0x178
/****************************************/
/* Processor Address Space */
/****************************************/
/* Sdram's BAR'S */
#define SCS_0_LOW_DECODE_ADDRESS 0x008
#define SCS_0_HIGH_DECODE_ADDRESS 0x010
#define SCS_1_LOW_DECODE_ADDRESS 0x208
#define SCS_1_HIGH_DECODE_ADDRESS 0x210
#define SCS_2_LOW_DECODE_ADDRESS 0x018
#define SCS_2_HIGH_DECODE_ADDRESS 0x020
#define SCS_3_LOW_DECODE_ADDRESS 0x218
#define SCS_3_HIGH_DECODE_ADDRESS 0x220
/* Devices BAR'S */
#define CS_0_LOW_DECODE_ADDRESS 0x028
#define CS_0_HIGH_DECODE_ADDRESS 0x030
#define CS_1_LOW_DECODE_ADDRESS 0x228
#define CS_1_HIGH_DECODE_ADDRESS 0x230
#define CS_2_LOW_DECODE_ADDRESS 0x248
#define CS_2_HIGH_DECODE_ADDRESS 0x250
#define CS_3_LOW_DECODE_ADDRESS 0x038
#define CS_3_HIGH_DECODE_ADDRESS 0x040
#define BOOTCS_LOW_DECODE_ADDRESS 0x238
#define BOOTCS_HIGH_DECODE_ADDRESS 0x240
#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048
#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050
#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058
#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060
#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080
#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088
#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258
#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260
#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280
#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288
#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090
#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098
#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0
#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8
#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0
#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8
#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0
#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8
#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0
#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8
#define INTERNAL_SPACE_DECODE 0x068
#define CPU_0_LOW_DECODE_ADDRESS 0x290
#define CPU_0_HIGH_DECODE_ADDRESS 0x298
#define CPU_1_LOW_DECODE_ADDRESS 0x2c0
#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8
#define PCI_0I_O_ADDRESS_REMAP 0x0f0
#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8
#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320
#define PCI_0MEMORY1_ADDRESS_REMAP 0x100
#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328
#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8
#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330
#define PCI_0MEMORY3_ADDRESS_REMAP 0x300
#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338
#define PCI_1I_O_ADDRESS_REMAP 0x108
#define PCI_1MEMORY0_ADDRESS_REMAP 0x110
#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340
#define PCI_1MEMORY1_ADDRESS_REMAP 0x118
#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348
#define PCI_1MEMORY2_ADDRESS_REMAP 0x310
#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350
#define PCI_1MEMORY3_ADDRESS_REMAP 0x318
#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358
/****************************************/
/* CPU Sync Barrier */
/****************************************/
#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0
#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8
/****************************************/
/* CPU Access Protect */
/****************************************/
#define CPU_LOW_PROTECT_ADDRESS_0 0X180
#define CPU_HIGH_PROTECT_ADDRESS_0 0X188
#define CPU_LOW_PROTECT_ADDRESS_1 0X190
#define CPU_HIGH_PROTECT_ADDRESS_1 0X198
#define CPU_LOW_PROTECT_ADDRESS_2 0X1a0
#define CPU_HIGH_PROTECT_ADDRESS_2 0X1a8
#define CPU_LOW_PROTECT_ADDRESS_3 0X1b0
#define CPU_HIGH_PROTECT_ADDRESS_3 0X1b8
#define CPU_LOW_PROTECT_ADDRESS_4 0X1c0
#define CPU_HIGH_PROTECT_ADDRESS_4 0X1c8
#define CPU_LOW_PROTECT_ADDRESS_5 0X1d0
#define CPU_HIGH_PROTECT_ADDRESS_5 0X1d8
#define CPU_LOW_PROTECT_ADDRESS_6 0X1e0
#define CPU_HIGH_PROTECT_ADDRESS_6 0X1e8
#define CPU_LOW_PROTECT_ADDRESS_7 0X1f0
#define CPU_HIGH_PROTECT_ADDRESS_7 0X1f8
/****************************************/
/* Snoop Control */
/****************************************/
#define SNOOP_BASE_ADDRESS_0 0x380
#define SNOOP_TOP_ADDRESS_0 0x388
#define SNOOP_BASE_ADDRESS_1 0x390
#define SNOOP_TOP_ADDRESS_1 0x398
#define SNOOP_BASE_ADDRESS_2 0x3a0
#define SNOOP_TOP_ADDRESS_2 0x3a8
#define SNOOP_BASE_ADDRESS_3 0x3b0
#define SNOOP_TOP_ADDRESS_3 0x3b8
/****************************************/
/* CPU Error Report */
/****************************************/
#define CPU_ERROR_ADDRESS_LOW 0x070
#define CPU_ERROR_ADDRESS_HIGH 0x078
#define CPU_ERROR_DATA_LOW 0x128
#define CPU_ERROR_DATA_HIGH 0x130
#define CPU_ERROR_PARITY 0x138
#define CPU_ERROR_CAUSE 0x140
#define CPU_ERROR_MASK 0x148
/****************************************/
/* Pslave Debug */
/****************************************/
#define X_0_ADDRESS 0x360
#define X_0_COMMAND_ID 0x368
#define X_1_ADDRESS 0x370
#define X_1_COMMAND_ID 0x378
#define WRITE_DATA_LOW 0x3c0
#define WRITE_DATA_HIGH 0x3c8
#define WRITE_BYTE_ENABLE 0X3e0
#define READ_DATA_LOW 0x3d0
#define READ_DATA_HIGH 0x3d8
#define READ_ID 0x3e8
/****************************************/
/* SDRAM and Device Address Space */
/****************************************/
/****************************************/
/* SDRAM Configuration */
/****************************************/
#define SDRAM_CONFIGURATION 0x448
#define SDRAM_OPERATION_MODE 0x474
#define SDRAM_ADDRESS_DECODE 0x47C
#define SDRAM_TIMING_PARAMETERS 0x4b4
#define SDRAM_UMA_CONTROL 0x4a4
#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8
#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac
#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0
/****************************************/
/* SDRAM Parameters */
/****************************************/
#define SDRAM_BANK0PARAMETERS 0x44C
#define SDRAM_BANK1PARAMETERS 0x450
#define SDRAM_BANK2PARAMETERS 0x454
#define SDRAM_BANK3PARAMETERS 0x458
/****************************************/
/* SDRAM Error Report */
/****************************************/
#define SDRAM_ERROR_DATA_LOW 0x484
#define SDRAM_ERROR_DATA_HIGH 0x480
#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490
#define SDRAM_RECEIVED_ECC 0x488
#define SDRAM_CALCULATED_ECC 0x48c
#define SDRAM_ECC_CONTROL 0x494
#define SDRAM_ECC_ERROR_COUNTER 0x498
/****************************************/
/* SDunit Debug (for internal use) */
/****************************************/
#define X0_ADDRESS 0x500
#define X0_COMMAND_AND_ID 0x504
#define X0_WRITE_DATA_LOW 0x508
#define X0_WRITE_DATA_HIGH 0x50c
#define X0_WRITE_BYTE_ENABLE 0x518
#define X0_READ_DATA_LOW 0x510
#define X0_READ_DATA_HIGH 0x514
#define X0_READ_ID 0x51c
#define X1_ADDRESS 0x520
#define X1_COMMAND_AND_ID 0x524
#define X1_WRITE_DATA_LOW 0x528
#define X1_WRITE_DATA_HIGH 0x52c
#define X1_WRITE_BYTE_ENABLE 0x538
#define X1_READ_DATA_LOW 0x530
#define X1_READ_DATA_HIGH 0x534
#define X1_READ_ID 0x53c
#define X0_SNOOP_ADDRESS 0x540
#define X0_SNOOP_COMMAND 0x544
#define X1_SNOOP_ADDRESS 0x548
#define X1_SNOOP_COMMAND 0x54c
/****************************************/
/* Device Parameters */
/****************************************/
#define DEVICE_BANK0PARAMETERS 0x45c
#define DEVICE_BANK1PARAMETERS 0x460
#define DEVICE_BANK2PARAMETERS 0x464
#define DEVICE_BANK3PARAMETERS 0x468
#define DEVICE_BOOT_BANK_PARAMETERS 0x46c
#define DEVICE_CONTROL 0x4c0
#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8
#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc
#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4
/****************************************/
/* Device Interrupt */
/****************************************/
#define DEVICE_INTERRUPT_CAUSE 0x4d0
#define DEVICE_INTERRUPT_MASK 0x4d4
#define DEVICE_ERROR_ADDRESS 0x4d8
/****************************************/
/* DMA Record */
/****************************************/
#define CHANNEL0_DMA_BYTE_COUNT 0x800
#define CHANNEL1_DMA_BYTE_COUNT 0x804
#define CHANNEL2_DMA_BYTE_COUNT 0x808
#define CHANNEL3_DMA_BYTE_COUNT 0x80C
#define CHANNEL4_DMA_BYTE_COUNT 0x900
#define CHANNEL5_DMA_BYTE_COUNT 0x904
#define CHANNEL6_DMA_BYTE_COUNT 0x908
#define CHANNEL7_DMA_BYTE_COUNT 0x90C
#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810
#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814
#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818
#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C
#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910
#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914
#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918
#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C
#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820
#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824
#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828
#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C
#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920
#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924
#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928
#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C
#define CHANNEL0NEXT_RECORD_POINTER 0x830
#define CHANNEL1NEXT_RECORD_POINTER 0x834
#define CHANNEL2NEXT_RECORD_POINTER 0x838
#define CHANNEL3NEXT_RECORD_POINTER 0x83C
#define CHANNEL4NEXT_RECORD_POINTER 0x930
#define CHANNEL5NEXT_RECORD_POINTER 0x934
#define CHANNEL6NEXT_RECORD_POINTER 0x938
#define CHANNEL7NEXT_RECORD_POINTER 0x93C
#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870
#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874
#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878
#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C
#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970
#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974
#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978
#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C
#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890
#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894
#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898
#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c
#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990
#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994
#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998
#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c
#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0
#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4
#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8
#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac
#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0
#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4
#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8
#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac
#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0
#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4
#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8
#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc
#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0
#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4
#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8
#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc
/****************************************/
/* DMA Channel Control */
/****************************************/
#define CHANNEL0CONTROL 0x840
#define CHANNEL0CONTROL_HIGH 0x880
#define CHANNEL1CONTROL 0x844
#define CHANNEL1CONTROL_HIGH 0x884
#define CHANNEL2CONTROL 0x848
#define CHANNEL2CONTROL_HIGH 0x888
#define CHANNEL3CONTROL 0x84C
#define CHANNEL3CONTROL_HIGH 0x88C
#define CHANNEL4CONTROL 0x940
#define CHANNEL4CONTROL_HIGH 0x980
#define CHANNEL5CONTROL 0x944
#define CHANNEL5CONTROL_HIGH 0x984
#define CHANNEL6CONTROL 0x948
#define CHANNEL6CONTROL_HIGH 0x988
#define CHANNEL7CONTROL 0x94C
#define CHANNEL7CONTROL_HIGH 0x98C
/****************************************/
/* DMA Arbiter */
/****************************************/
#define ARBITER_CONTROL_0_3 0x860
#define ARBITER_CONTROL_4_7 0x960
/****************************************/
/* DMA Interrupt */
/****************************************/
#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0
#define CHANELS0_3_INTERRUPT_MASK 0x8c4
#define CHANELS0_3_ERROR_ADDRESS 0x8c8
#define CHANELS0_3_ERROR_SELECT 0x8cc
#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0
#define CHANELS4_7_INTERRUPT_MASK 0x9c4
#define CHANELS4_7_ERROR_ADDRESS 0x9c8
#define CHANELS4_7_ERROR_SELECT 0x9cc
/****************************************/
/* DMA Debug (for internal use) */
/****************************************/
#define DMA_X0_ADDRESS 0x8e0
#define DMA_X0_COMMAND_AND_ID 0x8e4
#define DMA_X0_WRITE_DATA_LOW 0x8e8
#define DMA_X0_WRITE_DATA_HIGH 0x8ec
#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8
#define DMA_X0_READ_DATA_LOW 0x8f0
#define DMA_X0_READ_DATA_HIGH 0x8f4
#define DMA_X0_READ_ID 0x8fc
#define DMA_X1_ADDRESS 0x9e0
#define DMA_X1_COMMAND_AND_ID 0x9e4
#define DMA_X1_WRITE_DATA_LOW 0x9e8
#define DMA_X1_WRITE_DATA_HIGH 0x9ec
#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8
#define DMA_X1_READ_DATA_LOW 0x9f0
#define DMA_X1_READ_DATA_HIGH 0x9f4
#define DMA_X1_READ_ID 0x9fc
/****************************************/
/* Timer_Counter */
/****************************************/
#define TIMER_COUNTER0 0x850
#define TIMER_COUNTER1 0x854
#define TIMER_COUNTER2 0x858
#define TIMER_COUNTER3 0x85C
#define TIMER_COUNTER_0_3_CONTROL 0x864
#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
#define TIMER_COUNTER4 0x950
#define TIMER_COUNTER5 0x954
#define TIMER_COUNTER6 0x958
#define TIMER_COUNTER7 0x95C
#define TIMER_COUNTER_4_7_CONTROL 0x964
#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968
#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c
/****************************************/
/* PCI Slave Address Decoding */
/****************************************/
#define PCI_0SCS_0_BANK_SIZE 0xc08
#define PCI_1SCS_0_BANK_SIZE 0xc88
#define PCI_0SCS_1_BANK_SIZE 0xd08
#define PCI_1SCS_1_BANK_SIZE 0xd88
#define PCI_0SCS_2_BANK_SIZE 0xc0c
#define PCI_1SCS_2_BANK_SIZE 0xc8c
#define PCI_0SCS_3_BANK_SIZE 0xd0c
#define PCI_1SCS_3_BANK_SIZE 0xd8c
#define PCI_0CS_0_BANK_SIZE 0xc10
#define PCI_1CS_0_BANK_SIZE 0xc90
#define PCI_0CS_1_BANK_SIZE 0xd10
#define PCI_1CS_1_BANK_SIZE 0xd90
#define PCI_0CS_2_BANK_SIZE 0xd18
#define PCI_1CS_2_BANK_SIZE 0xd98
#define PCI_0CS_3_BANK_SIZE 0xc14
#define PCI_1CS_3_BANK_SIZE 0xc94
#define PCI_0CS_BOOT_BANK_SIZE 0xd14
#define PCI_1CS_BOOT_BANK_SIZE 0xd94
#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c
#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c
#define PCI_0P2P_MEM1_BAR_SIZE 0xd20
#define PCI_1P2P_MEM1_BAR_SIZE 0xda0
#define PCI_0P2P_I_O_BAR_SIZE 0xd24
#define PCI_1P2P_I_O_BAR_SIZE 0xda4
#define PCI_0CPU_BAR_SIZE 0xd28
#define PCI_1CPU_BAR_SIZE 0xda8
#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00
#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80
#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04
#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84
#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08
#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88
#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c
#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c
#define PCI_0DAC_CS_0_BANK_SIZE 0xe10
#define PCI_1DAC_CS_0_BANK_SIZE 0xe90
#define PCI_0DAC_CS_1_BANK_SIZE 0xe14
#define PCI_1DAC_CS_1_BANK_SIZE 0xe94
#define PCI_0DAC_CS_2_BANK_SIZE 0xe18
#define PCI_1DAC_CS_2_BANK_SIZE 0xe98
#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c
#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c
#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20
#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0
#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24
#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4
#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28
#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8
#define PCI_0DAC_CPU_BAR_SIZE 0xe2c
#define PCI_1DAC_CPU_BAR_SIZE 0xeac
#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c
#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac
#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c
#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc
#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48
#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8
#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48
#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8
#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c
#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc
#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c
#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc
#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50
#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0
#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50
#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0
#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58
#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8
#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54
#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4
#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54
#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4
#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c
#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc
#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60
#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0
#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64
#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4
#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68
#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8
#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c
#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec
#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70
#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0
#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00
#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0
#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04
#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84
#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08
#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88
#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c
#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c
#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10
#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90
#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14
#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94
#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18
#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98
#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c
#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c
#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20
#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0
#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24
#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4
#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28
#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8
#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c
#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac
#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30
#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0
#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34
#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4
#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38
#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8
#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c
#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc
/****************************************/
/* PCI Control */
/****************************************/
#define PCI_0COMMAND 0xc00
#define PCI_1COMMAND 0xc80
#define PCI_0MODE 0xd00
#define PCI_1MODE 0xd80
#define PCI_0TIMEOUT_RETRY 0xc04
#define PCI_1TIMEOUT_RETRY 0xc84
#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04
#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84
#define MSI_0TRIGGER_TIMER 0xc38
#define MSI_1TRIGGER_TIMER 0xcb8
#define PCI_0ARBITER_CONTROL 0x1d00
#define PCI_1ARBITER_CONTROL 0x1d80
/* changing untill here */
#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08
#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c
#define PCI_0CROSS_BAR_TIMEOUT 0x1d04
#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18
#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c
#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10
#define PCI_0P2P_CONFIGURATION 0x1d14
#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00
#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04
#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08
#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0c1e10
#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14
#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18
#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0c1e20
#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24
#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28
#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0c1e30
#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34
#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38
#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0c1e40
#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44
#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48
#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0c1e50
#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54
#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58
#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0c1e60
#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64
#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68
#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0c1e70
#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74
#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78
#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88
#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c
#define PCI_1CROSS_BAR_TIMEOUT 0x1d84
#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98
#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c
#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90
#define PCI_1P2P_CONFIGURATION 0x1d94
#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80
#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84
#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88
#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0c1e90
#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94
#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98
#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0c1ea0
#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8
#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0c1eb0
#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8
#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0c1ec0
#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8
#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0c1ed0
#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8
#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0c1ee0
#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4
#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8
#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0c1ef0
#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4
#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8
/****************************************/
/* PCI Snoop Control */
/****************************************/
#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00
#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04
#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08
#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10
#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14
#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18
#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20
#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24
#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28
#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30
#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34
#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38
#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80
#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84
#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88
#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90
#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94
#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98
#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0
#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4
#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8
#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0
#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4
#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8
/****************************************/
/* PCI Configuration Address */
/****************************************/
#define PCI_0CONFIGURATION_ADDRESS 0xcf8
#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc
#define PCI_1CONFIGURATION_ADDRESS 0xc78
#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c
#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34
#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4
/****************************************/
/* PCI Error Report */
/****************************************/
#define PCI_0SERR_MASK 0xc28
#define PCI_0ERROR_ADDRESS_LOW 0x1d40
#define PCI_0ERROR_ADDRESS_HIGH 0x1d44
#define PCI_0ERROR_DATA_LOW 0x1d48
#define PCI_0ERROR_DATA_HIGH 0x1d4c
#define PCI_0ERROR_COMMAND 0x1d50
#define PCI_0ERROR_CAUSE 0x1d58
#define PCI_0ERROR_MASK 0x1d5c
#define PCI_1SERR_MASK 0xca8
#define PCI_1ERROR_ADDRESS_LOW 0x1dc0
#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4
#define PCI_1ERROR_DATA_LOW 0x1dc8
#define PCI_1ERROR_DATA_HIGH 0x1dcc
#define PCI_1ERROR_COMMAND 0x1dd0
#define PCI_1ERROR_CAUSE 0x1dd8
#define PCI_1ERROR_MASK 0x1ddc
/****************************************/
/* Lslave Debug (for internal use) */
/****************************************/
#define L_SLAVE_X0_ADDRESS 0x1d20
#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24
#define L_SLAVE_X1_ADDRESS 0x1d28
#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c
#define L_SLAVE_WRITE_DATA_LOW 0x1d30
#define L_SLAVE_WRITE_DATA_HIGH 0x1d34
#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60
#define L_SLAVE_READ_DATA_LOW 0x1d38
#define L_SLAVE_READ_DATA_HIGH 0x1d3c
#define L_SLAVE_READ_ID 0x1d64
/****************************************/
/* PCI Configuration Function 0 */
/****************************************/
#define PCI_DEVICE_AND_VENDOR_ID 0x000
#define PCI_STATUS_AND_COMMAND 0x004
#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
#define PCI_SCS_0_BASE_ADDRESS 0x010
#define PCI_SCS_1_BASE_ADDRESS 0x014
#define PCI_SCS_2_BASE_ADDRESS 0x018
#define PCI_SCS_3_BASE_ADDRESS 0x01C
#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020
#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024
#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C
#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030
#define PCI_CAPABILTY_LIST_POINTER 0x034
#define PCI_INTERRUPT_PIN_AND_LINE 0x03C
#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
#define PCI_VPD_ADDRESS 0x048
#define PCI_VPD_DATA 0X04c
#define PCI_MSI_MESSAGE_CONTROL 0x050
#define PCI_MSI_MESSAGE_ADDRESS 0x054
#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058
#define PCI_MSI_MESSAGE_DATA 0x05c
#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058
/****************************************/
/* PCI Configuration Function 1 */
/****************************************/
#define PCI_CS_0_BASE_ADDRESS 0x110
#define PCI_CS_1_BASE_ADDRESS 0x114
#define PCI_CS_2_BASE_ADDRESS 0x118
#define PCI_CS_3_BASE_ADDRESS 0x11c
#define PCI_BOOTCS_BASE_ADDRESS 0x120
/****************************************/
/* PCI Configuration Function 2 */
/****************************************/
#define PCI_P2P_MEM0_BASE_ADDRESS 0x210
#define PCI_P2P_MEM1_BASE_ADDRESS 0x214
#define PCI_P2P_I_O_BASE_ADDRESS 0x218
#define PCI_CPU_BASE_ADDRESS 0x21c
/****************************************/
/* PCI Configuration Function 4 */
/****************************************/
#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410
#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414
#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418
#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c
#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420
#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424
/****************************************/
/* PCI Configuration Function 5 */
/****************************************/
#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510
#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514
#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518
#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c
#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520
#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524
/****************************************/
/* PCI Configuration Function 6 */
/****************************************/
#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610
#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614
#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618
#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c
#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620
#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624
/****************************************/
/* PCI Configuration Function 7 */
/****************************************/
#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710
#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714
#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718
#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c
#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720
#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724
/****************************************/
/* Interrupts */
/****************************************/
#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18
#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68
#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c
#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c
#define CPU_SELECT_CAUSE_REGISTER 0xc70
#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24
#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64
#define PCI_0SELECT_CAUSE 0xc74
#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4
#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4
#define PCI_1SELECT_CAUSE 0xcf4
#define CPU_INT_0_MASK 0xe60
#define CPU_INT_1_MASK 0xe64
#define CPU_INT_2_MASK 0xe68
#define CPU_INT_3_MASK 0xe6c
/****************************************/
/* I20 Support registers */
/****************************************/
#define INBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x010
#define INBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x014
#define OUTBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x018
#define OUTBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x01C
#define INBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x020
#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x024
#define INBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x028
#define OUTBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x02C
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x030
#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x034
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x040
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x044
#define QUEUE_CONTROL_REGISTER_PCI0_SIDE 0x050
#define QUEUE_BASE_ADDRESS_REGISTER_PCI0_SIDE 0x054
#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x060
#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x064
#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x068
#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x06C
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x070
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x074
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x0F8
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x0FC
#define INBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x090
#define INBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x094
#define OUTBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x098
#define OUTBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x09C
#define INBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0A0
#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0A4
#define INBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0A8
#define OUTBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0AC
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0B0
#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0B4
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C0
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C4
#define QUEUE_CONTROL_REGISTER_PCI1_SIDE 0x0D0
#define QUEUE_BASE_ADDRESS_REGISTER_PCI1_SIDE 0x0D4
#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E0
#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0E4
#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E8
#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0EC
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0F0
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0F4
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x078
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x07C
#define INBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C10
#define INBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C14
#define OUTBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C18
#define OUTBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C1C
#define INBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C20
#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C24
#define INBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C28
#define OUTBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C2C
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C30
#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C34
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C40
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C44
#define QUEUE_CONTROL_REGISTER_CPU0_SIDE 0X1C50
#define QUEUE_BASE_ADDRESS_REGISTER_CPU0_SIDE 0X1C54
#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C60
#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C64
#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C68
#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C6C
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C70
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C74
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1CF8
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1CFC
#define INBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C90
#define INBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C94
#define OUTBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C98
#define OUTBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C9C
#define INBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CA0
#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CA4
#define INBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CA8
#define OUTBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CAC
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CB0
#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CB4
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC0
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC4
#define QUEUE_CONTROL_REGISTER_CPU1_SIDE 0X1CD0
#define QUEUE_BASE_ADDRESS_REGISTER_CPU1_SIDE 0X1CD4
#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE0
#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CE4
#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE8
#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CEC
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CF0
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CF4
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1C78
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1C7C
/****************************************/
/* Communication Unit Registers */
/****************************************/
#define ETHERNET_0_ADDRESS_CONTROL_LOW
#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204
#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208
#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c
#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210
#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218
#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220
#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224
#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228
#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c
#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230
#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238
#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240
#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244
#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248
#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c
#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250
#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258
#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280
#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284
#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288
#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c
#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290
#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294
#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2a0
#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2a4
#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2a8
#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2ac
#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b0
#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b4
#define MPSC_2_ADDRESS_CONTROL_LOW 0xf2c0
#define MPSC_2_ADDRESS_CONTROL_HIGH 0xf2c4
#define MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8
#define MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc
#define MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0
#define MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4
#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320
#define SERIAL_INIT_LAST_DATA 0xf324
#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328
#define COMM_UNIT_ARBITER_CONTROL 0xf300
#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304
#define COMM_UNIT_INTERRUPT_CAUSE 0xf310
#define COMM_UNIT_INTERRUPT_MASK 0xf314
#define COMM_UNIT_ERROR_ADDRESS 0xf314
/****************************************/
/* Cunit Debug (for internal use) */
/****************************************/
#define CUNIT_ADDRESS 0xf340
#define CUNIT_COMMAND_AND_ID 0xf344
#define CUNIT_WRITE_DATA_LOW 0xf348
#define CUNIT_WRITE_DATA_HIGH 0xf34c
#define CUNIT_WRITE_BYTE_ENABLE 0xf358
#define CUNIT_READ_DATA_LOW 0xf350
#define CUNIT_READ_DATA_HIGH 0xf354
#define CUNIT_READ_ID 0xf35c
/****************************************/
/* Fast Ethernet Unit Registers */
/****************************************/
/* Ethernet */
#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000
#define ETHERNET_SMI_REGISTER 0x2010
/* Ethernet 0 */
#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400
#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408
#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410
#define ETHERNET0_PORT_STATUS_REGISTER 0x2418
#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420
#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428
#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430
#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438
#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440
#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448
#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450
#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458
#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480
#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484
#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488
#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c
#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0
#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4
#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8
#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac
#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0
#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4
#define ETHERNET0_MIB_COUNTER_BASE 0x2500
/* Ethernet 1 */
#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800
#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808
#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810
#define ETHERNET1_PORT_STATUS_REGISTER 0x2818
#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820
#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828
#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830
#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838
#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840
#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848
#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850
#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858
#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880
#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884
#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888
#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c
#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0
#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4
#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8
#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac
#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0
#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4
#define ETHERNET1_MIB_COUNTER_BASE 0x2900
/* Ethernet 2 */
#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00
#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08
#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10
#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18
#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20
#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28
#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30
#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38
#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40
#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48
#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50
#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58
#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80
#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84
#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88
#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c
#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0
#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4
#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8
#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac
#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0
#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4
#define ETHERNET2_MIB_COUNTER_BASE 0x2d00
/****************************************/
/* SDMA Registers */
/****************************************/
#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0
#define CHANNEL0_CONFIGURATION_REGISTER 0x4000
#define CHANNEL0_COMMAND_REGISTER 0x4008
#define CHANNEL0_RX_CMD_STATUS 0x4800
#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804
#define CHANNEL0_RX_BUFFER_POINTER 0x4808
#define CHANNEL0_RX_NEXT_POINTER 0x480c
#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810
#define CHANNEL0_TX_CMD_STATUS 0x4C00
#define CHANNEL0_TX_PACKET_SIZE 0x4C04
#define CHANNEL0_TX_BUFFER_POINTER 0x4C08
#define CHANNEL0_TX_NEXT_POINTER 0x4C0c
#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10
#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14
#define CHANNEL1_CONFIGURATION_REGISTER 0x6000
#define CHANNEL1_COMMAND_REGISTER 0x6008
#define CHANNEL1_RX_CMD_STATUS 0x6800
#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x6804
#define CHANNEL1_RX_BUFFER_POINTER 0x6808
#define CHANNEL1_RX_NEXT_POINTER 0x680c
#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
#define CHANNEL1_TX_CMD_STATUS 0x6C00
#define CHANNEL1_TX_PACKET_SIZE 0x6C04
#define CHANNEL1_TX_BUFFER_POINTER 0x6C08
#define CHANNEL1_TX_NEXT_POINTER 0x6C0c
#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10
#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x6c14
/* SDMA Interrupt */
#define SDMA_CAUSE 0xb820
#define SDMA_MASK 0xb8a0
/****************************************/
/* Baude Rate Generators Registers */
/****************************************/
/* BRG 0 */
#define BRG0_CONFIGURATION_REGISTER 0xb200
#define BRG0_BAUDE_TUNING_REGISTER 0xb204
/* BRG 1 */
#define BRG1_CONFIGURATION_REGISTER 0xb208
#define BRG1_BAUDE_TUNING_REGISTER 0xb20c
/* BRG 2 */
#define BRG2_CONFIGURATION_REGISTER 0xb210
#define BRG2_BAUDE_TUNING_REGISTER 0xb214
/* BRG Interrupts */
#define BRG_CAUSE_REGISTER 0xb834
#define BRG_MASK_REGISTER 0xb8b4
/* MISC */
#define MAIN_ROUTING_REGISTER 0xb400
#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404
#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408
#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c
#define WATCHDOG_CONFIGURATION_REGISTER 0xb410
#define WATCHDOG_VALUE_REGISTER 0xb414
/****************************************/
/* Flex TDM Registers */
/****************************************/
/* FTDM Port */
#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800
#define FLEXTDM_RECEIVE_READ_POINTER 0xa804
#define FLEXTDM_CONFIGURATION_REGISTER 0xa808
#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c
#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810
#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814
#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818
/* FTDM Interrupts */
#define FTDM_CAUSE_REGISTER 0xb830
#define FTDM_MASK_REGISTER 0xb8b0
/****************************************/
/* GPP Interface Registers */
/****************************************/
#define GPP_IO_CONTROL 0xf100
#define GPP_LEVEL_CONTROL 0xf110
#define GPP_VALUE 0xf104
#define GPP_INTERRUPT_CAUSE 0xf108
#define GPP_INTERRUPT_MASK 0xf10c
#define MPP_CONTROL0 0xf000
#define MPP_CONTROL1 0xf004
#define MPP_CONTROL2 0xf008
#define MPP_CONTROL3 0xf00c
#define DEBUG_PORT_MULTIPLEX 0xf014
#define SERIAL_PORT_MULTIPLEX 0xf010
/****************************************/
/* I2C Registers */
/****************************************/
#define I2C_SLAVE_ADDRESS 0xc000
#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040
#define I2C_DATA 0xc004
#define I2C_CONTROL 0xc008
#define I2C_STATUS_BAUDE_RATE 0xc00C
#define I2C_SOFT_RESET 0xc01c
/****************************************/
/* MPSC Registers */
/****************************************/
/* MPSC0 */
#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000
#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004
#define MPSC0_PROTOCOL_CONFIGURATION 0x8008
#define CHANNEL0_REGISTER1 0x800c
#define CHANNEL0_REGISTER2 0x8010
#define CHANNEL0_REGISTER3 0x8014
#define CHANNEL0_REGISTER4 0x8018
#define CHANNEL0_REGISTER5 0x801c
#define CHANNEL0_REGISTER6 0x8020
#define CHANNEL0_REGISTER7 0x8024
#define CHANNEL0_REGISTER8 0x8028
#define CHANNEL0_REGISTER9 0x802c
#define CHANNEL0_REGISTER10 0x8030
#define CHANNEL0_REGISTER11 0x8034
/* MPSC1 */
#define MPSC1_MAIN_CONFIGURATION_LOW 0x9000
#define MPSC1_MAIN_CONFIGURATION_HIGH 0x9004
#define MPSC1_PROTOCOL_CONFIGURATION 0x9008
#define CHANNEL1_REGISTER1 0x900c
#define CHANNEL1_REGISTER2 0x9010
#define CHANNEL1_REGISTER3 0x9014
#define CHANNEL1_REGISTER4 0x9018
#define CHANNEL1_REGISTER5 0x901c
#define CHANNEL1_REGISTER6 0x9020
#define CHANNEL1_REGISTER7 0x9024
#define CHANNEL1_REGISTER8 0x9028
#define CHANNEL1_REGISTER9 0x902c
#define CHANNEL1_REGISTER10 0x9030
#define CHANNEL1_REGISTER11 0x9034
/* MPSCs Interupts */
#define MPSC0_CAUSE 0xb804
#define MPSC0_MASK 0xb884
#define MPSC1_CAUSE 0xb80c
#define MPSC1_MASK 0xb88c
#endif /* __INCgt64240rh */
arch/mips/momentum/ocelot_g/gt64240_dep.h 0 → 100644
View file @ 98ebe7d3
/***********************************************************************
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* arch/mips/gt64240/gt64240-dep.h
* Board-dependent definitions for GT-64120 chip.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
***********************************************************************
*/
#ifndef _ASM_GT64240_DEP_H
#define _ASM_GT64240_DEP_H
#include <asm/addrspace.h> /* for KSEG1ADDR() */
#include <asm/byteorder.h> /* for cpu_to_le32() */
/*
* PCI address allocation
*/
#if 0
#define GT_PCI_MEM_BASE (0x22000000)
#define GT_PCI_MEM_SIZE GT_DEF_PCI0_MEM0_SIZE
#define GT_PCI_IO_BASE (0x20000000)
#define GT_PCI_IO_SIZE GT_DEF_PCI0_IO_SIZE
#endif
extern unsigned long gt64240_base;
#define GT64240_BASE (gt64240_base)
/*
* Because of an error/peculiarity in the Galileo chip, we need to swap the
* bytes when running bigendian.
*/
#define GT_WRITE(ofs, data) \
*(volatile u32 *)(GT64240_BASE+(ofs)) = cpu_to_le32(data)
#define GT_READ(ofs, data) \
*(data) = le32_to_cpu(*(volatile u32 *)(GT64240_BASE+(ofs)))
#define GT_READ_DATA(ofs) \
le32_to_cpu(*(volatile u32 *)(GT64240_BASE+(ofs)))
#define GT_WRITE_16(ofs, data) \
*(volatile u16 *)(GT64240_BASE+(ofs)) = cpu_to_le16(data)
#define GT_READ_16(ofs, data) \
*(data) = le16_to_cpu(*(volatile u16 *)(GT64240_BASE+(ofs)))
#define GT_WRITE_8(ofs, data) \
*(volatile u8 *)(GT64240_BASE+(ofs)) = data
#define GT_READ_8(ofs, data) \
*(data) = *(volatile u8 *)(GT64240_BASE+(ofs))
#endif /* _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H */
arch/mips/momentum/ocelot_g/int-handler.S 0 → 100644
View file @ 98ebe7d3
/*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* First-level interrupt dispatcher for ocelot board.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#define __ASSEMBLY__
#include <linux/config.h>
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
/*
* first level interrupt dispatcher for ocelot board -
* We check for the timer first, then check PCI ints A and D.
* Then check for serial IRQ and fall through.
*/
.align 5
NESTED(ocelot_handle_int, PT_SIZE, sp)
SAVE_ALL
CLI
.set at
mfc0 t0, CP0_CAUSE
mfc0 t2, CP0_STATUS
and t0, t2
andi t1, t0, STATUSF_IP2 /* int0 hardware line */
bnez t1, ll_pri_enet_irq
andi t1, t0, STATUSF_IP3 /* int1 hardware line */
bnez t1, ll_sec_enet_irq
andi t1, t0, STATUSF_IP4 /* int2 hardware line */
bnez t1, ll_uart_irq
andi t1, t0, STATUSF_IP5 /* int3 hardware line */
bnez t1, ll_cpci_irq
andi t1, t0, STATUSF_IP6 /* int4 hardware line */
bnez t1, ll_galileo_p0_irq
andi t1, t0, STATUSF_IP7 /* cpu timer */
bnez t1, ll_cputimer_irq
/* now look at the extended interrupts */
mfc0 t0, CP0_CAUSE
cfc0 t1, CP0_S1_INTCONTROL
/* shift the mask 8 bits left to line up the bits */
sll t2, t1, 8
and t0, t2
srl t0, t0, 16
andi t1, t0, STATUSF_IP8 /* int6 hardware line */
bnez t1, ll_galileo_p1_irq
andi t1, t0, STATUSF_IP9 /* int7 hardware line */
bnez t1, ll_pmc_irq
andi t1, t0, STATUSF_IP10 /* int8 hardware line */
bnez t1, ll_cpci_abcd_irq
andi t1, t0, STATUSF_IP11 /* int9 hardware line */
bnez t1, ll_testpoint_irq
.set reorder
/* wrong alarm or masked ... */
j spurious_interrupt
nop
END(ocelot_handle_int)
.align 5
ll_pri_enet_irq:
li a0, 2
move a1, sp
jal do_IRQ
j ret_from_irq
ll_sec_enet_irq:
li a0, 3
move a1, sp
jal do_IRQ
j ret_from_irq
ll_uart_irq:
li a0, 4
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpci_irq:
li a0, 5
move a1, sp
jal do_IRQ
j ret_from_irq
ll_galileo_p0_irq:
li a0, 6
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cputimer_irq:
li a0, 7
move a1, sp
jal do_IRQ
j ret_from_irq
ll_galileo_p1_irq:
li a0, 8
move a1, sp
jal do_IRQ
j ret_from_irq
ll_pmc_irq:
li a0, 9
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpci_abcd_irq:
li a0, 10
move a1, sp
jal do_IRQ
j ret_from_irq
ll_testpoint_irq:
li a0, 11
move a1, sp
jal do_IRQ
j ret_from_irq
arch/mips/momentum/ocelot_g/irq.c 0 → 100644
View file @ 98ebe7d3
/*
* Copyright (C) 2000 RidgeRun, Inc.
* Author: RidgeRun, Inc.
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
*
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
* Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <asm/bitops.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
static spinlock_t rm7000_irq_lock = SPIN_LOCK_UNLOCKED;
/* Function for careful CP0 interrupt mask access */
static inline void modify_cp0_intmask(unsigned clr_mask_in, unsigned set_mask_in)
{
unsigned long status;
unsigned clr_mask;
unsigned set_mask;
/* do the low 8 bits first */
clr_mask = 0xff & clr_mask_in;
set_mask = 0xff & set_mask_in;
status = read_c0_status();
status &= ~((clr_mask & 0xFF) << 8);
status |= (set_mask & 0xFF) << 8;
write_c0_status(status);
/* do the high 8 bits */
clr_mask = 0xff & (clr_mask_in >> 8);
set_mask = 0xff & (set_mask_in >> 8);
status = read_c0_intcontrol();
status &= ~((clr_mask & 0xFF) << 8);
status |= (set_mask & 0xFF) << 8;
write_c0_intrcontrol(status);
}
static inline void mask_irq(unsigned int irq)
{
modify_cp0_intmask(irq, 0);
}
static inline void unmask_irq(unsigned int irq)
{
modify_cp0_intmask(0, irq);
}
static void enable_cp7000_irq(unsigned int irq)
{
unsigned long flags;
spin_lock_irqsave(&rm7000_irq_lock, flags);
unmask_irq(1 << irq);
spin_unlock_irqrestore(&rm7000_irq_lock, flags);
}
static unsigned int startup_cp7000_irq(unsigned int irq)
{
enable_cp7000_irq(irq);
return 0; /* never anything pending */
}
static void disable_cp7000_irq(unsigned int irq)
{
unsigned long flags;
spin_lock_irqsave(&rm7000_irq_lock, flags);
mask_irq(1 << irq);
spin_unlock_irqrestore(&rm7000_irq_lock, flags);
}
#define shutdown_cp7000_irq disable_cp7000_irq
static void mask_and_ack_cp7000_irq(unsigned int irq)
{
mask_irq(1 << irq);
}
static void end_cp7000_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
unmask_irq(1 << irq);
}
static struct hw_interrupt_type cp7000_hpcdma_irq_type = {
"CP7000",
startup_cp7000_irq,
shutdown_cp7000_irq,
enable_cp7000_irq,
disable_cp7000_irq,
mask_and_ack_cp7000_irq,
end_cp7000_irq,
NULL
};
extern asmlinkage void ocelot_handle_int(void);
extern void gt64240_irq_init(void);
void __init init_IRQ(void)
{
int i;
/*
* Clear all of the interrupts while we change the able around a bit.
* int-handler is not on bootstrap
*/
clear_c0_status(ST0_IM | ST0_BEV);
local_irq_disable();
/* Sets the first-level interrupt dispatcher. */
set_except_vector(0, ocelot_handle_int);
init_generic_irq();
for (i = 0; i <= 15; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = &cp7000_hpcdma_irq_type;
}
gt64240_irq_init();
#ifdef CONFIG_KGDB
printk("start kgdb ...\n");
set_debug_traps();
breakpoint(); /* you may move this line to whereever you want :-) */
#endif
#ifdef CONFIG_GDB_CONSOLE
register_gdb_console();
#endif
}
arch/mips/momentum/ocelot_g/ocelot_pld.h 0 → 100644
View file @ 98ebe7d3
/*
* Ocelot Board Register Definitions
*
* (C) 2001 Red Hat, Inc.
*
* GPL'd
*/
#ifndef __MOMENCO_OCELOT_PLD_H__
#define __MOMENCO_OCELOT_PLD_H__
#define OCELOT_CS0_ADDR (0xfc000000)
#define OCELOT_REG_BOARDREV (0)
#define OCELOT_REG_PLD1_ID (1)
#define OCELOT_REG_PLD2_ID (2)
#define OCELOT_REG_RESET_STATUS (3)
#define OCELOT_REG_BOARD_STATUS (4)
#define OCELOT_REG_CPCI_ID (5)
#define OCELOT_REG_I2C_CTRL (8)
#define OCELOT_REG_EEPROM_MODE (9)
#define OCELOT_REG_INTMASK (10)
#define OCELOT_REG_INTSTATUS (11)
#define OCELOT_REG_INTSET (12)
#define OCELOT_REG_INTCLR (13)
#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y)
#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x)
#endif /* __MOMENCO_OCELOT_PLD_H__ */
arch/mips/momentum/ocelot_g/pci-irq.c 0 → 100644
View file @ 98ebe7d3
/*
* Copyright 2002 Momentum Computer Inc.
* Author: Matthew Dharm <mdharm@momenco.com>
*
* Based on work for the Linux port to the Ocelot board, which is
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* arch/mips/momentum/ocelot_g/pci.c
* Board-specific PCI routines for gt64240 controller.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/version.h>
#include <linux/init.h>
#include <asm/pci.h>
void __devinit gt64240_board_pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_bus *current_bus = bus;
struct pci_dev *devices;
struct list_head *devices_link;
u16 cmd;
/* loop over all known devices on this bus */
list_for_each(devices_link, &(current_bus->devices)) {
devices = pci_dev_b(devices_link);
if (devices == NULL)
continue;
if ((current_bus->number == 0) &&
PCI_SLOT(devices->devfn) == 1) {
/* Intel 82543 Gigabit MAC */
devices->irq = 2; /* irq_nr is 2 for INT0 */
} else if ((current_bus->number == 0) &&
PCI_SLOT(devices->devfn) == 2) {
/* Intel 82543 Gigabit MAC */
devices->irq = 3; /* irq_nr is 3 for INT1 */
} else if ((current_bus->number == 1) &&
PCI_SLOT(devices->devfn) == 3) {
/* Intel 21555 bridge */
devices->irq = 5; /* irq_nr is 8 for INT6 */
} else if ((current_bus->number == 1) &&
PCI_SLOT(devices->devfn) == 4) {
/* PMC Slot */
devices->irq = 9; /* irq_nr is 9 for INT7 */
} else {
/* We don't have assign interrupts for other devices. */
devices->irq = 0xff;
}
/* Assign an interrupt number for the device */
bus->ops->write(current_bus, devices,
PCI_INTERRUPT_LINE, 1, devices->irq);
/* enable master for everything but the GT-64240 */
if (((current_bus->number != 0) && (current_bus->number != 1))
|| (PCI_SLOT(devices->devfn) != 0)) {
bus->ops->read(current_bus, devices,
PCI_COMMAND, 2, &cmd);
cmd |= PCI_COMMAND_MASTER;
bus->ops->write(current_bus, devices,
PCI_COMMAND, 2, cmd);
}
}
}
arch/mips/momentum/ocelot_g/prom.c 0 → 100644
View file @ 98ebe7d3
/*
* Copyright 2002 Momentum Computer Inc.
* Author: Matthew Dharm <mdharm@momenco.com>
*
* Based on Ocelot Linux port, which is
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include "gt64240.h"
#include "ocelot_pld.h"
struct callvectors {
int (*open) (char*, int, int);
int (*close) (int);
int (*read) (int, void*, int);
int (*write) (int, void*, int);
off_t (*lseek) (int, off_t, int);
int (*printf) (const char*, ...);
void (*cacheflush) (void);
char* (*gets) (char*);
};
struct callvectors* debug_vectors;
char arcs_cmdline[CL_SIZE];
extern unsigned long gt64240_base;
extern unsigned long bus_clock;
#ifdef CONFIG_GALILLEO_GT64240_ETH
extern unsigned char prom_mac_addr_base[6];
#endif
const char *get_system_type(void)
{
return "Momentum Ocelot";
}
/* [jsun@junsun.net] PMON passes arguments in C main() style */
void __init prom_init(int argc, char **arg, char** env, struct callvectors *cv)
{
int i;
uint32_t tmp;
/* save the PROM vectors for debugging use */
debug_vectors = cv;
/* arg[0] is "g", the rest is boot parameters */
arcs_cmdline[0] = '\0';
for (i = 1; i < argc; i++) {
if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
>= sizeof(arcs_cmdline))
break;
strcat(arcs_cmdline, arg[i]);
strcat(arcs_cmdline, " ");
}
mips_machgroup = MACH_GROUP_MOMENCO;
mips_machtype = MACH_MOMENCO_OCELOT_G;
#ifdef CONFIG_GALILLEO_GT64240_ETH
/* get the base MAC address for on-board ethernet ports */
memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6);
#endif
while (*env) {
if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
gt64240_base = simple_strtol(*env + strlen("gtbase="),
NULL, 16);
}
if (strncmp("busclock", *env, strlen("busclock")) == 0) {
bus_clock = simple_strtol(*env + strlen("busclock="),
NULL, 10);
}
*env++;
}
debug_vectors->printf("Booting Linux kernel...\n");
}
void __init prom_free_prom_memory(void)
{
}
void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
{
}
arch/mips/momentum/ocelot_g/reset.c 0 → 100644
View file @ 98ebe7d3
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Copyright (C) 1997, 2001 Ralf Baechle
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/system.h>
#include <linux/delay.h>
void momenco_ocelot_restart(char *command)
{
void *nvram = ioremap_nocache(0x2c807000, 0x1000);
if (!nvram) {
printk(KERN_NOTICE "ioremap of reset register failed\n");
return;
}
writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to
assert reset in 1/16 second */
mdelay(10+(1000/16));
iounmap(nvram);
printk(KERN_NOTICE "Watchdog reset failed\n");
}
void momenco_ocelot_halt(void)
{
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
while (1)
__asm__(".set\tmips3\n\t"
"wait\n\t"
".set\tmips0");
}
void momenco_ocelot_power_off(void)
{
momenco_ocelot_halt();
}
arch/mips/momentum/ocelot_g/setup.c 0 → 100644
View file @ 98ebe7d3
/*
* setup.c
*
* BRIEF MODULE DESCRIPTION
* Momentum Computer Ocelot-G (CP7000G) - board dependent boot routines
*
* Copyright (C) 1996, 1997, 2001 Ralf Baechle
* Copyright (C) 2000 RidgeRun, Inc.
* Copyright (C) 2001 Red Hat, Inc.
* Copyright (C) 2002 Momentum Computer
*
* Author: Matthew Dharm, Momentum Computer
* mdharm@momenco.com
*
* Author: RidgeRun, Inc.
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mc146818rtc.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/timex.h>
#include <linux/vmalloc.h>
#include <asm/time.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pci.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/reboot.h>
#include <asm/mc146818rtc.h>
#include <linux/version.h>
#include <linux/bootmem.h>
#include <linux/blk.h>
#include "gt64240.h"
#include "ocelot_pld.h"
extern struct rtc_ops no_rtc_ops;
#ifdef CONFIG_GALILLEO_GT64240_ETH
extern unsigned char prom_mac_addr_base[6];
#endif
unsigned long gt64240_base;
/* These functions are used for rebooting or halting the machine*/
extern void momenco_ocelot_restart(char *command);
extern void momenco_ocelot_halt(void);
extern void momenco_ocelot_power_off(void);
extern void gt64240_time_init(void);
extern void momenco_ocelot_irq_setup(void);
static char reset_reason;
#define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1)
static void __init setup_l3cache(unsigned long size);
/* setup code for a handoff from a version 2 PMON 2000 PROM */
void PMON_v2_setup(void)
{
/* A wired TLB entry for the GT64240 and the serial port. The
GT64240 is going to be hit on every IRQ anyway - there's
absolutely no point in letting it be a random TLB entry, as
it'll just cause needless churning of the TLB. And we use
the other half for the serial port, which is just a PITA
otherwise :)
Device Physical Virtual
GT64240 Internal Regs 0xf4000000 0xe0000000
UARTs (CS2) 0xfd000000 0xe0001000
*/
add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
add_wired_entry(ENTRYLO(0xfd000000), ENTRYLO(0xfd001000), 0xfd000000, PM_4K);
/* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
in the CS[012] region. We can't use ioremap() yet. The NVRAM
is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
Ocelot PLD (CS0) 0xfc000000 0xe0020000
NVRAM (CS1) 0xfc800000 0xe0030000
*/
add_temporary_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfc010000), 0xfc000000, PM_64K);
add_temporary_entry(ENTRYLO(0xfc800000), ENTRYLO(0xfc810000), 0xfc800000, PM_64K);
gt64240_base = 0xf4000000;
}
void __init momenco_ocelot_g_setup(void)
{
void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
unsigned int tmpword;
board_time_init = gt64240_time_init;
_machine_restart = momenco_ocelot_restart;
_machine_halt = momenco_ocelot_halt;
_machine_power_off = momenco_ocelot_power_off;
/*
* initrd_start = (ulong)ocelot_initrd_start;
* initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
* initrd_below_start_ok = 1;
*/
rtc_ops = &no_rtc_ops;
/* do handoff reconfiguration */
PMON_v2_setup();
#ifdef CONFIG_GALILLEO_GT64240_ETH
/* get the mac addr */
memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6);
#endif
/* Turn off the Bit-Error LED */
OCELOT_PLD_WRITE(0x80, INTCLR);
tmpword = OCELOT_PLD_READ(BOARDREV);
if (tmpword < 26)
printk("Momenco Ocelot-G: Board Assembly Rev. %c\n", 'A'+tmpword);
else
printk("Momenco Ocelot-G: Board Assembly Revision #0x%x\n", tmpword);
tmpword = OCELOT_PLD_READ(PLD1_ID);
printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
tmpword = OCELOT_PLD_READ(PLD2_ID);
printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
tmpword = OCELOT_PLD_READ(RESET_STATUS);
printk("Reset reason: 0x%x\n", tmpword);
reset_reason = tmpword;
OCELOT_PLD_WRITE(0xff, RESET_STATUS);
tmpword = OCELOT_PLD_READ(BOARD_STATUS);
printk("Board Status register: 0x%02x\n", tmpword);
printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
if (tmpword&12)
l3func((1<<(((tmpword&12) >> 2)+20)));
switch(tmpword &3) {
case 3:
/* 512MiB -- two banks of 256MiB */
add_memory_region( 0x0<<20, 0x100<<20, BOOT_MEM_RAM);
/*
add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
*/
break;
case 2:
/* 256MiB -- two banks of 128MiB */
add_memory_region( 0x0<<20, 0x80<<20, BOOT_MEM_RAM);
add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
break;
case 1:
/* 128MiB -- 64MiB per bank */
add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
break;
case 0:
/* 64MiB */
add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
break;
}
/* FIXME: Fix up the DiskOnChip mapping */
GT_WRITE(0x468, 0xfef73);
}
extern int rm7k_tcache_enabled;
/*
* This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
*/
#define Page_Invalidate_T 0x16
static void __init setup_l3cache(unsigned long size)
{
int register i;
unsigned long tmp;
printk("Enabling L3 cache...");
/* Enable the L3 cache in the GT64120A's CPU Configuration register */
GT_READ(0, &tmp);
GT_WRITE(0, tmp | (1<<14));
/* Enable the L3 cache in the CPU */
set_c0_config(1<<12 /* CONF_TE */);
/* Clear the cache */
write_c0_taglo(0);
write_c0_taghi(0);
for (i=0; i < size; i+= 4096) {
__asm__ __volatile__ (
".set noreorder\n\t"
".set mips3\n\t"
"cache %1, (%0)\n\t"
".set mips0\n\t"
".set reorder"
:
: "r" (KSEG0ADDR(i)),
"i" (Page_Invalidate_T));
}
/* Let the RM7000 MM code know that the tertiary cache is enabled */
rm7k_tcache_enabled = 1;
printk("Done\n");
}
/* This needs to be one of the first initcalls, because no I/O port access
can work before this */
static int io_base_ioremap(void)
{
/* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
void *io_remap_range = ioremap(0xc0000000, 0x30000000);
if (!io_remap_range) {
panic("Could not ioremap I/O port range");
}
printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range);
set_io_port_base(io_remap_range - 0xc0000000);
return 0;
}
module_init(io_base_ioremap);
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