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Commit 9b9fe724 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
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drm/radeon/kms: clean up i2c 

- Change reg/mask names to match what we use internally
and in the bios
- Clarify how i2c over gpio on radeon actually works
Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent ab1e9ea0
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Showing with 86 additions and 67 deletions
drivers/gpu/drm/radeon/radeon_atombios.c
View file @ 9b9fe724
...@@ -82,18 +82,18 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device ...@@ -82,18 +82,18 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4; i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4; i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4; i2c.en_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4; i2c.en_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4; i2c.y_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4; i2c.y_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4; i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4; i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift); i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
i2c.mask_data_mask = (1 << gpio.ucDataMaskShift); i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
i2c.put_clk_mask = (1 << gpio.ucClkEnShift); i2c.en_clk_mask = (1 << gpio.ucClkEnShift);
i2c.put_data_mask = (1 << gpio.ucDataEnShift); i2c.en_data_mask = (1 << gpio.ucDataEnShift);
i2c.get_clk_mask = (1 << gpio.ucClkY_Shift); i2c.y_clk_mask = (1 << gpio.ucClkY_Shift);
i2c.get_data_mask = (1 << gpio.ucDataY_Shift); i2c.y_data_mask = (1 << gpio.ucDataY_Shift);
i2c.a_clk_mask = (1 << gpio.ucClkA_Shift); i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
i2c.a_data_mask = (1 << gpio.ucDataA_Shift); i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
i2c.valid = true; i2c.valid = true;
......
drivers/gpu/drm/radeon/radeon_combios.c
View file @ 9b9fe724
...@@ -450,29 +450,29 @@ struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line) ...@@ -450,29 +450,29 @@ struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
i2c.mask_data_mask = RADEON_GPIO_EN_0; i2c.mask_data_mask = RADEON_GPIO_EN_0;
i2c.a_clk_mask = RADEON_GPIO_A_1; i2c.a_clk_mask = RADEON_GPIO_A_1;
i2c.a_data_mask = RADEON_GPIO_A_0; i2c.a_data_mask = RADEON_GPIO_A_0;
i2c.put_clk_mask = RADEON_GPIO_EN_1; i2c.en_clk_mask = RADEON_GPIO_EN_1;
i2c.put_data_mask = RADEON_GPIO_EN_0; i2c.en_data_mask = RADEON_GPIO_EN_0;
i2c.get_clk_mask = RADEON_GPIO_Y_1; i2c.y_clk_mask = RADEON_GPIO_Y_1;
i2c.get_data_mask = RADEON_GPIO_Y_0; i2c.y_data_mask = RADEON_GPIO_Y_0;
if ((ddc_line == RADEON_LCD_GPIO_MASK) || if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
(ddc_line == RADEON_MDGPIO_EN_REG)) { (ddc_line == RADEON_MDGPIO_EN_REG)) {
i2c.mask_clk_reg = ddc_line; i2c.mask_clk_reg = ddc_line;
i2c.mask_data_reg = ddc_line; i2c.mask_data_reg = ddc_line;
i2c.a_clk_reg = ddc_line; i2c.a_clk_reg = ddc_line;
i2c.a_data_reg = ddc_line; i2c.a_data_reg = ddc_line;
i2c.put_clk_reg = ddc_line; i2c.en_clk_reg = ddc_line;
i2c.put_data_reg = ddc_line; i2c.en_data_reg = ddc_line;
i2c.get_clk_reg = ddc_line + 4; i2c.y_clk_reg = ddc_line + 4;
i2c.get_data_reg = ddc_line + 4; i2c.y_data_reg = ddc_line + 4;
} else { } else {
i2c.mask_clk_reg = ddc_line; i2c.mask_clk_reg = ddc_line;
i2c.mask_data_reg = ddc_line; i2c.mask_data_reg = ddc_line;
i2c.a_clk_reg = ddc_line; i2c.a_clk_reg = ddc_line;
i2c.a_data_reg = ddc_line; i2c.a_data_reg = ddc_line;
i2c.put_clk_reg = ddc_line; i2c.en_clk_reg = ddc_line;
i2c.put_data_reg = ddc_line; i2c.en_data_reg = ddc_line;
i2c.get_clk_reg = ddc_line; i2c.y_clk_reg = ddc_line;
i2c.get_data_reg = ddc_line; i2c.y_data_reg = ddc_line;
} }
if (ddc_line) if (ddc_line)
...@@ -1567,18 +1567,18 @@ static bool radeon_apply_legacy_quirks(struct drm_device *dev, ...@@ -1567,18 +1567,18 @@ static bool radeon_apply_legacy_quirks(struct drm_device *dev,
ddc_i2c->mask_data_mask = 0x80; ddc_i2c->mask_data_mask = 0x80;
ddc_i2c->a_clk_mask = (0x20 << 8); ddc_i2c->a_clk_mask = (0x20 << 8);
ddc_i2c->a_data_mask = 0x80; ddc_i2c->a_data_mask = 0x80;
ddc_i2c->put_clk_mask = (0x20 << 8); ddc_i2c->en_clk_mask = (0x20 << 8);
ddc_i2c->put_data_mask = 0x80; ddc_i2c->en_data_mask = 0x80;
ddc_i2c->get_clk_mask = (0x20 << 8); ddc_i2c->y_clk_mask = (0x20 << 8);
ddc_i2c->get_data_mask = 0x80; ddc_i2c->y_data_mask = 0x80;
ddc_i2c->mask_clk_reg = RADEON_GPIOPAD_MASK; ddc_i2c->mask_clk_reg = RADEON_GPIOPAD_MASK;
ddc_i2c->mask_data_reg = RADEON_GPIOPAD_MASK; ddc_i2c->mask_data_reg = RADEON_GPIOPAD_MASK;
ddc_i2c->a_clk_reg = RADEON_GPIOPAD_A; ddc_i2c->a_clk_reg = RADEON_GPIOPAD_A;
ddc_i2c->a_data_reg = RADEON_GPIOPAD_A; ddc_i2c->a_data_reg = RADEON_GPIOPAD_A;
ddc_i2c->put_clk_reg = RADEON_GPIOPAD_EN; ddc_i2c->en_clk_reg = RADEON_GPIOPAD_EN;
ddc_i2c->put_data_reg = RADEON_GPIOPAD_EN; ddc_i2c->en_data_reg = RADEON_GPIOPAD_EN;
ddc_i2c->get_clk_reg = RADEON_LCD_GPIO_Y_REG; ddc_i2c->y_clk_reg = RADEON_LCD_GPIO_Y_REG;
ddc_i2c->get_data_reg = RADEON_LCD_GPIO_Y_REG; ddc_i2c->y_data_reg = RADEON_LCD_GPIO_Y_REG;
} }
/* Certain IBM chipset RN50s have a BIOS reporting two VGAs, /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
...@@ -1939,13 +1939,13 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) ...@@ -1939,13 +1939,13 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
RBIOS32(lcd_ddc_info + 3); RBIOS32(lcd_ddc_info + 3);
ddc_i2c.a_data_mask = ddc_i2c.a_data_mask =
RBIOS32(lcd_ddc_info + 7); RBIOS32(lcd_ddc_info + 7);
ddc_i2c.put_clk_mask = ddc_i2c.en_clk_mask =
RBIOS32(lcd_ddc_info + 3); RBIOS32(lcd_ddc_info + 3);
ddc_i2c.put_data_mask = ddc_i2c.en_data_mask =
RBIOS32(lcd_ddc_info + 7); RBIOS32(lcd_ddc_info + 7);
ddc_i2c.get_clk_mask = ddc_i2c.y_clk_mask =
RBIOS32(lcd_ddc_info + 3); RBIOS32(lcd_ddc_info + 3);
ddc_i2c.get_data_mask = ddc_i2c.y_data_mask =
RBIOS32(lcd_ddc_info + 7); RBIOS32(lcd_ddc_info + 7);
break; break;
case DDC_GPIO: case DDC_GPIO:
...@@ -1960,13 +1960,13 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) ...@@ -1960,13 +1960,13 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
RBIOS32(lcd_ddc_info + 3); RBIOS32(lcd_ddc_info + 3);
ddc_i2c.a_data_mask = ddc_i2c.a_data_mask =
RBIOS32(lcd_ddc_info + 7); RBIOS32(lcd_ddc_info + 7);
ddc_i2c.put_clk_mask = ddc_i2c.en_clk_mask =
RBIOS32(lcd_ddc_info + 3); RBIOS32(lcd_ddc_info + 3);
ddc_i2c.put_data_mask = ddc_i2c.en_data_mask =
RBIOS32(lcd_ddc_info + 7); RBIOS32(lcd_ddc_info + 7);
ddc_i2c.get_clk_mask = ddc_i2c.y_clk_mask =
RBIOS32(lcd_ddc_info + 3); RBIOS32(lcd_ddc_info + 3);
ddc_i2c.get_data_mask = ddc_i2c.y_data_mask =
RBIOS32(lcd_ddc_info + 7); RBIOS32(lcd_ddc_info + 7);
break; break;
default: default:
......
drivers/gpu/drm/radeon/radeon_display.c
View file @ 9b9fe724
...@@ -270,10 +270,10 @@ static void radeon_print_display_setup(struct drm_device *dev) ...@@ -270,10 +270,10 @@ static void radeon_print_display_setup(struct drm_device *dev)
radeon_connector->ddc_bus->rec.mask_data_reg, radeon_connector->ddc_bus->rec.mask_data_reg,
radeon_connector->ddc_bus->rec.a_clk_reg, radeon_connector->ddc_bus->rec.a_clk_reg,
radeon_connector->ddc_bus->rec.a_data_reg, radeon_connector->ddc_bus->rec.a_data_reg,
radeon_connector->ddc_bus->rec.put_clk_reg, radeon_connector->ddc_bus->rec.en_clk_reg,
radeon_connector->ddc_bus->rec.put_data_reg, radeon_connector->ddc_bus->rec.en_data_reg,
radeon_connector->ddc_bus->rec.get_clk_reg, radeon_connector->ddc_bus->rec.y_clk_reg,
radeon_connector->ddc_bus->rec.get_data_reg); radeon_connector->ddc_bus->rec.y_data_reg);
DRM_INFO(" Encoders:\n"); DRM_INFO(" Encoders:\n");
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
radeon_encoder = to_radeon_encoder(encoder); radeon_encoder = to_radeon_encoder(encoder);
......
drivers/gpu/drm/radeon/radeon_i2c.c
View file @ 9b9fe724
...@@ -78,16 +78,16 @@ void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state) ...@@ -78,16 +78,16 @@ void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
} }
} }
if (lock_state) {
temp = RREG32(rec->a_clk_reg); /* clear the output pin values */
temp &= ~(rec->a_clk_mask); temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
WREG32(rec->a_clk_reg, temp); WREG32(rec->a_clk_reg, temp);
temp = RREG32(rec->a_data_reg); temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
temp &= ~(rec->a_data_mask);
WREG32(rec->a_data_reg, temp); WREG32(rec->a_data_reg, temp);
}
/* mask the gpio pins for software use */
temp = RREG32(rec->mask_clk_reg); temp = RREG32(rec->mask_clk_reg);
if (lock_state) if (lock_state)
temp |= rec->mask_clk_mask; temp |= rec->mask_clk_mask;
...@@ -112,8 +112,9 @@ static int get_clock(void *i2c_priv) ...@@ -112,8 +112,9 @@ static int get_clock(void *i2c_priv)
struct radeon_i2c_bus_rec *rec = &i2c->rec; struct radeon_i2c_bus_rec *rec = &i2c->rec;
uint32_t val; uint32_t val;
val = RREG32(rec->get_clk_reg); /* read the value off the pin */
val &= rec->get_clk_mask; val = RREG32(rec->y_clk_reg);
val &= rec->y_clk_mask;
return (val != 0); return (val != 0);
} }
...@@ -126,8 +127,10 @@ static int get_data(void *i2c_priv) ...@@ -126,8 +127,10 @@ static int get_data(void *i2c_priv)
struct radeon_i2c_bus_rec *rec = &i2c->rec; struct radeon_i2c_bus_rec *rec = &i2c->rec;
uint32_t val; uint32_t val;
val = RREG32(rec->get_data_reg); /* read the value off the pin */
val &= rec->get_data_mask; val = RREG32(rec->y_data_reg);
val &= rec->y_data_mask;
return (val != 0); return (val != 0);
} }
...@@ -138,9 +141,10 @@ static void set_clock(void *i2c_priv, int clock) ...@@ -138,9 +141,10 @@ static void set_clock(void *i2c_priv, int clock)
struct radeon_i2c_bus_rec *rec = &i2c->rec; struct radeon_i2c_bus_rec *rec = &i2c->rec;
uint32_t val; uint32_t val;
val = RREG32(rec->put_clk_reg) & (uint32_t)~(rec->put_clk_mask); /* set pin direction */
val |= clock ? 0 : rec->put_clk_mask; val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
WREG32(rec->put_clk_reg, val); val |= clock ? 0 : rec->en_clk_mask;
WREG32(rec->en_clk_reg, val);
} }
static void set_data(void *i2c_priv, int data) static void set_data(void *i2c_priv, int data)
...@@ -150,9 +154,10 @@ static void set_data(void *i2c_priv, int data) ...@@ -150,9 +154,10 @@ static void set_data(void *i2c_priv, int data)
struct radeon_i2c_bus_rec *rec = &i2c->rec; struct radeon_i2c_bus_rec *rec = &i2c->rec;
uint32_t val; uint32_t val;
val = RREG32(rec->put_data_reg) & (uint32_t)~(rec->put_data_mask); /* set pin direction */
val |= data ? 0 : rec->put_data_mask; val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
WREG32(rec->put_data_reg, val); val |= data ? 0 : rec->en_data_mask;
WREG32(rec->en_data_reg, val);
} }
struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
......
drivers/gpu/drm/radeon/radeon_mode.h
View file @ 9b9fe724
...@@ -89,24 +89,38 @@ enum radeon_tv_std { ...@@ -89,24 +89,38 @@ enum radeon_tv_std {
TV_STD_PAL_CN, TV_STD_PAL_CN,
}; };
/* radeon gpio-based i2c
* 1. "mask" reg and bits
* grabs the gpio pins for software use
* 0=not held 1=held
* 2. "a" reg and bits
* output pin value
* 0=low 1=high
* 3. "en" reg and bits
* sets the pin direction
* 0=input 1=output
* 4. "y" reg and bits
* input pin value
* 0=low 1=high
*/
struct radeon_i2c_bus_rec { struct radeon_i2c_bus_rec {
bool valid; bool valid;
uint32_t mask_clk_reg; uint32_t mask_clk_reg;
uint32_t mask_data_reg; uint32_t mask_data_reg;
uint32_t a_clk_reg; uint32_t a_clk_reg;
uint32_t a_data_reg; uint32_t a_data_reg;
uint32_t put_clk_reg; uint32_t en_clk_reg;
uint32_t put_data_reg; uint32_t en_data_reg;
uint32_t get_clk_reg; uint32_t y_clk_reg;
uint32_t get_data_reg; uint32_t y_data_reg;
uint32_t mask_clk_mask; uint32_t mask_clk_mask;
uint32_t mask_data_mask; uint32_t mask_data_mask;
uint32_t put_clk_mask;
uint32_t put_data_mask;
uint32_t get_clk_mask;
uint32_t get_data_mask;
uint32_t a_clk_mask; uint32_t a_clk_mask;
uint32_t a_data_mask; uint32_t a_data_mask;
uint32_t en_clk_mask;
uint32_t en_data_mask;
uint32_t y_clk_mask;
uint32_t y_data_mask;
}; };
struct radeon_tmds_pll { struct radeon_tmds_pll {
......
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