Commit 9c54ea95 authored by Krzysztof Halasa's avatar Krzysztof Halasa Committed by Linus Torvalds

Subject: [PATCH] Intel FB pixel clock calculation fix

Intel framebuffer mis-calculated pixel clocks.

The pixel clock (and thus both H and V sync) will be slower than requested, so
if you set the minimum allowed the display may not sync.  In case of really
old CRT display it could theoretically damage it.

I'm using it with PAL TV (using RGB input - SCART connector) and the bug
prevented it from working at all (TV requirements are more strict and made the
bug visible).
Signed-off-by: default avatarKrzysztof Halasa <khc@pm.waw.pl>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent ba0268a8
...@@ -924,10 +924,10 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *re ...@@ -924,10 +924,10 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *re
if (m > pll->max_m) if (m > pll->max_m)
m = pll->max_m - 1; m = pll->max_m - 1;
for (testm = m - 1; testm <= m; testm++) { for (testm = m - 1; testm <= m; testm++) {
f_out = calc_vclock3(index, m, n, p); f_out = calc_vclock3(index, testm, n, p);
if (splitm(index, testm, &m1, &m2)) { if (splitm(index, testm, &m1, &m2)) {
WRN_MSG("cannot split m = %d\n", m); WRN_MSG("cannot split m = %d\n",
n++; testm);
continue; continue;
} }
if (clock > f_out) if (clock > f_out)
......
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