Commit 9c8e09b7 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter

drm/i915: Set PIPECONF color range bit on Valleyview

VLV has the color range selection bit in the PIPECONF register.
Configure it appropriately.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
[danvet: fixup rebase issues due to slightly different baseline.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 84b046f3
...@@ -4583,6 +4583,13 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) ...@@ -4583,6 +4583,13 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
else else
pipeconf |= PIPECONF_PROGRESSIVE; pipeconf |= PIPECONF_PROGRESSIVE;
if (IS_VALLEYVIEW(dev)) {
if (intel_crtc->config.limited_color_range)
pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
else
pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
}
I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
POSTING_READ(PIPECONF(intel_crtc->pipe)); POSTING_READ(PIPECONF(intel_crtc->pipe));
} }
......
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