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Commit 9cd70164 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'imx-dt-3.18' of... 

Merge tag 'imx-dt-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

Merge "ARM: imx: device tree changes for 3.18" from Shawn Guo:

The i.MX device tree changes for 3.18:
 - Device tree support for i.MX ADS and Armadeus APF9328 boards
 - Enable thermal sensor support for i.MX6SL
 - Add LCD support for i.MX6SL EVK board
 - Fix display duplicate name for a bunch of board dts files
 - Configure imx6qdl-sabresd board pins locally to remove the dependency
   on bootloader
 - A set of imx28-tx28 board dts updates from Lothar
 - Add pci config space as platform resource
 - Enable devices RTC, I2C and HDMI for nitrogen6x board
 - Split HummingBoard DT to support s/dl and d/q
 - mSATA and IR input support for HummingBoard
 - Add SSI baud clock for i.MX6 device trees
 - Add USB support for vf610-colibri and vf610-twr boards
 - A set of cleanup and updates on Gateworks boards

* tag 'imx-dt-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (86 commits)
  ARM: dts: imx6: make gpt per clock can be from OSC
  ARM: dts: imx: ventana: add canbus support for GW52xx
  ARM: dts: imx: ventana: cleanup pinctrl groups
  ARM: dts: imx: ventana: configure padconf for all pins
  ARM: dts: imx: ventana: use gpio constants
  ARM: dts: imx: ventana: remove unused aliases
  ARM: dts: imx: ventana: remove unsupported dt nodes
  ARM: dts: imx28-tx28: add alias for CAN XCVR regulator
  ARM: dts: imx28-tx28: add spi-gpio as alternative for spi-mxs
  ARM: dts: imx28-tx28: use GPIO flags
  ARM: dts: imx28-tx28: remove spidev labels and add third instance of spidev
  ARM: dts: imx6sl: add baud clock and clock-names for ssi
  ARM: dts: imx6qdl: add baud clock and clock-names for ssi
  ARM: dts: imx6qdl-sabresd: Configure the pins locally
  ARM: dts: imx28-m28evk: Fix display duplicate name warning
  ARM: dts: imx28-tx28: Fix display duplicate name warning
  ARM: dts: imx28-m28cu: Fix display duplicate name warning
  ARM: dts: imx28-cfa100: Fix display duplicate name warning
  ARM: dts: imx28-apf28dev: Fix display duplicate name warning
  ARM: dts: imx28-apx4devkit: Fix display duplicate name warning
  ...
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 7e9b2828 2b2244a3
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Documentation/devicetree/bindings/i2c/trivial-devices.txt
View file @ 9cd70164
...@@ -44,7 +44,7 @@ dallas,ds1775 Tiny Digital Thermometer and Thermostat ...@@ -44,7 +44,7 @@ dallas,ds1775 Tiny Digital Thermometer and Thermostat
dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM
dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O
dallas,ds75 Digital Thermometer and Thermostat dallas,ds75 Digital Thermometer and Thermostat
dialog,da9053 DA9053: flexible system level PMIC with multicore support dlg,da9053 DA9053: flexible system level PMIC with multicore support
epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE
epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE
fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer
......
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
View file @ 9cd70164
...@@ -17,7 +17,9 @@ Example: ...@@ -17,7 +17,9 @@ Example:
pcie@0x01000000 { pcie@0x01000000 {
compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
reg = <0x01ffc000 0x4000>; reg = <0x01ffc000 0x04000>,
<0x01f00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
device_type = "pci"; device_type = "pci";
......
Documentation/devicetree/bindings/regulator/da9210.txt
View file @ 9cd70164
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
Required properties: Required properties:
- compatible: must be "diasemi,da9210" - compatible: must be "dlg,da9210"
- reg: the i2c slave address of the regulator. It should be 0x68. - reg: the i2c slave address of the regulator. It should be 0x68.
Any standard regulator properties can be used to configure the single da9210 Any standard regulator properties can be used to configure the single da9210
...@@ -11,7 +11,7 @@ DCDC. ...@@ -11,7 +11,7 @@ DCDC.
Example: Example:
da9210@68 { da9210@68 {
compatible = "diasemi,da9210"; compatible = "dlg,da9210";
reg = <0x68>; reg = <0x68>;
regulator-min-microvolt = <900000>; regulator-min-microvolt = <900000>;
......
Documentation/devicetree/bindings/vendor-prefixes.txt
View file @ 9cd70164
...@@ -38,6 +38,7 @@ dallas Maxim Integrated Products (formerly Dallas Semiconductor) ...@@ -38,6 +38,7 @@ dallas Maxim Integrated Products (formerly Dallas Semiconductor)
davicom DAVICOM Semiconductor, Inc. davicom DAVICOM Semiconductor, Inc.
denx Denx Software Engineering denx Denx Software Engineering
digi Digi International Inc. digi Digi International Inc.
dlg Dialog Semiconductor
dlink D-Link Corporation dlink D-Link Corporation
dmo Data Modul AG dmo Data Modul AG
ebv EBV Elektronik ebv EBV Elektronik
......
arch/arm/boot/dts/Makefile
View file @ 9cd70164
...@@ -161,6 +161,8 @@ dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb ...@@ -161,6 +161,8 @@ dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
dtb-$(CONFIG_ARCH_MXC) += \ dtb-$(CONFIG_ARCH_MXC) += \
imx1-ads.dtb \
imx1-apf9328.dtb \
imx25-eukrea-mbimxsd25-baseboard.dtb \ imx25-eukrea-mbimxsd25-baseboard.dtb \
imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \
imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \
...@@ -199,6 +201,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ ...@@ -199,6 +201,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6dl-gw52xx.dtb \ imx6dl-gw52xx.dtb \
imx6dl-gw53xx.dtb \ imx6dl-gw53xx.dtb \
imx6dl-gw54xx.dtb \ imx6dl-gw54xx.dtb \
imx6dl-gw552x.dtb \
imx6dl-hummingboard.dtb \ imx6dl-hummingboard.dtb \
imx6dl-nitrogen6x.dtb \ imx6dl-nitrogen6x.dtb \
imx6dl-phytec-pbab01.dtb \ imx6dl-phytec-pbab01.dtb \
...@@ -223,6 +226,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ ...@@ -223,6 +226,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6q-gw53xx.dtb \ imx6q-gw53xx.dtb \
imx6q-gw5400-a.dtb \ imx6q-gw5400-a.dtb \
imx6q-gw54xx.dtb \ imx6q-gw54xx.dtb \
imx6q-gw552x.dtb \
imx6q-hummingboard.dtb \
imx6q-nitrogen6x.dtb \ imx6q-nitrogen6x.dtb \
imx6q-phytec-pbab01.dtb \ imx6q-phytec-pbab01.dtb \
imx6q-rex-pro.dtb \ imx6q-rex-pro.dtb \
...@@ -240,7 +245,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ ...@@ -240,7 +245,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6q-tx6q-1110.dtb \ imx6q-tx6q-1110.dtb \
imx6sl-evk.dtb \ imx6sl-evk.dtb \
imx6sx-sdb.dtb \ imx6sx-sdb.dtb \
vf610-colibri.dtb \ vf610-colibri-eval-v3.dtb \
vf610-cosmic.dtb \ vf610-cosmic.dtb \
vf610-twr.dtb vf610-twr.dtb
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
......
arch/arm/boot/dts/imx1-ads.dts 0 → 100644
View file @ 9cd70164
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx1.dtsi"
/ {
model = "Freescale MX1 ADS";
compatible = "fsl,imx1ads", "fsl,imx1";
chosen {
stdout-path = &uart1;
};
memory {
reg = <0x08000000 0x04000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
clk32 {
compatible = "fsl,imx-clk32", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
};
};
};
&cspi1 {
pinctrl-0 = <&pinctrl_cspi1>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
status = "okay";
};
&i2c {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c>;
status = "okay";
extgpio0: pcf8575@22 {
compatible = "nxp,pcf8575";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
extgpio1: pcf8575@24 {
compatible = "nxp,pcf8575";
reg = <0x24>;
gpio-controller;
#gpio-cells = <2>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
fsl,uart-has-rtscts;
status = "okay";
};
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim>;
status = "okay";
nor: nor@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x02000000>;
bank-width = <4>;
fsl,weim-cs-timing = <0x00003e00 0x00000801>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&iomuxc {
imx1-ads {
pinctrl_cspi1: cspi1grp {
fsl,pins = <
MX1_PAD_SPI1_MISO__SPI1_MISO 0x0
MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0
MX1_PAD_SPI1_RDY__SPI1_RDY 0x0
MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0
MX1_PAD_SPI1_SS__GPIO3_15 0x0
>;
};
pinctrl_i2c: i2cgrp {
fsl,pins = <
MX1_PAD_I2C_SCL__I2C_SCL 0x0
MX1_PAD_I2C_SDA__I2C_SDA 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX1_PAD_UART1_TXD__UART1_TXD 0x0
MX1_PAD_UART1_RXD__UART1_RXD 0x0
MX1_PAD_UART1_CTS__UART1_CTS 0x0
MX1_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX1_PAD_UART2_TXD__UART2_TXD 0x0
MX1_PAD_UART2_RXD__UART2_RXD 0x0
MX1_PAD_UART2_CTS__UART2_CTS 0x0
MX1_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_weim: weimgrp {
fsl,pins = <
MX1_PAD_A0__A0 0x0
MX1_PAD_A16__A16 0x0
MX1_PAD_A17__A17 0x0
MX1_PAD_A18__A18 0x0
MX1_PAD_A19__A19 0x0
MX1_PAD_A20__A20 0x0
MX1_PAD_A21__A21 0x0
MX1_PAD_A22__A22 0x0
MX1_PAD_A23__A23 0x0
MX1_PAD_A24__A24 0x0
MX1_PAD_BCLK__BCLK 0x0
MX1_PAD_CS4__CS4 0x0
MX1_PAD_DTACK__DTACK 0x0
MX1_PAD_ECB__ECB 0x0
MX1_PAD_LBA__LBA 0x0
>;
};
};
};
arch/arm/boot/dts/imx1-apf9328.dts 0 → 100644
View file @ 9cd70164
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx1.dtsi"
/ {
model = "Armadeus APF9328";
compatible = "armadeus,imx1-apf9328", "fsl,imx1";
chosen {
stdout-path = &uart1;
};
memory {
reg = <0x08000000 0x00800000>;
};
};
&i2c {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
fsl,uart-has-rtscts;
status = "okay";
};
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim>;
status = "okay";
nor: nor@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x02000000>;
bank-width = <2>;
fsl,weim-cs-timing = <0x00330e04 0x00000d01>;
#address-cells = <1>;
#size-cells = <1>;
};
eth: eth@4,c00000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eth>;
compatible = "davicom,dm9000";
reg = <
4 0x00c00000 0x2
4 0x00c00002 0x2
>;
interrupt-parent = <&gpio2>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
fsl,weim-cs-timing = <0x0000c700 0x19190d01>;
};
};
&iomuxc {
imx1-apf9328 {
pinctrl_eth: ethgrp {
fsl,pins = <
MX1_PAD_SIM_SVEN__GPIO2_14 0x0
>;
};
pinctrl_i2c: i2cgrp {
fsl,pins = <
MX1_PAD_I2C_SCL__I2C_SCL 0x0
MX1_PAD_I2C_SDA__I2C_SDA 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX1_PAD_UART1_TXD__UART1_TXD 0x0
MX1_PAD_UART1_RXD__UART1_RXD 0x0
MX1_PAD_UART1_CTS__UART1_CTS 0x0
MX1_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX1_PAD_UART2_TXD__UART2_TXD 0x0
MX1_PAD_UART2_RXD__UART2_RXD 0x0
MX1_PAD_UART2_CTS__UART2_CTS 0x0
MX1_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_weim: weimgrp {
fsl,pins = <
MX1_PAD_A0__A0 0x0
MX1_PAD_A16__A16 0x0
MX1_PAD_A17__A17 0x0
MX1_PAD_A18__A18 0x0
MX1_PAD_A19__A19 0x0
MX1_PAD_A20__A20 0x0
MX1_PAD_A21__A21 0x0
MX1_PAD_A22__A22 0x0
MX1_PAD_A23__A23 0x0
MX1_PAD_A24__A24 0x0
MX1_PAD_BCLK__BCLK 0x0
MX1_PAD_CS4__CS4 0x0
MX1_PAD_DTACK__DTACK 0x0
MX1_PAD_ECB__ECB 0x0
MX1_PAD_LBA__LBA 0x0
>;
};
};
};
arch/arm/boot/dts/imx1-pinfunc.h 0 → 100644
View file @ 9cd70164
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DTS_IMX1_PINFUNC_H
#define __DTS_IMX1_PINFUNC_H
/*
* The pin function ID is a tuple of
* <pin mux_id>
* mux_id consists of
* function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
*
* function: 0 - Primary function
* 1 - Alternate function
* 2 - GPIO
* direction: 0 - Input
* 1 - Output
* gpio_oconf: 0 - A_IN
* 1 - B_IN
* 2 - A_OUT
* 3 - Data Register
* gpio_iconfa/b: 0 - GPIO_IN
* 1 - Interrupt Status Register
* 2 - 0
* 3 - 1
*
* 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable
* configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
* number on the specific port (between 0 and 31).
*/
#define MX1_PAD_A24__A24 0x00 0x004
#define MX1_PAD_A24__GPIO1_0 0x00 0x032
#define MX1_PAD_A24__SPI2_CLK 0x00 0x006
#define MX1_PAD_TIN__TIN 0x01 0x000
#define MX1_PAD_TIN__GPIO1_1 0x01 0x032
#define MX1_PAD_TIN__SPI2_RXD 0x01 0x022
#define MX1_PAD_PWMO__PWMO 0x02 0x004
#define MX1_PAD_PWMO__GPIO1_2 0x02 0x032
#define MX1_PAD_CSI_MCLK__CSI_MCLK 0x03 0x004
#define MX1_PAD_CSI_MCLK__GPIO1_3 0x03 0x032
#define MX1_PAD_CSI_D0__CSI_D0 0x04 0x000
#define MX1_PAD_CSI_D0__GPIO1_4 0x04 0x032
#define MX1_PAD_CSI_D1__CSI_D1 0x05 0x000
#define MX1_PAD_CSI_D1__GPIO1_5 0x05 0x032
#define MX1_PAD_CSI_D2__CSI_D2 0x06 0x000
#define MX1_PAD_CSI_D2__GPIO1_6 0x06 0x032
#define MX1_PAD_CSI_D3__CSI_D3 0x07 0x000
#define MX1_PAD_CSI_D3__GPIO1_7 0x07 0x032
#define MX1_PAD_CSI_D4__CSI_D4 0x08 0x000
#define MX1_PAD_CSI_D4__GPIO1_8 0x08 0x032
#define MX1_PAD_CSI_D5__CSI_D5 0x09 0x000
#define MX1_PAD_CSI_D5__GPIO1_9 0x09 0x032
#define MX1_PAD_CSI_D6__CSI_D6 0x0a 0x000
#define MX1_PAD_CSI_D6__GPIO1_10 0x0a 0x032
#define MX1_PAD_CSI_D7__CSI_D7 0x0b 0x000
#define MX1_PAD_CSI_D7__GPIO1_11 0x0b 0x032
#define MX1_PAD_CSI_VSYNC__CSI_VSYNC 0x0c 0x000
#define MX1_PAD_CSI_VSYNC__GPIO1_12 0x0c 0x032
#define MX1_PAD_CSI_HSYNC__CSI_HSYNC 0x0d 0x000
#define MX1_PAD_CSI_HSYNC__GPIO1_13 0x0d 0x032
#define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK 0x0e 0x000
#define MX1_PAD_CSI_PIXCLK__GPIO1_14 0x0e 0x032
#define MX1_PAD_I2C_SDA__I2C_SDA 0x0f 0x000
#define MX1_PAD_I2C_SDA__GPIO1_15 0x0f 0x032
#define MX1_PAD_I2C_SCL__I2C_SCL 0x10 0x004
#define MX1_PAD_I2C_SCL__GPIO1_16 0x10 0x032
#define MX1_PAD_DTACK__DTACK 0x11 0x000
#define MX1_PAD_DTACK__GPIO1_17 0x11 0x032
#define MX1_PAD_DTACK__SPI2_SS 0x11 0x002
#define MX1_PAD_DTACK__A25 0x11 0x016
#define MX1_PAD_BCLK__BCLK 0x12 0x004
#define MX1_PAD_BCLK__GPIO1_18 0x12 0x032
#define MX1_PAD_LBA__LBA 0x13 0x004
#define MX1_PAD_LBA__GPIO1_19 0x13 0x032
#define MX1_PAD_ECB__ECB 0x14 0x000
#define MX1_PAD_ECB__GPIO1_20 0x14 0x032
#define MX1_PAD_A0__A0 0x15 0x004
#define MX1_PAD_A0__GPIO1_21 0x15 0x032
#define MX1_PAD_CS4__CS4 0x16 0x004
#define MX1_PAD_CS4__GPIO1_22 0x16 0x032
#define MX1_PAD_CS5__CS5 0x17 0x004
#define MX1_PAD_CS5__GPIO1_23 0x17 0x032
#define MX1_PAD_A16__A16 0x18 0x004
#define MX1_PAD_A16__GPIO1_24 0x18 0x032
#define MX1_PAD_A17__A17 0x19 0x004
#define MX1_PAD_A17__GPIO1_25 0x19 0x032
#define MX1_PAD_A18__A18 0x1a 0x004
#define MX1_PAD_A18__GPIO1_26 0x1a 0x032
#define MX1_PAD_A19__A19 0x1b 0x004
#define MX1_PAD_A19__GPIO1_27 0x1b 0x032
#define MX1_PAD_A20__A20 0x1c 0x004
#define MX1_PAD_A20__GPIO1_28 0x1c 0x032
#define MX1_PAD_A21__A21 0x1d 0x004
#define MX1_PAD_A21__GPIO1_29 0x1d 0x032
#define MX1_PAD_A22__A22 0x1e 0x004
#define MX1_PAD_A22__GPIO1_30 0x1e 0x032
#define MX1_PAD_A23__A23 0x1f 0x004
#define MX1_PAD_A23__GPIO1_31 0x1f 0x032
#define MX1_PAD_SD_DAT0__SD_DAT0 0x28 0x000
#define MX1_PAD_SD_DAT0__MS_PI0 0x28 0x001
#define MX1_PAD_SD_DAT0__GPIO2_8 0x28 0x032
#define MX1_PAD_SD_DAT1__SD_DAT1 0x29 0x000
#define MX1_PAD_SD_DAT1__MS_PI1 0x29 0x001
#define MX1_PAD_SD_DAT1__GPIO2_9 0x29 0x032
#define MX1_PAD_SD_DAT2__SD_DAT2 0x2a 0x000
#define MX1_PAD_SD_DAT2__MS_SCLKI 0x2a 0x001
#define MX1_PAD_SD_DAT2__GPIO2_10 0x2a 0x032
#define MX1_PAD_SD_DAT3__SD_DAT3 0x2b 0x000
#define MX1_PAD_SD_DAT3__MS_SDIO 0x2b 0x001
#define MX1_PAD_SD_DAT3__GPIO2_11 0x2b 0x032
#define MX1_PAD_SD_SCLK__SD_SCLK 0x2c 0x004
#define MX1_PAD_SD_SCLK__MS_SCLKO 0x2c 0x005
#define MX1_PAD_SD_SCLK__GPIO2_12 0x2c 0x032
#define MX1_PAD_SD_CMD__SD_CMD 0x2d 0x000
#define MX1_PAD_SD_CMD__MS_BS 0x2d 0x005
#define MX1_PAD_SD_CMD__GPIO2_13 0x2d 0x032
#define MX1_PAD_SIM_SVEN__SIM_SVEN 0x2e 0x004
#define MX1_PAD_SIM_SVEN__SSI_RXFS 0x2e 0x001
#define MX1_PAD_SIM_SVEN__GPIO2_14 0x2e 0x032
#define MX1_PAD_SIM_PD__SIM_PD 0x2f 0x000
#define MX1_PAD_SIM_PD__SSI_RXCLK 0x2f 0x001
#define MX1_PAD_SIM_PD__GPIO2_15 0x2f 0x032
#define MX1_PAD_SIM_TX__SIM_TX 0x30 0x000
#define MX1_PAD_SIM_TX__SSI_RXDAT 0x30 0x001
#define MX1_PAD_SIM_TX__GPIO2_16 0x30 0x032
#define MX1_PAD_SIM_RX__SIM_RX 0x31 0x000
#define MX1_PAD_SIM_RX__SSI_TXDAT 0x31 0x005
#define MX1_PAD_SIM_RX__GPIO2_17 0x31 0x032
#define MX1_PAD_SIM_RST__SIM_RST 0x32 0x004
#define MX1_PAD_SIM_RST__SSI_TXFS 0x32 0x001
#define MX1_PAD_SIM_RST__GPIO2_18 0x32 0x032
#define MX1_PAD_SIM_CLK__SIM_CLK 0x33 0x004
#define MX1_PAD_SIM_CLK__SSI_TXCLK 0x33 0x001
#define MX1_PAD_SIM_CLK__GPIO2_19 0x33 0x032
#define MX1_PAD_USBD_AFE__USBD_AFE 0x34 0x004
#define MX1_PAD_USBD_AFE__GPIO2_20 0x34 0x032
#define MX1_PAD_USBD_OE__USBD_OE 0x35 0x004
#define MX1_PAD_USBD_OE__GPIO2_21 0x35 0x032
#define MX1_PAD_USBD_RCV__USBD_RCV 0x36 0x000
#define MX1_PAD_USBD_RCV__GPIO2_22 0x36 0x032
#define MX1_PAD_USBD_SUSPND__USBD_SUSPND 0x37 0x004
#define MX1_PAD_USBD_SUSPND__GPIO2_23 0x37 0x032
#define MX1_PAD_USBD_VP__USBD_VP 0x38 0x000
#define MX1_PAD_USBD_VP__GPIO2_24 0x38 0x032
#define MX1_PAD_USBD_VM__USBD_VM 0x39 0x000
#define MX1_PAD_USBD_VM__GPIO2_25 0x39 0x032
#define MX1_PAD_USBD_VPO__USBD_VPO 0x3a 0x004
#define MX1_PAD_USBD_VPO__GPIO2_26 0x3a 0x032
#define MX1_PAD_USBD_VMO__USBD_VMO 0x3b 0x004
#define MX1_PAD_USBD_VMO__GPIO2_27 0x3b 0x032
#define MX1_PAD_UART2_CTS__UART2_CTS 0x3c 0x004
#define MX1_PAD_UART2_CTS__GPIO2_28 0x3c 0x032
#define MX1_PAD_UART2_RTS__UART2_RTS 0x3d 0x000
#define MX1_PAD_UART2_RTS__GPIO2_29 0x3d 0x032
#define MX1_PAD_UART2_TXD__UART2_TXD 0x3e 0x004
#define MX1_PAD_UART2_TXD__GPIO2_30 0x3e 0x032
#define MX1_PAD_UART2_RXD__UART2_RXD 0x3f 0x000
#define MX1_PAD_UART2_RXD__GPIO2_31 0x3f 0x032
#define MX1_PAD_SSI_RXFS__SSI_RXFS 0x43 0x000
#define MX1_PAD_SSI_RXFS__GPIO3_3 0x43 0x032
#define MX1_PAD_SSI_RXCLK__SSI_RXCLK 0x44 0x000
#define MX1_PAD_SSI_RXCLK__GPIO3_4 0x44 0x032
#define MX1_PAD_SSI_RXDAT__SSI_RXDAT 0x45 0x000
#define MX1_PAD_SSI_RXDAT__GPIO3_5 0x45 0x032
#define MX1_PAD_SSI_TXDAT__SSI_TXDAT 0x46 0x004
#define MX1_PAD_SSI_TXDAT__GPIO3_6 0x46 0x032
#define MX1_PAD_SSI_TXFS__SSI_TXFS 0x47 0x000
#define MX1_PAD_SSI_TXFS__GPIO3_7 0x47 0x032
#define MX1_PAD_SSI_TXCLK__SSI_TXCLK 0x48 0x000
#define MX1_PAD_SSI_TXCLK__GPIO3_8 0x48 0x032
#define MX1_PAD_UART1_CTS__UART1_CTS 0x49 0x004
#define MX1_PAD_UART1_CTS__GPIO3_9 0x49 0x032
#define MX1_PAD_UART1_RTS__UART1_RTS 0x4a 0x000
#define MX1_PAD_UART1_RTS__GPIO3_10 0x4a 0x032
#define MX1_PAD_UART1_TXD__UART1_TXD 0x4b 0x004
#define MX1_PAD_UART1_TXD__GPIO3_11 0x4b 0x032
#define MX1_PAD_UART1_RXD__UART1_RXD 0x4c 0x000
#define MX1_PAD_UART1_RXD__GPIO3_12 0x4c 0x032
#define MX1_PAD_SPI1_RDY__SPI1_RDY 0x4d 0x000
#define MX1_PAD_SPI1_RDY__GPIO3_13 0x4d 0x032
#define MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x4e 0x004
#define MX1_PAD_SPI1_SCLK__GPIO3_14 0x4e 0x032
#define MX1_PAD_SPI1_SS__SPI1_SS 0x4f 0x000
#define MX1_PAD_SPI1_SS__GPIO3_15 0x4f 0x032
#define MX1_PAD_SPI1_MISO__SPI1_MISO 0x50 0x000
#define MX1_PAD_SPI1_MISO__GPIO3_16 0x50 0x032
#define MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x51 0x004
#define MX1_PAD_SPI1_MOSI__GPIO3_17 0x51 0x032
#define MX1_PAD_BT13__BT13 0x53 0x004
#define MX1_PAD_BT13__SSI2_RXCLK 0x53 0x001
#define MX1_PAD_BT13__GPIO3_19 0x53 0x032
#define MX1_PAD_BT12__BT12 0x54 0x004
#define MX1_PAD_BT12__SSI2_TXFS 0x54 0x001
#define MX1_PAD_BT12__GPIO3_20 0x54 0x032
#define MX1_PAD_BT11__BT11 0x55 0x004
#define MX1_PAD_BT11__SSI2_TXCLK 0x55 0x001
#define MX1_PAD_BT11__GPIO3_21 0x55 0x032
#define MX1_PAD_BT10__BT10 0x56 0x004
#define MX1_PAD_BT10__SSI2_TX 0x56 0x001
#define MX1_PAD_BT10__GPIO3_22 0x56 0x032
#define MX1_PAD_BT9__BT9 0x57 0x004
#define MX1_PAD_BT9__SSI2_RX 0x57 0x001
#define MX1_PAD_BT9__GPIO3_23 0x57 0x032
#define MX1_PAD_BT8__BT8 0x58 0x004
#define MX1_PAD_BT8__SSI2_RXFS 0x58 0x001
#define MX1_PAD_BT8__GPIO3_24 0x58 0x032
#define MX1_PAD_BT8__UART3_RI 0x58 0x016
#define MX1_PAD_BT7__BT7 0x59 0x004
#define MX1_PAD_BT7__GPIO3_25 0x59 0x032
#define MX1_PAD_BT7__UART3_DSR 0x59 0x016
#define MX1_PAD_BT6__BT6 0x5a 0x004
#define MX1_PAD_BT6__GPIO3_26 0x5a 0x032
#define MX1_PAD_BT6__SPI2_SS3 0x5a 0x016
#define MX1_PAD_BT6__UART3_DTR 0x5a 0x022
#define MX1_PAD_BT5__BT5 0x5b 0x000
#define MX1_PAD_BT5__GPIO3_27 0x5b 0x032
#define MX1_PAD_BT5__UART3_DCD 0x5b 0x016
#define MX1_PAD_BT4__BT4 0x5c 0x000
#define MX1_PAD_BT4__GPIO3_28 0x5c 0x032
#define MX1_PAD_BT4__UART3_CTS 0x5c 0x016
#define MX1_PAD_BT3__BT3 0x5d 0x000
#define MX1_PAD_BT3__GPIO3_29 0x5d 0x032
#define MX1_PAD_BT3__UART3_RTS 0x5d 0x022
#define MX1_PAD_BT2__BT2 0x5e 0x004
#define MX1_PAD_BT2__GPIO3_30 0x5e 0x032
#define MX1_PAD_BT2__UART3_TX 0x5e 0x016
#define MX1_PAD_BT1__BT1 0x5f 0x000
#define MX1_PAD_BT1__GPIO3_31 0x5f 0x032
#define MX1_PAD_BT1__UART3_RX 0x5f 0x022
#define MX1_PAD_LSCLK__LSCLK 0x66 0x004
#define MX1_PAD_LSCLK__GPIO4_6 0x66 0x032
#define MX1_PAD_REV__REV 0x67 0x004
#define MX1_PAD_REV__UART2_DTR 0x67 0x001
#define MX1_PAD_REV__GPIO4_7 0x67 0x032
#define MX1_PAD_REV__SPI2_CLK 0x67 0x006
#define MX1_PAD_CLS__CLS 0x68 0x004
#define MX1_PAD_CLS__UART2_DCD 0x68 0x005
#define MX1_PAD_CLS__GPIO4_8 0x68 0x032
#define MX1_PAD_CLS__SPI2_SS 0x68 0x002
#define MX1_PAD_PS__PS 0x69 0x004
#define MX1_PAD_PS__UART2_RI 0x69 0x005
#define MX1_PAD_PS__GPIO4_9 0x69 0x032
#define MX1_PAD_PS__SPI2_RXD 0x69 0x022
#define MX1_PAD_SPL_SPR__SPL_SPR 0x6a 0x004
#define MX1_PAD_SPL_SPR__UART2_DSR 0x6a 0x005
#define MX1_PAD_SPL_SPR__GPIO4_10 0x6a 0x032
#define MX1_PAD_SPL_SPR__SPI2_TXD 0x6a 0x006
#define MX1_PAD_CONTRAST__CONTRAST 0x6b 0x004
#define MX1_PAD_CONTRAST__GPIO4_11 0x6b 0x032
#define MX1_PAD_CONTRAST__SPI2_SS2 0x6b 0x012
#define MX1_PAD_ACD_OE__ACD_OE 0x6c 0x004
#define MX1_PAD_ACD_OE__GPIO4_12 0x6c 0x032
#define MX1_PAD_LP_HSYNC__LP_HSYNC 0x6d 0x004
#define MX1_PAD_LP_HSYNC__GPIO4_13 0x6d 0x032
#define MX1_PAD_FLM_VSYNC__FLM_VSYNC 0x6e 0x004
#define MX1_PAD_FLM_VSYNC__GPIO4_14 0x6e 0x032
#define MX1_PAD_LD0__LD0 0x6f 0x004
#define MX1_PAD_LD0__GPIO4_15 0x6f 0x032
#define MX1_PAD_LD1__LD1 0x70 0x004
#define MX1_PAD_LD1__GPIO4_16 0x70 0x032
#define MX1_PAD_LD2__LD2 0x71 0x004
#define MX1_PAD_LD2__GPIO4_17 0x71 0x032
#define MX1_PAD_LD3__LD3 0x72 0x004
#define MX1_PAD_LD3__GPIO4_18 0x72 0x032
#define MX1_PAD_LD4__LD4 0x73 0x004
#define MX1_PAD_LD4__GPIO4_19 0x73 0x032
#define MX1_PAD_LD5__LD5 0x74 0x004
#define MX1_PAD_LD5__GPIO4_20 0x74 0x032
#define MX1_PAD_LD6__LD6 0x75 0x004
#define MX1_PAD_LD6__GPIO4_21 0x75 0x032
#define MX1_PAD_LD7__LD7 0x76 0x004
#define MX1_PAD_LD7__GPIO4_22 0x76 0x032
#define MX1_PAD_LD8__LD8 0x77 0x004
#define MX1_PAD_LD8__GPIO4_23 0x77 0x032
#define MX1_PAD_LD9__LD9 0x78 0x004
#define MX1_PAD_LD9__GPIO4_24 0x78 0x032
#define MX1_PAD_LD10__LD10 0x79 0x004
#define MX1_PAD_LD10__GPIO4_25 0x79 0x032
#define MX1_PAD_LD11__LD11 0x7a 0x004
#define MX1_PAD_LD11__GPIO4_26 0x7a 0x032
#define MX1_PAD_LD12__LD12 0x7b 0x004
#define MX1_PAD_LD12__GPIO4_27 0x7b 0x032
#define MX1_PAD_LD13__LD13 0x7c 0x004
#define MX1_PAD_LD13__GPIO4_28 0x7c 0x032
#define MX1_PAD_LD14__LD14 0x7d 0x004
#define MX1_PAD_LD14__GPIO4_29 0x7d 0x032
#define MX1_PAD_LD15__LD15 0x7e 0x004
#define MX1_PAD_LD15__GPIO4_30 0x7e 0x032
#define MX1_PAD_TMR2OUT__TMR2OUT 0x7f 0x000
#define MX1_PAD_TMR2OUT__GPIO4_31 0x7f 0x032
#define MX1_PAD_TMR2OUT__SPI2_TXD 0x7f 0x006
#endif
arch/arm/boot/dts/imx1.dtsi 0 → 100644
View file @ 9cd70164
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "skeleton.dtsi"
#include "imx1-pinfunc.h"
#include <dt-bindings/clock/imx1-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &i2c;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
spi0 = &cspi1;
spi1 = &cspi2;
};
aitc: aitc-interrupt-controller@00223000 {
compatible = "fsl,imx1-aitc", "fsl,avic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x00223000 0x1000>;
};
cpus {
#size-cells = <0>;
#address-cells = <1>;
cpu: cpu@0 {
device_type = "cpu";
compatible = "arm,arm920t";
operating-points = <200000 1900000>;
clock-latency = <62500>;
clocks = <&clks IMX1_CLK_MCU>;
voltage-tolerance = <5>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&aitc>;
ranges;
aipi@00200000 {
compatible = "fsl,aipi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00200000 0x10000>;
ranges;
gpt1: timer@00202000 {
compatible = "fsl,imx1-gpt";
reg = <0x00202000 0x1000>;
interrupts = <59>;
clocks = <&clks IMX1_CLK_HCLK>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
};
gpt2: timer@00203000 {
compatible = "fsl,imx1-gpt";
reg = <0x00203000 0x1000>;
interrupts = <58>;
clocks = <&clks IMX1_CLK_HCLK>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
};
fb: fb@00205000 {
compatible = "fsl,imx1-fb";
reg = <0x00205000 0x1000>;
interrupts = <14>;
clocks = <&clks IMX1_CLK_DUMMY>,
<&clks IMX1_CLK_DUMMY>,
<&clks IMX1_CLK_PER2>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
uart1: serial@00206000 {
compatible = "fsl,imx1-uart";
reg = <0x00206000 0x1000>;
interrupts = <30 29 26>;
clocks = <&clks IMX1_CLK_HCLK>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
status = "disabled";
};
uart2: serial@00207000 {
compatible = "fsl,imx1-uart";
reg = <0x00207000 0x1000>;
interrupts = <24 23 20>;
clocks = <&clks IMX1_CLK_HCLK>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
status = "disabled";
};
pwm: pwm@00208000 {
#pwm-cells = <2>;
compatible = "fsl,imx1-pwm";
reg = <0x00208000 0x1000>;
interrupts = <34>;
clocks = <&clks IMX1_CLK_DUMMY>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
};
dma: dma@00209000 {
compatible = "fsl,imx1-dma";
reg = <0x00209000 0x1000>;
interrupts = <61 60>;
clocks = <&clks IMX1_CLK_HCLK>,
<&clks IMX1_CLK_DMA_GATE>;
clock-names = "ipg", "ahb";
#dma-cells = <1>;
};
uart3: serial@0020a000 {
compatible = "fsl,imx1-uart";
reg = <0x0020a000 0x1000>;
interrupts = <54 4 1>;
clocks = <&clks IMX1_CLK_UART3_GATE>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
status = "disabled";
};
};
aipi@00210000 {
compatible = "fsl,aipi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00210000 0x10000>;
ranges;
cspi1: cspi@00213000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx1-cspi";
reg = <0x00213000 0x1000>;
interrupts = <41>;
clocks = <&clks IMX1_CLK_DUMMY>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
status = "disabled";
};
i2c: i2c@00217000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx1-i2c";
reg = <0x00217000 0x1000>;
interrupts = <39>;
clocks = <&clks IMX1_CLK_HCLK>;
status = "disabled";
};
cspi2: cspi@00219000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx1-cspi";
reg = <0x00219000 0x1000>;
interrupts = <40>;
clocks = <&clks IMX1_CLK_DUMMY>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
status = "disabled";
};
clks: ccm@0021b000 {
compatible = "fsl,imx1-ccm";
reg = <0x0021b000 0x1000>;
#clock-cells = <1>;
};
iomuxc: iomuxc@0021c000 {
compatible = "fsl,imx1-iomuxc";
reg = <0x0021c000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio1: gpio@0021c000 {
compatible = "fsl,imx1-gpio";
reg = <0x0021c000 0x100>;
interrupts = <11>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@0021c100 {
compatible = "fsl,imx1-gpio";
reg = <0x0021c100 0x100>;
interrupts = <12>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@0021c200 {
compatible = "fsl,imx1-gpio";
reg = <0x0021c200 0x100>;
interrupts = <13>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@0021c300 {
compatible = "fsl,imx1-gpio";
reg = <0x0021c300 0x100>;
interrupts = <62>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
weim: weim@00220000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx1-weim";
reg = <0x00220000 0x1000>;
clocks = <&clks IMX1_CLK_DUMMY>;
ranges = <
0 0 0x10000000 0x02000000
1 0 0x12000000 0x01000000
2 0 0x13000000 0x01000000
3 0 0x14000000 0x01000000
4 0 0x15000000 0x01000000
5 0 0x16000000 0x01000000
>;
status = "disabled";
};
esram: esram@00300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x20000>;
};
};
};
arch/arm/boot/dts/imx23-evk.dts
View file @ 9cd70164
...@@ -60,10 +60,10 @@ lcdif@80030000 { ...@@ -60,10 +60,10 @@ lcdif@80030000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a>; pinctrl-0 = <&lcdif_24bit_pins_a>;
lcd-supply = <&reg_lcd_3v3>; lcd-supply = <&reg_lcd_3v3>;
display = <&display>; display = <&display0>;
status = "okay"; status = "okay";
display: display { display0: display0 {
bits-per-pixel = <32>; bits-per-pixel = <32>;
bus-width = <24>; bus-width = <24>;
......
arch/arm/boot/dts/imx25-pinfunc.h
View file @ 9cd70164
...@@ -247,6 +247,7 @@ ...@@ -247,6 +247,7 @@
#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000 #define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000
#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000 #define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000
#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x11 0x000
#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000 #define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000
#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001 #define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001
...@@ -260,6 +261,7 @@ ...@@ -260,6 +261,7 @@
#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000 #define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000 #define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000
#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000 #define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001 #define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
...@@ -269,31 +271,46 @@ ...@@ -269,31 +271,46 @@
#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000 #define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000 #define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x001
#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000 #define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000
#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000 #define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000
#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000 #define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000
#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000 #define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000
#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000 #define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000
#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 0x134 0x32C 0x4dc 0x12 0x001
#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000 #define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000
#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000 #define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000
#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x001
#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000 #define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000
#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000
#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000 #define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000
#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x001
#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000 #define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000
#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000
#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000 #define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000
#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x001
#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001
#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000 #define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000
#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000 #define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000
#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x001
#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001
#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000 #define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000
#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000 #define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000
#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x001
#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001
#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000 #define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000
#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000 #define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000
#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x001
#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001
#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000 #define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000
#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000 #define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000
...@@ -303,18 +320,24 @@ ...@@ -303,18 +320,24 @@
#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000 #define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000
#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000 #define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000
#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x000 0x12 0x000
#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000 #define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000
#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000 #define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000
#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x12 0x000
#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000 #define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000 #define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000
#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x12 0x000
#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000 #define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000 #define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000
#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x11 0x001
#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x12 0x000
#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000 #define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000 #define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000
#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x12 0x000
#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000 #define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000
#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000 #define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000
...@@ -328,6 +351,7 @@ ...@@ -328,6 +351,7 @@
#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000 #define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000
#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001 #define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001
#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x12 0x000
#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000 #define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000
#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000 #define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000
...@@ -342,6 +366,7 @@ ...@@ -342,6 +366,7 @@
#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000 #define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000
#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002 #define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002
#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000
#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000 #define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002 #define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002
...@@ -349,14 +374,17 @@ ...@@ -349,14 +374,17 @@
#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000 #define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000
#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000 #define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x11 0x001
#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002 #define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002
#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000 #define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000
#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000 #define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000
#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x11 0x001
#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002 #define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002
#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000 #define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000 #define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000
#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x11 0x001
#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000 #define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000 #define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000
...@@ -457,14 +485,15 @@ ...@@ -457,14 +485,15 @@
#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000 #define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000
#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000 #define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000
#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000
#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001 #define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001
#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000 #define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000
#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 #define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002
#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000
#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000 #define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000
#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000 #define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000
#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000
#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000 #define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000
#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000 #define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000
......
arch/arm/boot/dts/imx25.dtsi
View file @ 9cd70164
...@@ -239,6 +239,7 @@ spi2: cspi@50010000 { ...@@ -239,6 +239,7 @@ spi2: cspi@50010000 {
}; };
ssi2: ssi@50014000 { ssi2: ssi@50014000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
reg = <0x50014000 0x4000>; reg = <0x50014000 0x4000>;
interrupts = <11>; interrupts = <11>;
...@@ -274,6 +275,7 @@ tsc: tsc@50030000 { ...@@ -274,6 +275,7 @@ tsc: tsc@50030000 {
}; };
ssi1: ssi@50034000 { ssi1: ssi@50034000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
reg = <0x50034000 0x4000>; reg = <0x50034000 0x4000>;
interrupts = <12>; interrupts = <12>;
...@@ -453,7 +455,7 @@ gpio2: gpio@53fd0000 { ...@@ -453,7 +455,7 @@ gpio2: gpio@53fd0000 {
}; };
sdma: sdma@53fd4000 { sdma: sdma@53fd4000 {
compatible = "fsl,imx25-sdma", "fsl,imx35-sdma"; compatible = "fsl,imx25-sdma";
reg = <0x53fd4000 0x4000>; reg = <0x53fd4000 0x4000>;
clocks = <&clks 112>, <&clks 68>; clocks = <&clks 112>, <&clks 68>;
clock-names = "ipg", "ahb"; clock-names = "ipg", "ahb";
......
arch/arm/boot/dts/imx27-apf27dev.dts
View file @ 9cd70164
...@@ -67,6 +67,16 @@ &cspi1 { ...@@ -67,6 +67,16 @@ &cspi1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>; pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>;
status = "okay"; status = "okay";
adc@0 {
compatible = "maxim,max1027";
reg = <0>;
interrupt-parent = <&gpio5>;
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_max1027>;
spi-max-frequency = <10000000>;
};
}; };
&cspi2 { &cspi2 {
...@@ -189,6 +199,13 @@ MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 ...@@ -189,6 +199,13 @@ MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>; >;
}; };
pinctrl_max1027: max1027 {
fsl,pins = <
MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */
MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */
>;
};
pinctrl_pwm: pwmgrp { pinctrl_pwm: pwmgrp {
fsl,pins = < fsl,pins = <
MX27_PAD_PWMO__PWMO 0x0 MX27_PAD_PWMO__PWMO 0x0
......
arch/arm/boot/dts/imx28-apf28dev.dts
View file @ 9cd70164
...@@ -83,10 +83,10 @@ lcdif@80030000 { ...@@ -83,10 +83,10 @@ lcdif@80030000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&lcdif_16bit_pins_a pinctrl-0 = <&lcdif_16bit_pins_a
&lcdif_pins_apf28dev>; &lcdif_pins_apf28dev>;
display = <&display>; display = <&display0>;
status = "okay"; status = "okay";
display: display { display0: display0 {
bits-per-pixel = <16>; bits-per-pixel = <16>;
bus-width = <16>; bus-width = <16>;
......
arch/arm/boot/dts/imx28-apx4devkit.dts
View file @ 9cd70164
...@@ -94,10 +94,10 @@ lcdif@80030000 { ...@@ -94,10 +94,10 @@ lcdif@80030000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_apx4>; &lcdif_pins_apx4>;
display = <&display>; display = <&display0>;
status = "okay"; status = "okay";
display: display { display0: display0 {
bits-per-pixel = <32>; bits-per-pixel = <32>;
bus-width = <24>; bus-width = <24>;
......
arch/arm/boot/dts/imx28-cfa10049.dts
View file @ 9cd70164
...@@ -177,10 +177,10 @@ lcdif@80030000 { ...@@ -177,10 +177,10 @@ lcdif@80030000 {
pinctrl-0 = <&lcdif_18bit_pins_cfa10049 pinctrl-0 = <&lcdif_18bit_pins_cfa10049
&lcdif_pins_cfa10049 &lcdif_pins_cfa10049
&lcdif_pins_cfa10049_pullup>; &lcdif_pins_cfa10049_pullup>;
display = <&display>; display = <&display0>;
status = "okay"; status = "okay";
display: display { display0: display0 {
bits-per-pixel = <32>; bits-per-pixel = <32>;
bus-width = <18>; bus-width = <18>;
......
arch/arm/boot/dts/imx28-cfa10055.dts
View file @ 9cd70164
...@@ -92,10 +92,10 @@ lcdif@80030000 { ...@@ -92,10 +92,10 @@ lcdif@80030000 {
pinctrl-0 = <&lcdif_18bit_pins_cfa10055 pinctrl-0 = <&lcdif_18bit_pins_cfa10055
&lcdif_pins_cfa10055 &lcdif_pins_cfa10055
&lcdif_pins_cfa10055_pullup>; &lcdif_pins_cfa10055_pullup>;
display = <&display>; display = <&display0>;
status = "okay"; status = "okay";
display: display { display0: display0 {
bits-per-pixel = <32>; bits-per-pixel = <32>;
bus-width = <18>; bus-width = <18>;
......
arch/arm/boot/dts/imx28-cfa10056.dts
View file @ 9cd70164
...@@ -64,10 +64,10 @@ lcdif@80030000 { ...@@ -64,10 +64,10 @@ lcdif@80030000 {
pinctrl-0 = <&lcdif_24bit_pins_a pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_cfa10056 &lcdif_pins_cfa10056
&lcdif_pins_cfa10056_pullup >; &lcdif_pins_cfa10056_pullup >;
display = <&display>; display = <&display0>;
status = "okay"; status = "okay";
display: display { display0: display0 {
bits-per-pixel = <32>; bits-per-pixel = <32>;
bus-width = <24>; bus-width = <24>;
......
arch/arm/boot/dts/imx28-cfa10057.dts
View file @ 9cd70164
...@@ -78,10 +78,10 @@ lcdif@80030000 { ...@@ -78,10 +78,10 @@ lcdif@80030000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&lcdif_18bit_pins_cfa10057 pinctrl-0 = <&lcdif_18bit_pins_cfa10057
&lcdif_pins_cfa10057>; &lcdif_pins_cfa10057>;
display = <&display>; display = <&display0>;
status = "okay"; status = "okay";
display: display { display0: display0 {
bits-per-pixel = <32>; bits-per-pixel = <32>;
bus-width = <18>; bus-width = <18>;
......
arch/arm/boot/dts/imx28-cfa10058.dts
View file @ 9cd70164
...@@ -51,10 +51,10 @@ lcdif@80030000 { ...@@ -51,10 +51,10 @@ lcdif@80030000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_cfa10058>; &lcdif_pins_cfa10058>;
display = <&display>; display = <&display0>;
status = "okay"; status = "okay";
display: display { display0: display0 {
bits-per-pixel = <32>; bits-per-pixel = <32>;
bus-width = <24>; bus-width = <24>;
......
arch/arm/boot/dts/imx28-evk.dts
View file @ 9cd70164
...@@ -124,10 +124,10 @@ lcdif@80030000 { ...@@ -124,10 +124,10 @@ lcdif@80030000 {
pinctrl-0 = <&lcdif_24bit_pins_a pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_evk>; &lcdif_pins_evk>;
lcd-supply = <&reg_lcd_3v3>; lcd-supply = <&reg_lcd_3v3>;
display = <&display>; display = <&display0>;
status = "okay"; status = "okay";
display: display { display0: display0 {
bits-per-pixel = <32>; bits-per-pixel = <32>;
bus-width = <24>; bus-width = <24>;
......
arch/arm/boot/dts/imx28-m28cu3.dts
View file @ 9cd70164
...@@ -115,10 +115,10 @@ lcdif@80030000 { ...@@ -115,10 +115,10 @@ lcdif@80030000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_m28>; &lcdif_pins_m28>;
display = <&display>; display = <&display0>;
status = "okay"; status = "okay";
display: display0 { display0: display0 {
bits-per-pixel = <32>; bits-per-pixel = <32>;
bus-width = <24>; bus-width = <24>;
......
arch/arm/boot/dts/imx28-m28evk.dts
View file @ 9cd70164
...@@ -81,10 +81,10 @@ lcdif@80030000 { ...@@ -81,10 +81,10 @@ lcdif@80030000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_m28>; &lcdif_pins_m28>;
display = <&display>; display = <&display0>;
status = "okay"; status = "okay";
display: display { display0: display0 {
bits-per-pixel = <16>; bits-per-pixel = <16>;
bus-width = <18>; bus-width = <18>;
......
arch/arm/boot/dts/imx28-tx28.dts
View file @ 9cd70164
...@@ -21,12 +21,15 @@ / { ...@@ -21,12 +21,15 @@ / {
aliases { aliases {
can0 = &can0; can0 = &can0;
can1 = &can1; can1 = &can1;
display = &display; display = &display0;
ds1339 = &ds1339; ds1339 = &ds1339;
gpio5 = &gpio5; gpio5 = &gpio5;
lcdif = &lcdif; lcdif = &lcdif;
lcdif_23bit_pins = &tx28_lcdif_23bit_pins; lcdif_23bit_pins = &tx28_lcdif_23bit_pins;
lcdif_24bit_pins = &lcdif_24bit_pins_a; lcdif_24bit_pins = &lcdif_24bit_pins_a;
reg_can_xcvr = &reg_can_xcvr;
spi_gpio = &spi_gpio;
spi_mxs = &ssp3;
stk5led = &user_led; stk5led = &user_led;
usbotg = &usb0; usbotg = &usb0;
}; };
...@@ -37,7 +40,7 @@ memory { ...@@ -37,7 +40,7 @@ memory {
onewire { onewire {
compatible = "w1-gpio"; compatible = "w1-gpio";
gpios = <&gpio2 7 0>; gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
status = "disabled"; status = "disabled";
}; };
...@@ -52,7 +55,7 @@ reg_usb0_vbus: regulator@0 { ...@@ -52,7 +55,7 @@ reg_usb0_vbus: regulator@0 {
regulator-name = "usb0_vbus"; regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
gpio = <&gpio0 18 0>; gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
}; };
...@@ -62,7 +65,7 @@ reg_usb1_vbus: regulator@1 { ...@@ -62,7 +65,7 @@ reg_usb1_vbus: regulator@1 {
regulator-name = "usb1_vbus"; regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
gpio = <&gpio3 27 0>; gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
}; };
...@@ -90,7 +93,7 @@ reg_can_xcvr: regulator@4 { ...@@ -90,7 +93,7 @@ reg_can_xcvr: regulator@4 {
regulator-name = "CAN XCVR"; regulator-name = "CAN XCVR";
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
gpio = <&gpio1 0 0>; gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&tx28_flexcan_xcvr_pins>; pinctrl-0 = <&tx28_flexcan_xcvr_pins>;
}; };
...@@ -101,7 +104,7 @@ reg_lcd: regulator@5 { ...@@ -101,7 +104,7 @@ reg_lcd: regulator@5 {
regulator-name = "LCD POWER"; regulator-name = "LCD POWER";
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
gpio = <&gpio1 31 0>; gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
}; };
...@@ -111,7 +114,7 @@ reg_lcd_reset: regulator@6 { ...@@ -111,7 +114,7 @@ reg_lcd_reset: regulator@6 {
regulator-name = "LCD RESET"; regulator-name = "LCD RESET";
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
gpio = <&gpio3 30 0>; gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
startup-delay-us = <300000>; startup-delay-us = <300000>;
enable-active-high; enable-active-high;
regulator-always-on; regulator-always-on;
...@@ -143,7 +146,7 @@ leds { ...@@ -143,7 +146,7 @@ leds {
user_led: user { user_led: user {
label = "Heartbeat"; label = "Heartbeat";
gpios = <&gpio4 10 0>; gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
}; };
}; };
...@@ -172,16 +175,16 @@ backlight { ...@@ -172,16 +175,16 @@ backlight {
matrix_keypad: matrix-keypad@0 { matrix_keypad: matrix-keypad@0 {
compatible = "gpio-matrix-keypad"; compatible = "gpio-matrix-keypad";
col-gpios = < col-gpios = <
&gpio5 0 0 &gpio5 0 GPIO_ACTIVE_HIGH
&gpio5 1 0 &gpio5 1 GPIO_ACTIVE_HIGH
&gpio5 2 0 &gpio5 2 GPIO_ACTIVE_HIGH
&gpio5 3 0 &gpio5 3 GPIO_ACTIVE_HIGH
>; >;
row-gpios = < row-gpios = <
&gpio5 4 0 &gpio5 4 GPIO_ACTIVE_HIGH
&gpio5 5 0 &gpio5 5 GPIO_ACTIVE_HIGH
&gpio5 6 0 &gpio5 6 GPIO_ACTIVE_HIGH
&gpio5 7 0 &gpio5 7 GPIO_ACTIVE_HIGH
>; >;
/* sample keymap */ /* sample keymap */
linux,keymap = < linux,keymap = <
...@@ -203,6 +206,44 @@ &gpio5 7 0 ...@@ -203,6 +206,44 @@ &gpio5 7 0
col-scan-delay-us = <5000>; col-scan-delay-us = <5000>;
linux,no-autorepeat; linux,no-autorepeat;
}; };
spi_gpio: spi-gpio {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&tx28_spi_gpio_pins>;
gpio-sck = <&gpio2 24 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio2 25 GPIO_ACTIVE_HIGH>;
gpio-miso = <&gpio2 26 GPIO_ACTIVE_HIGH>;
num-chipselects = <3>;
cs-gpios = <
&gpio2 27 GPIO_ACTIVE_LOW
&gpio3 8 GPIO_ACTIVE_LOW
&gpio3 9 GPIO_ACTIVE_LOW
>;
/* enable this and disable ssp3 below, if you need full duplex SPI transfer */
status = "disabled";
spi@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <57600000>;
};
spi@1 {
compatible = "spidev";
reg = <1>;
spi-max-frequency = <57600000>;
};
spi@2 {
compatible = "spidev";
reg = <2>;
spi-max-frequency = <57600000>;
};
};
}; };
/* 2nd TX-Std UART - (A)UART1 */ /* 2nd TX-Std UART - (A)UART1 */
...@@ -284,8 +325,8 @@ polytouch: edt-ft5x06@38 { ...@@ -284,8 +325,8 @@ polytouch: edt-ft5x06@38 {
pinctrl-0 = <&tx28_edt_ft5x06_pins>; pinctrl-0 = <&tx28_edt_ft5x06_pins>;
interrupt-parent = <&gpio2>; interrupt-parent = <&gpio2>;
interrupts = <5 0>; interrupts = <5 0>;
reset-gpios = <&gpio2 6 1>; reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
wake-gpios = <&gpio4 9 0>; wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
}; };
touchscreen: tsc2007@48 { touchscreen: tsc2007@48 {
...@@ -295,7 +336,7 @@ touchscreen: tsc2007@48 { ...@@ -295,7 +336,7 @@ touchscreen: tsc2007@48 {
pinctrl-0 = <&tx28_tsc2007_pins>; pinctrl-0 = <&tx28_tsc2007_pins>;
interrupt-parent = <&gpio3>; interrupt-parent = <&gpio3>;
interrupts = <20 0>; interrupts = <20 0>;
pendown-gpio = <&gpio3 20 1>; pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
ti,x-plate-ohms = /bits/ 16 <660>; ti,x-plate-ohms = /bits/ 16 <660>;
}; };
...@@ -309,10 +350,10 @@ &lcdif { ...@@ -309,10 +350,10 @@ &lcdif {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>; pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>;
lcd-supply = <&reg_lcd>; lcd-supply = <&reg_lcd>;
display = <&display>; display = <&display0>;
status = "okay"; status = "okay";
display: display@0 { display0: display0 {
bits-per-pixel = <32>; bits-per-pixel = <32>;
bus-width = <24>; bus-width = <24>;
display-timings { display-timings {
...@@ -558,6 +599,20 @@ MX28_PAD_PWM3__GPIO_3_28 ...@@ -558,6 +599,20 @@ MX28_PAD_PWM3__GPIO_3_28
fsl,pull-up = <MXS_PULL_DISABLE>; fsl,pull-up = <MXS_PULL_DISABLE>;
}; };
tx28_spi_gpio_pins: spi-gpiogrp {
fsl,pinmux-ids = <
MX28_PAD_AUART2_RX__GPIO_3_8
MX28_PAD_AUART2_TX__GPIO_3_9
MX28_PAD_SSP3_SCK__GPIO_2_24
MX28_PAD_SSP3_MOSI__GPIO_2_25
MX28_PAD_SSP3_MISO__GPIO_2_26
MX28_PAD_SSP3_SS0__GPIO_2_27
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
tx28_tsc2007_pins: tx28-tsc2007-pins { tx28_tsc2007_pins: tx28-tsc2007-pins {
fsl,pinmux-ids = < fsl,pinmux-ids = <
MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */ MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */
...@@ -619,17 +674,23 @@ &ssp3 { ...@@ -619,17 +674,23 @@ &ssp3 {
clock-frequency = <57600000>; clock-frequency = <57600000>;
status = "okay"; status = "okay";
spidev0: spi@0 { spi@0 {
compatible = "spidev"; compatible = "spidev";
reg = <0>; reg = <0>;
spi-max-frequency = <57600000>; spi-max-frequency = <57600000>;
}; };
spidev1: spi@1 { spi@1 {
compatible = "spidev"; compatible = "spidev";
reg = <1>; reg = <1>;
spi-max-frequency = <57600000>; spi-max-frequency = <57600000>;
}; };
spi@2 {
compatible = "spidev";
reg = <2>;
spi-max-frequency = <57600000>;
};
}; };
&usb0 { &usb0 {
......
arch/arm/boot/dts/imx28.dtsi
View file @ 9cd70164
...@@ -489,6 +489,38 @@ MX28_PAD_SSP0_SCK__SSP0_SCK ...@@ -489,6 +489,38 @@ MX28_PAD_SSP0_SCK__SSP0_SCK
fsl,pull-up = <MXS_PULL_DISABLE>; fsl,pull-up = <MXS_PULL_DISABLE>;
}; };
mmc1_4bit_pins_a: mmc1-4bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_D00__SSP1_D0
MX28_PAD_GPMI_D01__SSP1_D1
MX28_PAD_GPMI_D02__SSP1_D2
MX28_PAD_GPMI_D03__SSP1_D3
MX28_PAD_GPMI_RDY1__SSP1_CMD
MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
MX28_PAD_GPMI_WRN__SSP1_SCK
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mmc1_cd_cfg: mmc1-cd-cfg {
fsl,pinmux-ids = <
MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
mmc1_sck_cfg: mmc1-sck-cfg {
fsl,pinmux-ids = <
MX28_PAD_GPMI_WRN__SSP1_SCK
>;
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
mmc2_4bit_pins_a: mmc2-4bit@0 { mmc2_4bit_pins_a: mmc2-4bit@0 {
reg = <0>; reg = <0>;
fsl,pinmux-ids = < fsl,pinmux-ids = <
...@@ -553,6 +585,17 @@ MX28_PAD_PWM1__I2C1_SDA ...@@ -553,6 +585,17 @@ MX28_PAD_PWM1__I2C1_SDA
fsl,pull-up = <MXS_PULL_ENABLE>; fsl,pull-up = <MXS_PULL_ENABLE>;
}; };
i2c1_pins_b: i2c1@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_AUART2_CTS__I2C1_SCL
MX28_PAD_AUART2_RTS__I2C1_SDA
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
saif0_pins_a: saif0@0 { saif0_pins_a: saif0@0 {
reg = <0>; reg = <0>;
fsl,pinmux-ids = < fsl,pinmux-ids = <
......
arch/arm/boot/dts/imx35.dtsi
View file @ 9cd70164
...@@ -114,6 +114,7 @@ i2c2: i2c@43f98000 { ...@@ -114,6 +114,7 @@ i2c2: i2c@43f98000 {
}; };
ssi1: ssi@43fa0000 { ssi1: ssi@43fa0000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx35-ssi", "fsl,imx21-ssi"; compatible = "fsl,imx35-ssi", "fsl,imx21-ssi";
reg = <0x43fa0000 0x4000>; reg = <0x43fa0000 0x4000>;
interrupts = <11>; interrupts = <11>;
......
arch/arm/boot/dts/imx50.dtsi
View file @ 9cd70164
...@@ -145,6 +145,7 @@ ecspi1: ecspi@50010000 { ...@@ -145,6 +145,7 @@ ecspi1: ecspi@50010000 {
}; };
ssi2: ssi@50014000 { ssi2: ssi@50014000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx50-ssi", compatible = "fsl,imx50-ssi",
"fsl,imx51-ssi", "fsl,imx51-ssi",
"fsl,imx21-ssi"; "fsl,imx21-ssi";
...@@ -454,6 +455,7 @@ i2c1: i2c@63fc8000 { ...@@ -454,6 +455,7 @@ i2c1: i2c@63fc8000 {
}; };
ssi1: ssi@63fcc000 { ssi1: ssi@63fcc000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx50-ssi", "fsl,imx51-ssi", compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
"fsl,imx21-ssi"; "fsl,imx21-ssi";
reg = <0x63fcc000 0x4000>; reg = <0x63fcc000 0x4000>;
......
arch/arm/boot/dts/imx51.dtsi
View file @ 9cd70164
...@@ -210,6 +210,7 @@ ecspi1: ecspi@70010000 { ...@@ -210,6 +210,7 @@ ecspi1: ecspi@70010000 {
}; };
ssi2: ssi@70014000 { ssi2: ssi@70014000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x70014000 0x4000>; reg = <0x70014000 0x4000>;
interrupts = <30>; interrupts = <30>;
...@@ -499,6 +500,7 @@ i2c1: i2c@83fc8000 { ...@@ -499,6 +500,7 @@ i2c1: i2c@83fc8000 {
}; };
ssi1: ssi@83fcc000 { ssi1: ssi@83fcc000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fcc000 0x4000>; reg = <0x83fcc000 0x4000>;
interrupts = <29>; interrupts = <29>;
...@@ -554,6 +556,7 @@ pata: pata@83fe0000 { ...@@ -554,6 +556,7 @@ pata: pata@83fe0000 {
}; };
ssi3: ssi@83fe8000 { ssi3: ssi@83fe8000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fe8000 0x4000>; reg = <0x83fe8000 0x4000>;
interrupts = <96>; interrupts = <96>;
......
arch/arm/boot/dts/imx53-smd.dts
View file @ 9cd70164
...@@ -265,7 +265,7 @@ camera: ov5642@3c { ...@@ -265,7 +265,7 @@ camera: ov5642@3c {
}; };
pmic: dialog@48 { pmic: dialog@48 {
compatible = "dialog,da9053", "dialog,da9052"; compatible = "dlg,da9053", "dlg,da9052";
reg = <0x48>; reg = <0x48>;
}; };
}; };
......
arch/arm/boot/dts/imx53.dtsi
View file @ 9cd70164
...@@ -221,6 +221,7 @@ ecspi1: ecspi@50010000 { ...@@ -221,6 +221,7 @@ ecspi1: ecspi@50010000 {
}; };
ssi2: ssi@50014000 { ssi2: ssi@50014000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx53-ssi", compatible = "fsl,imx53-ssi",
"fsl,imx51-ssi", "fsl,imx51-ssi",
"fsl,imx21-ssi"; "fsl,imx21-ssi";
...@@ -661,6 +662,7 @@ i2c1: i2c@63fc8000 { ...@@ -661,6 +662,7 @@ i2c1: i2c@63fc8000 {
}; };
ssi1: ssi@63fcc000 { ssi1: ssi@63fcc000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
"fsl,imx21-ssi"; "fsl,imx21-ssi";
reg = <0x63fcc000 0x4000>; reg = <0x63fcc000 0x4000>;
...@@ -688,6 +690,7 @@ nfc: nand@63fdb000 { ...@@ -688,6 +690,7 @@ nfc: nand@63fdb000 {
}; };
ssi3: ssi@63fe8000 { ssi3: ssi@63fe8000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
"fsl,imx21-ssi"; "fsl,imx21-ssi";
reg = <0x63fe8000 0x4000>; reg = <0x63fe8000 0x4000>;
...@@ -744,5 +747,10 @@ ocram: sram@f8000000 { ...@@ -744,5 +747,10 @@ ocram: sram@f8000000 {
reg = <0xf8000000 0x20000>; reg = <0xf8000000 0x20000>;
clocks = <&clks IMX5_CLK_OCRAM>; clocks = <&clks IMX5_CLK_OCRAM>;
}; };
pmu {
compatible = "arm,cortex-a8-pmu";
interrupts = <77>;
};
}; };
}; };
arch/arm/boot/dts/imx6dl-gw552x.dts 0 → 100644
View file @ 9cd70164
/*
* Copyright 2014 Gateworks Corporation
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw552x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X";
compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl";
};
arch/arm/boot/dts/imx6dl-hummingboard.dts
View file @ 9cd70164
/* /*
* Copyright (C) 2013,2014 Russell King * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
* Based on dt work by Russell King
*/ */
/dts-v1/; /dts-v1/;
#include "imx6dl.dtsi" #include "imx6dl.dtsi"
#include "imx6qdl-microsom.dtsi" #include "imx6qdl-hummingboard.dtsi"
#include "imx6qdl-microsom-ar8035.dtsi"
/ { / {
model = "SolidRun HummingBoard DL/Solo"; model = "SolidRun HummingBoard Solo/DualLite";
compatible = "solidrun,hummingboard", "fsl,imx6dl"; compatible = "solidrun,hummingboard/dl", "fsl,imx6dl";
chosen {
stdout-path = &uart1;
};
ir_recv: ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 2 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>;
};
regulators {
compatible = "simple-bus";
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usbh1_vbus: usb-h1-vbus {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 0 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usbotg_vbus: usb-otg-vbus {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 22 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "On-board SPDIF";
/* IMX6 doesn't implement this yet */
spdif-controller = <&spdif>;
spdif-out;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
status = "okay";
};
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
/*
* Not fitted on Carrier-1 board... yet
status = "okay";
rtc: pcf8523@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};
*/
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
status = "okay";
};
&iomuxc {
hummingboard {
pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
fsl,pins = <
MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
>;
};
pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
>;
};
pinctrl_hummingboard_hdmi: hummingboard-hdmi {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
>;
};
pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_hummingboard_spdif: hummingboard-spdif {
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
};
pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
};
pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
/*
* Similar to pinctrl_usbotg_2, but we want it
* pulled down for a fixed host connection.
*/
fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
};
pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
};
pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
fsl,pins = <
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
>;
};
pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
>;
};
};
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_spdif>;
status = "okay";
};
&usbh1 {
disable-over-current;
vbus-supply = <&reg_usbh1_vbus>;
status = "okay";
};
&usbotg {
disable-over-current;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
vbus-supply = <&reg_usbotg_vbus>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <
&pinctrl_hummingboard_usdhc2_aux
&pinctrl_hummingboard_usdhc2
>;
vmmc-supply = <&reg_3p3v>;
cd-gpios = <&gpio1 4 0>;
status = "okay";
}; };
arch/arm/boot/dts/imx6q-gw5400-a.dts
View file @ 9cd70164
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
*/ */
/dts-v1/; /dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6q.dtsi" #include "imx6q.dtsi"
/ { / {
...@@ -18,7 +19,6 @@ / { ...@@ -18,7 +19,6 @@ / {
/* these are used by bootloader for disabling nodes */ /* these are used by bootloader for disabling nodes */
aliases { aliases {
ethernet0 = &fec;
ethernet1 = &eth1; ethernet1 = &eth1;
i2c0 = &i2c1; i2c0 = &i2c1;
i2c1 = &i2c2; i2c1 = &i2c2;
...@@ -26,12 +26,10 @@ aliases { ...@@ -26,12 +26,10 @@ aliases {
led0 = &led0; led0 = &led0;
led1 = &led1; led1 = &led1;
led2 = &led2; led2 = &led2;
sky2 = &eth1;
ssi0 = &ssi1; ssi0 = &ssi1;
spi0 = &ecspi1; spi0 = &ecspi1;
usb0 = &usbh1; usb0 = &usbh1;
usb1 = &usbotg; usb1 = &usbotg;
usdhc2 = &usdhc3;
}; };
chosen { chosen {
...@@ -40,23 +38,25 @@ chosen { ...@@ -40,23 +38,25 @@ chosen {
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 { led0: user1 {
label = "user1"; label = "user1";
gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 -> MX6_PANLEDG */
default-state = "on"; default-state = "on";
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
}; };
led1: user2 { led1: user2 {
label = "user2"; label = "user2";
gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR */ gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* 106 -> MX6_PANLEDR */
default-state = "off"; default-state = "off";
}; };
led2: user3 { led2: user3 {
label = "user3"; label = "user3";
gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* 111 -> MX6_LOCLED# */
default-state = "off"; default-state = "off";
}; };
}; };
...@@ -67,7 +67,9 @@ memory { ...@@ -67,7 +67,9 @@ memory {
pps { pps {
compatible = "pps-gpio"; compatible = "pps-gpio";
gpios = <&gpio1 5 0>; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
}; };
...@@ -109,7 +111,7 @@ reg_usb_otg_vbus: regulator@3 { ...@@ -109,7 +111,7 @@ reg_usb_otg_vbus: regulator@3 {
regulator-name = "usb_otg_vbus"; regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>; gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
}; };
}; };
...@@ -137,7 +139,7 @@ &audmux { ...@@ -137,7 +139,7 @@ &audmux {
&ecspi1 { &ecspi1 {
fsl,spi-num-chipselects = <1>; fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>; cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>; pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay"; status = "okay";
...@@ -153,7 +155,7 @@ &fec { ...@@ -153,7 +155,7 @@ &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 30 0>; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
}; };
...@@ -199,11 +201,6 @@ gpio: pca9555@23 { ...@@ -199,11 +201,6 @@ gpio: pca9555@23 {
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
hwmon: gsc@29 {
compatible = "gw,gsp";
reg = <0x29>;
};
rtc: ds1672@68 { rtc: ds1672@68 {
compatible = "dallas,ds1672"; compatible = "dallas,ds1672";
reg = <0x68>; reg = <0x68>;
...@@ -314,16 +311,6 @@ vgen6_reg: vgen6 { ...@@ -314,16 +311,6 @@ vgen6_reg: vgen6 {
}; };
}; };
}; };
pciswitch: pex8609@3f {
compatible = "plx,pex8609";
reg = <0x3f>;
};
pciclkgen: si52147@6b {
compatible = "sil,si52147";
reg = <0x6b>;
};
}; };
&i2c3 { &i2c3 {
...@@ -345,51 +332,73 @@ codec: sgtl5000@0a { ...@@ -345,51 +332,73 @@ codec: sgtl5000@0a {
VDDIO-supply = <&reg_3p3v>; VDDIO-supply = <&reg_3p3v>;
}; };
hdmiin: adv7611@4c {
compatible = "adi,adv7611";
reg = <0x4c>;
};
touchscreen: egalax_ts@04 { touchscreen: egalax_ts@04 {
compatible = "eeti,egalax_ts"; compatible = "eeti,egalax_ts";
reg = <0x04>; reg = <0x04>;
interrupt-parent = <&gpio7>; interrupt-parent = <&gpio7>;
interrupts = <12 2>; /* gpio7_12 active low */ interrupts = <12 2>;
wakeup-gpios = <&gpio7 12 0>; wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
}; };
};
videoout: adv7393@2a { &ldb {
compatible = "adi,adv7393"; status = "okay";
reg = <0x2a>; };
};
&pcie {
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
videoin: adv7180@20 { eth1: sky2@8 { /* MAC/PHY on bus 8 */
compatible = "adi,adv7180"; compatible = "marvell,sky2";
reg = <0x20>;
}; };
}; };
&iomuxc { &ssi1 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>; pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&iomuxc {
imx6q-gw5400-a { imx6q-gw5400-a {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* GPS_PPS */
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* user2 led */
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */
MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */
>;
};
pinctrl_audmux: audmuxgrp { pinctrl_audmux: audmuxgrp {
fsl,pins = < fsl,pins = <
...@@ -397,6 +406,7 @@ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 ...@@ -397,6 +406,7 @@ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
>; >;
}; };
...@@ -405,6 +415,7 @@ pinctrl_ecspi1: ecspi1grp { ...@@ -405,6 +415,7 @@ pinctrl_ecspi1: ecspi1grp {
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */
>; >;
}; };
...@@ -429,6 +440,14 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 ...@@ -429,6 +440,14 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>; >;
}; };
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */
>;
};
pinctrl_i2c1: i2c1grp { pinctrl_i2c1: i2c1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
...@@ -450,6 +469,19 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 ...@@ -450,6 +469,19 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>; >;
}; };
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */
>;
};
pinctrl_uart1: uart1grp { pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
...@@ -474,6 +506,7 @@ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 ...@@ -474,6 +506,7 @@ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
pinctrl_usbotg: usbotggrp { pinctrl_usbotg: usbotggrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
>; >;
}; };
...@@ -489,59 +522,3 @@ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 ...@@ -489,59 +522,3 @@ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
}; };
}; };
}; };
&ldb {
status = "okay";
};
&pcie {
reset-gpio = <&gpio1 29 0>;
status = "okay";
eth1: sky2@8 { /* MAC/PHY on bus 8 */
compatible = "marvell,sky2";
};
};
&ssi1 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
arch/arm/boot/dts/imx6q-gw552x.dts 0 → 100644
View file @ 9cd70164
/*
* Copyright 2014 Gateworks Corporation
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw552x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW552X";
compatible = "gw,imx6q-gw552x", "gw,ventana", "fsl,imx6q";
};
&sata {
status = "okay";
};
arch/arm/boot/dts/imx6q-hummingboard.dts 0 → 100644
View file @ 9cd70164
/*
* Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
* Based on dt work by Russell King
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-hummingboard.dtsi"
/ {
model = "SolidRun HummingBoard Dual/Quad";
compatible = "solidrun,hummingboard/q", "fsl,imx6q";
};
&sata {
status = "okay";
fsl,transmit-level-mV = <1025>;
fsl,transmit-boost-mdB = <3330>;
fsl,transmit-atten-16ths = <9>;
fsl,receive-eq-mdB = <3000>;
};
arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
View file @ 9cd70164
...@@ -9,11 +9,11 @@ ...@@ -9,11 +9,11 @@
* http://www.gnu.org/copyleft/gpl.html * http://www.gnu.org/copyleft/gpl.html
*/ */
#include <dt-bindings/gpio/gpio.h>
/ { / {
/* these are used by bootloader for disabling nodes */ /* these are used by bootloader for disabling nodes */
aliases { aliases {
can0 = &can1;
ethernet0 = &fec;
led0 = &led0; led0 = &led0;
led1 = &led1; led1 = &led1;
nand = &gpmi; nand = &gpmi;
...@@ -27,17 +27,19 @@ chosen { ...@@ -27,17 +27,19 @@ chosen {
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 { led0: user1 {
label = "user1"; label = "user1";
gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on"; default-state = "on";
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
}; };
led1: user2 { led1: user2 {
label = "user2"; label = "user2";
gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off"; default-state = "off";
}; };
}; };
...@@ -48,7 +50,9 @@ memory { ...@@ -48,7 +50,9 @@ memory {
pps { pps {
compatible = "pps-gpio"; compatible = "pps-gpio";
gpios = <&gpio1 26 0>; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
}; };
...@@ -81,7 +85,7 @@ reg_usb_otg_vbus: regulator@2 { ...@@ -81,7 +85,7 @@ reg_usb_otg_vbus: regulator@2 {
regulator-name = "usb_otg_vbus"; regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>; gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
}; };
}; };
...@@ -91,7 +95,7 @@ &fec { ...@@ -91,7 +95,7 @@ &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 30 0>; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
...@@ -143,11 +147,6 @@ gpio: pca9555@23 { ...@@ -143,11 +147,6 @@ gpio: pca9555@23 {
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
hwmon: gsc@29 {
compatible = "gw,gsp";
reg = <0x29>;
};
rtc: ds1672@68 { rtc: ds1672@68 {
compatible = "dallas,ds1672"; compatible = "dallas,ds1672";
reg = <0x68>; reg = <0x68>;
...@@ -159,53 +158,6 @@ &i2c2 { ...@@ -159,53 +158,6 @@ &i2c2 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>; pinctrl-0 = <&pinctrl_i2c2>;
status = "okay"; status = "okay";
pmic: ltc3676@3c {
compatible = "lltc,ltc3676";
reg = <0x3c>;
regulators {
sw1_reg: ltc3676__sw1 {
regulator-min-microvolt = <1175000>;
regulator-max-microvolt = <1175000>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: ltc3676__sw2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: ltc3676__sw3 {
regulator-min-microvolt = <1175000>;
regulator-max-microvolt = <1175000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: ltc3676__sw4 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ltc3676__ldo2 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: ltc3676__ldo4 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
};
};
}; };
&i2c3 { &i2c3 {
...@@ -213,31 +165,53 @@ &i2c3 { ...@@ -213,31 +165,53 @@ &i2c3 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>; pinctrl-0 = <&pinctrl_i2c3>;
status = "okay"; status = "okay";
};
videoin: adv7180@20 { &pcie {
compatible = "adi,adv7180"; pinctrl-names = "default";
reg = <0x20>; pinctrl-0 = <&pinctrl_pcie>;
}; reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";
}; };
&iomuxc { &uart1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>; pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
imx6qdl-gw51xx { &uart2 {
pinctrl_hog: hoggrp { pinctrl-names = "default";
fsl,pins = < pinctrl-0 = <&pinctrl_uart2>;
MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ status = "okay";
MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ };
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 /* PCIE_RST# */
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */
>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usbh1 {
status = "okay";
};
&iomuxc {
imx6qdl-gw51xx {
pinctrl_enet: enetgrp { pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
...@@ -256,6 +230,14 @@ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 ...@@ -256,6 +230,14 @@ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
>; >;
}; };
...@@ -301,6 +283,18 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 ...@@ -301,6 +283,18 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>; >;
}; };
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>;
};
pinctrl_uart1: uart1grp { pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
...@@ -332,48 +326,8 @@ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 ...@@ -332,48 +326,8 @@ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
pinctrl_usbotg: usbotggrp { pinctrl_usbotg: usbotggrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
>; >;
}; };
}; };
}; };
&pcie {
reset-gpio = <&gpio1 0 0>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usbh1 {
status = "okay";
};
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
View file @ 9cd70164
...@@ -9,10 +9,11 @@ ...@@ -9,10 +9,11 @@
* http://www.gnu.org/copyleft/gpl.html * http://www.gnu.org/copyleft/gpl.html
*/ */
#include <dt-bindings/gpio/gpio.h>
/ { / {
/* these are used by bootloader for disabling nodes */ /* these are used by bootloader for disabling nodes */
aliases { aliases {
ethernet0 = &fec;
led0 = &led0; led0 = &led0;
led1 = &led1; led1 = &led1;
led2 = &led2; led2 = &led2;
...@@ -20,7 +21,6 @@ aliases { ...@@ -20,7 +21,6 @@ aliases {
ssi0 = &ssi1; ssi0 = &ssi1;
usb0 = &usbh1; usb0 = &usbh1;
usb1 = &usbotg; usb1 = &usbotg;
usdhc2 = &usdhc3;
}; };
chosen { chosen {
...@@ -36,23 +36,25 @@ backlight { ...@@ -36,23 +36,25 @@ backlight {
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 { led0: user1 {
label = "user1"; label = "user1";
gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on"; default-state = "on";
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
}; };
led1: user2 { led1: user2 {
label = "user2"; label = "user2";
gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off"; default-state = "off";
}; };
led2: user3 { led2: user3 {
label = "user3"; label = "user3";
gpios = <&gpio4 15 1>; /* 111 - MX6_LOCLED# */ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off"; default-state = "off";
}; };
}; };
...@@ -63,7 +65,9 @@ memory { ...@@ -63,7 +65,9 @@ memory {
pps { pps {
compatible = "pps-gpio"; compatible = "pps-gpio";
gpios = <&gpio1 26 0>; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
}; };
...@@ -115,7 +119,7 @@ reg_usb_otg_vbus: regulator@4 { ...@@ -115,7 +119,7 @@ reg_usb_otg_vbus: regulator@4 {
regulator-name = "usb_otg_vbus"; regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>; gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
}; };
}; };
...@@ -141,11 +145,17 @@ &audmux { ...@@ -141,11 +145,17 @@ &audmux {
status = "okay"; status = "okay";
}; };
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 30 0>; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
...@@ -197,11 +207,6 @@ gpio: pca9555@23 { ...@@ -197,11 +207,6 @@ gpio: pca9555@23 {
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
hwmon: gsc@29 {
compatible = "gw,gsp";
reg = <0x29>;
};
rtc: ds1672@68 { rtc: ds1672@68 {
compatible = "dallas,ds1672"; compatible = "dallas,ds1672";
reg = <0x68>; reg = <0x68>;
...@@ -213,65 +218,6 @@ &i2c2 { ...@@ -213,65 +218,6 @@ &i2c2 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>; pinctrl-0 = <&pinctrl_i2c2>;
status = "okay"; status = "okay";
pciswitch: pex8609@3f {
compatible = "plx,pex8609";
reg = <0x3f>;
};
pmic: ltc3676@3c {
compatible = "lltc,ltc3676";
reg = <0x3c>;
regulators {
sw1_reg: ltc3676__sw1 {
regulator-min-microvolt = <1175000>;
regulator-max-microvolt = <1175000>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: ltc3676__sw2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: ltc3676__sw3 {
regulator-min-microvolt = <1175000>;
regulator-max-microvolt = <1175000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: ltc3676__sw4 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ltc3676__ldo2 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: ltc3676__ldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: ltc3676__ldo4 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
};
};
}; };
&i2c3 { &i2c3 {
...@@ -280,11 +226,6 @@ &i2c3 { ...@@ -280,11 +226,6 @@ &i2c3 {
pinctrl-0 = <&pinctrl_i2c3>; pinctrl-0 = <&pinctrl_i2c3>;
status = "okay"; status = "okay";
accelerometer: fxos8700@1e {
compatible = "fsl,fxos8700";
reg = <0x13>;
};
codec: sgtl5000@0a { codec: sgtl5000@0a {
compatible = "fsl,sgtl5000"; compatible = "fsl,sgtl5000";
reg = <0x0a>; reg = <0x0a>;
...@@ -297,49 +238,101 @@ touchscreen: egalax_ts@04 { ...@@ -297,49 +238,101 @@ touchscreen: egalax_ts@04 {
compatible = "eeti,egalax_ts"; compatible = "eeti,egalax_ts";
reg = <0x04>; reg = <0x04>;
interrupt-parent = <&gpio7>; interrupt-parent = <&gpio7>;
interrupts = <12 2>; /* gpio7_12 active low */ interrupts = <12 2>;
wakeup-gpios = <&gpio7 12 0>; wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
}; };
};
&ldb {
status = "okay";
videoin: adv7180@20 { lvds-channel@0 {
compatible = "adi,adv7180"; fsl,data-mapping = "spwg";
reg = <0x20>; fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
}; };
}; };
&iomuxc { &pcie {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>; pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
};
imx6qdl-gw52xx { &pwm4 {
pinctrl_hog: hoggrp { pinctrl-names = "default";
fsl,pins = < pinctrl-0 = <&pinctrl_pwm4>;
MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ status = "okay";
MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ };
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x80000000 /* VIDDEC_PDN# */ &ssi1 {
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ fsl,mode = "i2s-slave";
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */ status = "okay";
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */ };
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ &uart1 {
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USB_SEL_PCI */ pinctrl-names = "default";
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ pinctrl-0 = <&pinctrl_uart1>;
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ status = "okay";
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ };
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */
MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* LVDS_TCH# */ &uart2 {
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_CD# */ pinctrl-names = "default";
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 /* UART2_EN# */ pinctrl-0 = <&pinctrl_uart2>;
>; status = "okay";
}; };
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usbh1 {
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&iomuxc {
imx6qdl-gw52xx {
pinctrl_audmux: audmuxgrp { pinctrl_audmux: audmuxgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
>; >;
}; };
...@@ -361,6 +354,23 @@ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 ...@@ -361,6 +354,23 @@ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>; >;
}; };
...@@ -406,6 +416,18 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 ...@@ -406,6 +416,18 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>; >;
}; };
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp { pinctrl_pwm4: pwm4grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
...@@ -436,6 +458,7 @@ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 ...@@ -436,6 +458,7 @@ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
pinctrl_usbotg: usbotggrp { pinctrl_usbotg: usbotggrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
>; >;
}; };
...@@ -447,85 +470,8 @@ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 ...@@ -447,85 +470,8 @@ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
>; >;
}; };
}; };
}; };
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&pcie {
reset-gpio = <&gpio1 29 0>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usbh1 {
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
View file @ 9cd70164
...@@ -9,21 +9,19 @@ ...@@ -9,21 +9,19 @@
* http://www.gnu.org/copyleft/gpl.html * http://www.gnu.org/copyleft/gpl.html
*/ */
#include <dt-bindings/gpio/gpio.h>
/ { / {
/* these are used by bootloader for disabling nodes */ /* these are used by bootloader for disabling nodes */
aliases { aliases {
can0 = &can1;
ethernet0 = &fec;
ethernet1 = &eth1; ethernet1 = &eth1;
led0 = &led0; led0 = &led0;
led1 = &led1; led1 = &led1;
led2 = &led2; led2 = &led2;
nand = &gpmi; nand = &gpmi;
sky2 = &eth1;
ssi0 = &ssi1; ssi0 = &ssi1;
usb0 = &usbh1; usb0 = &usbh1;
usb1 = &usbotg; usb1 = &usbotg;
usdhc2 = &usdhc3;
}; };
chosen { chosen {
...@@ -39,23 +37,25 @@ backlight { ...@@ -39,23 +37,25 @@ backlight {
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 { led0: user1 {
label = "user1"; label = "user1";
gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on"; default-state = "on";
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
}; };
led1: user2 { led1: user2 {
label = "user2"; label = "user2";
gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off"; default-state = "off";
}; };
led2: user3 { led2: user3 {
label = "user3"; label = "user3";
gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off"; default-state = "off";
}; };
}; };
...@@ -66,7 +66,9 @@ memory { ...@@ -66,7 +66,9 @@ memory {
pps { pps {
compatible = "pps-gpio"; compatible = "pps-gpio";
gpios = <&gpio1 26 0>; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
}; };
...@@ -118,7 +120,7 @@ reg_usb_otg_vbus: regulator@4 { ...@@ -118,7 +120,7 @@ reg_usb_otg_vbus: regulator@4 {
regulator-name = "usb_otg_vbus"; regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>; gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
}; };
}; };
...@@ -154,7 +156,7 @@ &fec { ...@@ -154,7 +156,7 @@ &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 30 0>; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
...@@ -206,11 +208,6 @@ gpio: pca9555@23 { ...@@ -206,11 +208,6 @@ gpio: pca9555@23 {
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
hwmon: gsc@29 {
compatible = "gw,gsp";
reg = <0x29>;
};
rtc: ds1672@68 { rtc: ds1672@68 {
compatible = "dallas,ds1672"; compatible = "dallas,ds1672";
reg = <0x68>; reg = <0x68>;
...@@ -222,77 +219,6 @@ &i2c2 { ...@@ -222,77 +219,6 @@ &i2c2 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>; pinctrl-0 = <&pinctrl_i2c2>;
status = "okay"; status = "okay";
pciclkgen: si53156@6b {
compatible = "sil,si53156";
reg = <0x6b>;
};
pciswitch: pex8606@3f {
compatible = "plx,pex8606";
reg = <0x3f>;
};
pmic: ltc3676@3c {
compatible = "lltc,ltc3676";
reg = <0x3c>;
regulators {
/* VDD_SOC */
sw1_reg: ltc3676__sw1 {
regulator-min-microvolt = <1175000>;
regulator-max-microvolt = <1175000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_1P8 */
sw2_reg: ltc3676__sw2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_ARM */
sw3_reg: ltc3676__sw3 {
regulator-min-microvolt = <1175000>;
regulator-max-microvolt = <1175000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_DDR */
sw4_reg: ltc3676__sw4 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_2P5 */
ldo2_reg: ltc3676__ldo2 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_1P8 */
ldo3_reg: ltc3676__ldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_HIGH */
ldo4_reg: ltc3676__ldo4 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
};
};
}; };
&i2c3 { &i2c3 {
...@@ -301,11 +227,6 @@ &i2c3 { ...@@ -301,11 +227,6 @@ &i2c3 {
pinctrl-0 = <&pinctrl_i2c3>; pinctrl-0 = <&pinctrl_i2c3>;
status = "okay"; status = "okay";
accelerometer: fxos8700@1e {
compatible = "fsl,fxos8700";
reg = <0x1e>;
};
codec: sgtl5000@0a { codec: sgtl5000@0a {
compatible = "fsl,sgtl5000"; compatible = "fsl,sgtl5000";
reg = <0x0a>; reg = <0x0a>;
...@@ -314,65 +235,110 @@ codec: sgtl5000@0a { ...@@ -314,65 +235,110 @@ codec: sgtl5000@0a {
VDDIO-supply = <&reg_3p3v>; VDDIO-supply = <&reg_3p3v>;
}; };
hdmiin: adv7611@4c {
compatible = "adi,adv7611";
reg = <0x4c>;
};
touchscreen: egalax_ts@04 { touchscreen: egalax_ts@04 {
compatible = "eeti,egalax_ts"; compatible = "eeti,egalax_ts";
reg = <0x04>; reg = <0x04>;
interrupt-parent = <&gpio1>; interrupt-parent = <&gpio1>;
interrupts = <11 2>; /* gpio1_11 active low */ interrupts = <11 2>;
wakeup-gpios = <&gpio1 11 0>; wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
}; };
};
videoout: adv7393@2a { &ldb {
compatible = "adi,adv7393"; status = "okay";
reg = <0x2a>;
lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
}; };
};
videoin: adv7180@20 { &pcie {
compatible = "adi,adv7180"; pinctrl-names = "default";
reg = <0x20>; pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
eth1: sky2@8 { /* MAC/PHY on bus 8 */
compatible = "marvell,sky2";
}; };
}; };
&iomuxc { &pwm4 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>; pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
imx6qdl-gw53xx { &ssi1 {
pinctrl_hog: hoggrp { fsl,mode = "i2s-slave";
fsl,pins = < status = "okay";
MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* PCIE6EXP_DIO0 */ };
MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* PCIE6EXP_DIO1 */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ &uart1 {
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_SHDN */ pinctrl-names = "default";
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ pinctrl-0 = <&pinctrl_uart1>;
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ status = "okay";
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ };
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ &uart2 {
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 /* PMIC_IRQ# */ pinctrl-names = "default";
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* HUB_RST# */ pinctrl-0 = <&pinctrl_uart2>;
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIE_WDIS# */ status = "okay";
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* ACCEL_IRQ# */ };
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 /* USBOTG_OC# */
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */
MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* TOUCH_IRQ# */
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_DET# */
>;
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&iomuxc {
imx6qdl-gw53xx {
pinctrl_audmux: audmuxgrp { pinctrl_audmux: audmuxgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
>; >;
}; };
...@@ -399,8 +365,17 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 ...@@ -399,8 +365,17 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
pinctrl_flexcan1: flexcan1grp { pinctrl_flexcan1: flexcan1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>; >;
}; };
...@@ -446,6 +421,19 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 ...@@ -446,6 +421,19 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>; >;
}; };
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp { pinctrl_pwm4: pwm4grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
...@@ -476,6 +464,8 @@ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 ...@@ -476,6 +464,8 @@ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
pinctrl_usbotg: usbotggrp { pinctrl_usbotg: usbotggrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
>; >;
}; };
...@@ -487,90 +477,8 @@ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 ...@@ -487,90 +477,8 @@ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
>; >;
}; };
}; };
}; };
&ldb {
status = "okay";
lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&pcie {
reset-gpio = <&gpio1 29 0>;
status = "okay";
eth1: sky2@8 { /* MAC/PHY on bus 8 */
compatible = "marvell,sky2";
};
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
View file @ 9cd70164
...@@ -9,21 +9,19 @@ ...@@ -9,21 +9,19 @@
* http://www.gnu.org/copyleft/gpl.html * http://www.gnu.org/copyleft/gpl.html
*/ */
#include <dt-bindings/gpio/gpio.h>
/ { / {
/* these are used by bootloader for disabling nodes */ /* these are used by bootloader for disabling nodes */
aliases { aliases {
can0 = &can1;
ethernet0 = &fec;
ethernet1 = &eth1; ethernet1 = &eth1;
led0 = &led0; led0 = &led0;
led1 = &led1; led1 = &led1;
led2 = &led2; led2 = &led2;
nand = &gpmi; nand = &gpmi;
sky2 = &eth1;
ssi0 = &ssi1; ssi0 = &ssi1;
usb0 = &usbh1; usb0 = &usbh1;
usb1 = &usbotg; usb1 = &usbotg;
usdhc2 = &usdhc3;
}; };
chosen { chosen {
...@@ -39,23 +37,25 @@ backlight { ...@@ -39,23 +37,25 @@ backlight {
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 { led0: user1 {
label = "user1"; label = "user1";
gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on"; default-state = "on";
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
}; };
led1: user2 { led1: user2 {
label = "user2"; label = "user2";
gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off"; default-state = "off";
}; };
led2: user3 { led2: user3 {
label = "user3"; label = "user3";
gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off"; default-state = "off";
}; };
}; };
...@@ -66,7 +66,9 @@ memory { ...@@ -66,7 +66,9 @@ memory {
pps { pps {
compatible = "pps-gpio"; compatible = "pps-gpio";
gpios = <&gpio1 26 0>; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
}; };
...@@ -108,7 +110,7 @@ reg_usb_otg_vbus: regulator@3 { ...@@ -108,7 +110,7 @@ reg_usb_otg_vbus: regulator@3 {
regulator-name = "usb_otg_vbus"; regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>; gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
}; };
}; };
...@@ -144,7 +146,7 @@ &fec { ...@@ -144,7 +146,7 @@ &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 30 0>; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
...@@ -196,11 +198,6 @@ gpio: pca9555@23 { ...@@ -196,11 +198,6 @@ gpio: pca9555@23 {
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
hwmon: gsc@29 {
compatible = "gw,gsp";
reg = <0x29>;
};
rtc: ds1672@68 { rtc: ds1672@68 {
compatible = "dallas,ds1672"; compatible = "dallas,ds1672";
reg = <0x68>; reg = <0x68>;
...@@ -311,16 +308,6 @@ vgen6_reg: vgen6 { ...@@ -311,16 +308,6 @@ vgen6_reg: vgen6 {
}; };
}; };
}; };
pciswitch: pex8609@3f {
compatible = "plx,pex8609";
reg = <0x3f>;
};
pciclkgen: si52147@6b {
compatible = "sil,si52147";
reg = <0x6b>;
};
}; };
&i2c3 { &i2c3 {
...@@ -329,11 +316,6 @@ &i2c3 { ...@@ -329,11 +316,6 @@ &i2c3 {
pinctrl-0 = <&pinctrl_i2c3>; pinctrl-0 = <&pinctrl_i2c3>;
status = "okay"; status = "okay";
accelerometer: fxos8700@1e {
compatible = "fsl,fxos8700";
reg = <0x1e>;
};
codec: sgtl5000@0a { codec: sgtl5000@0a {
compatible = "fsl,sgtl5000"; compatible = "fsl,sgtl5000";
reg = <0x0a>; reg = <0x0a>;
...@@ -342,59 +324,115 @@ codec: sgtl5000@0a { ...@@ -342,59 +324,115 @@ codec: sgtl5000@0a {
VDDIO-supply = <&reg_3p3v>; VDDIO-supply = <&reg_3p3v>;
}; };
hdmiin: adv7611@4c {
compatible = "adi,adv7611";
reg = <0x4c>;
};
touchscreen: egalax_ts@04 { touchscreen: egalax_ts@04 {
compatible = "eeti,egalax_ts"; compatible = "eeti,egalax_ts";
reg = <0x04>; reg = <0x04>;
interrupt-parent = <&gpio7>; interrupt-parent = <&gpio7>;
interrupts = <12 2>; /* gpio7_12 active low */ interrupts = <12 2>;
wakeup-gpios = <&gpio7 12 0>; wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
}; };
};
videoout: adv7393@2a { &ldb {
compatible = "adi,adv7393"; status = "okay";
reg = <0x2a>;
lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
}; };
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
videoin: adv7180@20 { eth1: sky2@8 { /* MAC/PHY on bus 8 */
compatible = "adi,adv7180"; compatible = "marvell,sky2";
reg = <0x20>;
}; };
}; };
&iomuxc { &pwm4 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>; pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
imx6qdl-gw54xx { &ssi1 {
pinctrl_hog: hoggrp { fsl,mode = "i2s-slave";
fsl,pins = < status = "okay";
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ };
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ &ssi2 {
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ fsl,mode = "i2s-slave";
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ status = "okay";
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ };
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ &uart1 {
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ pinctrl-names = "default";
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ pinctrl-0 = <&pinctrl_uart1>;
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ status = "okay";
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ };
MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */
>; &uart2 {
}; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&iomuxc {
imx6qdl-gw54xx {
pinctrl_audmux: audmuxgrp { pinctrl_audmux: audmuxgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
>; >;
}; };
...@@ -421,8 +459,17 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 ...@@ -421,8 +459,17 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
pinctrl_flexcan1: flexcan1grp { pinctrl_flexcan1: flexcan1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>; >;
}; };
...@@ -468,6 +515,19 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 ...@@ -468,6 +515,19 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>; >;
}; };
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp { pinctrl_pwm4: pwm4grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
...@@ -498,6 +558,7 @@ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 ...@@ -498,6 +558,7 @@ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
pinctrl_usbotg: usbotggrp { pinctrl_usbotg: usbotggrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
>; >;
}; };
...@@ -513,90 +574,3 @@ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 ...@@ -513,90 +574,3 @@ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
}; };
}; };
}; };
&ldb {
status = "okay";
lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&pcie {
reset-gpio = <&gpio1 29 0>;
status = "okay";
eth1: sky2@8 { /* MAC/PHY on bus 8 */
compatible = "marvell,sky2";
};
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&ssi2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
arch/arm/boot/dts/imx6qdl-gw552x.dtsi 0 → 100644
View file @ 9cd70164
/*
* Copyright 2014 Gateworks Corporation
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <dt-bindings/gpio/gpio.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
nand = &gpmi;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
bootargs = "console=ttymxc1,115200";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
led2: user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
};
};
memory {
reg = <0x10000000 0x20000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_1p0v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "1P0V";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
reg_3p3v: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom2: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom3: eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom4: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
gpio: pca9555@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay"; };
&usbh1 {
status = "okay";
};
&iomuxc {
imx6qdl-gw552x {
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
};
};
arch/arm/boot/dts/imx6qdl-hummingboard.dtsi 0 → 100644
View file @ 9cd70164
/*
* Copyright (C) 2013,2014 Russell King
*/
#include "imx6qdl-microsom.dtsi"
#include "imx6qdl-microsom-ar8035.dtsi"
/ {
chosen {
stdout-path = &uart1;
};
ir_recv: ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio3 5 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>;
};
regulators {
compatible = "simple-bus";
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usbh1_vbus: usb-h1-vbus {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 0 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usbotg_vbus: usb-otg-vbus {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 22 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "On-board SPDIF";
/* IMX6 doesn't implement this yet */
spdif-controller = <&spdif>;
spdif-out;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
status = "okay";
};
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
/*
* Not fitted on Carrier-1 board... yet
status = "okay";
rtc: pcf8523@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};
*/
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
status = "okay";
};
&iomuxc {
hummingboard {
pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
fsl,pins = <
MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
>;
};
pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 {
fsl,pins = <
MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1
>;
};
pinctrl_hummingboard_hdmi: hummingboard-hdmi {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
>;
};
pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_hummingboard_spdif: hummingboard-spdif {
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
};
pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
};
pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
/*
* Similar to pinctrl_usbotg_2, but we want it
* pulled down for a fixed host connection.
*/
fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
};
pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
};
pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
fsl,pins = <
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
>;
};
pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
>;
};
};
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_spdif>;
status = "okay";
};
&usbh1 {
disable-over-current;
vbus-supply = <&reg_usbh1_vbus>;
status = "okay";
};
&usbotg {
disable-over-current;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
vbus-supply = <&reg_usbotg_vbus>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <
&pinctrl_hummingboard_usdhc2_aux
&pinctrl_hummingboard_usdhc2
>;
vmmc-supply = <&reg_3p3v>;
cd-gpios = <&gpio1 4 0>;
status = "okay";
};
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
View file @ 9cd70164
...@@ -174,6 +174,11 @@ &fec { ...@@ -174,6 +174,11 @@ &fec {
status = "okay"; status = "okay";
}; };
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 { &i2c1 {
clock-frequency = <100000>; clock-frequency = <100000>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -187,6 +192,25 @@ codec: sgtl5000@0a { ...@@ -187,6 +192,25 @@ codec: sgtl5000@0a {
VDDA-supply = <&reg_2p5v>; VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>; VDDIO-supply = <&reg_3p3v>;
}; };
rtc: rtc@6f {
compatible = "isil,isl1208";
reg = <0x6f>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
}; };
&iomuxc { &iomuxc {
...@@ -266,6 +290,20 @@ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 ...@@ -266,6 +290,20 @@ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>; >;
}; };
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pwm1: pwm1grp { pinctrl_pwm1: pwm1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
......
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
View file @ 9cd70164
...@@ -83,7 +83,7 @@ eeprom@50 { ...@@ -83,7 +83,7 @@ eeprom@50 {
}; };
pmic@58 { pmic@58 {
compatible = "dialog,da9063"; compatible = "dlg,da9063";
reg = <0x58>; reg = <0x58>;
interrupt-parent = <&gpio4>; interrupt-parent = <&gpio4>;
interrupts = <17 0x8>; /* active-low GPIO4_17 */ interrupts = <17 0x8>; /* active-low GPIO4_17 */
......
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
View file @ 9cd70164
...@@ -54,6 +54,19 @@ reg_audio: regulator@2 { ...@@ -54,6 +54,19 @@ reg_audio: regulator@2 {
gpio = <&gpio4 10 0>; gpio = <&gpio4 10 0>;
enable-active-high; enable-active-high;
}; };
reg_pcie: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_reg>;
regulator-name = "MPCIE_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 19 0>;
regulator-always-on;
enable-active-high;
};
}; };
gpio-keys { gpio-keys {
...@@ -314,15 +327,15 @@ &iomuxc { ...@@ -314,15 +327,15 @@ &iomuxc {
imx6qdl-sabresd { imx6qdl-sabresd {
pinctrl_hog: hoggrp { pinctrl_hog: hoggrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
>; >;
}; };
...@@ -367,9 +380,9 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 ...@@ -367,9 +380,9 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
pinctrl_gpio_keys: gpio_keysgrp { pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
>; >;
}; };
...@@ -396,7 +409,13 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 ...@@ -396,7 +409,13 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
pinctrl_pcie: pciegrp { pinctrl_pcie: pciegrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
>;
};
pinctrl_pcie_reg: pciereggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
>; >;
}; };
...@@ -468,7 +487,7 @@ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 ...@@ -468,7 +487,7 @@ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
gpio_leds { gpio_leds {
pinctrl_gpio_leds: gpioledsgrp { pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
>; >;
}; };
}; };
......
arch/arm/boot/dts/imx6qdl.dtsi
View file @ 9cd70164
...@@ -137,7 +137,9 @@ L2: l2-cache@00a02000 { ...@@ -137,7 +137,9 @@ L2: l2-cache@00a02000 {
pcie: pcie@0x01000000 { pcie: pcie@0x01000000 {
compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
reg = <0x01ffc000 0x4000>; /* DBI */ reg = <0x01ffc000 0x04000>,
<0x01f00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
device_type = "pci"; device_type = "pci";
...@@ -273,11 +275,14 @@ esai: esai@02024000 { ...@@ -273,11 +275,14 @@ esai: esai@02024000 {
}; };
ssi1: ssi@02028000 { ssi1: ssi@02028000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6q-ssi", compatible = "fsl,imx6q-ssi",
"fsl,imx51-ssi"; "fsl,imx51-ssi";
reg = <0x02028000 0x4000>; reg = <0x02028000 0x4000>;
interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_SSI1_IPG>; clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
<&clks IMX6QDL_CLK_SSI1>;
clock-names = "ipg", "baud";
dmas = <&sdma 37 1 0>, dmas = <&sdma 37 1 0>,
<&sdma 38 1 0>; <&sdma 38 1 0>;
dma-names = "rx", "tx"; dma-names = "rx", "tx";
...@@ -286,11 +291,14 @@ ssi1: ssi@02028000 { ...@@ -286,11 +291,14 @@ ssi1: ssi@02028000 {
}; };
ssi2: ssi@0202c000 { ssi2: ssi@0202c000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6q-ssi", compatible = "fsl,imx6q-ssi",
"fsl,imx51-ssi"; "fsl,imx51-ssi";
reg = <0x0202c000 0x4000>; reg = <0x0202c000 0x4000>;
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_SSI2_IPG>; clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
<&clks IMX6QDL_CLK_SSI2>;
clock-names = "ipg", "baud";
dmas = <&sdma 41 1 0>, dmas = <&sdma 41 1 0>,
<&sdma 42 1 0>; <&sdma 42 1 0>;
dma-names = "rx", "tx"; dma-names = "rx", "tx";
...@@ -299,11 +307,14 @@ ssi2: ssi@0202c000 { ...@@ -299,11 +307,14 @@ ssi2: ssi@0202c000 {
}; };
ssi3: ssi@02030000 { ssi3: ssi@02030000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6q-ssi", compatible = "fsl,imx6q-ssi",
"fsl,imx51-ssi"; "fsl,imx51-ssi";
reg = <0x02030000 0x4000>; reg = <0x02030000 0x4000>;
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_SSI3_IPG>; clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
<&clks IMX6QDL_CLK_SSI3>;
clock-names = "ipg", "baud";
dmas = <&sdma 45 1 0>, dmas = <&sdma 45 1 0>,
<&sdma 46 1 0>; <&sdma 46 1 0>;
dma-names = "rx", "tx"; dma-names = "rx", "tx";
...@@ -396,8 +407,9 @@ gpt: gpt@02098000 { ...@@ -396,8 +407,9 @@ gpt: gpt@02098000 {
reg = <0x02098000 0x4000>; reg = <0x02098000 0x4000>;
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_GPT_IPG>, clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
<&clks IMX6QDL_CLK_GPT_IPG_PER>; <&clks IMX6QDL_CLK_GPT_IPG_PER>,
clock-names = "ipg", "per"; <&clks IMX6QDL_CLK_GPT_3M>;
clock-names = "ipg", "per", "osc_per";
}; };
gpio1: gpio@0209c000 { gpio1: gpio@0209c000 {
......
arch/arm/boot/dts/imx6sl-evk.dts
View file @ 9cd70164
...@@ -20,6 +20,13 @@ memory { ...@@ -20,6 +20,13 @@ memory {
reg = <0x80000000 0x40000000>; reg = <0x80000000 0x40000000>;
}; };
backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -74,6 +81,14 @@ reg_aud4v: regulator@3 { ...@@ -74,6 +81,14 @@ reg_aud4v: regulator@3 {
regulator-max-microvolt = <4325000>; regulator-max-microvolt = <4325000>;
regulator-boot-on; regulator-boot-on;
}; };
reg_lcd_3v3: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "lcd-3v3";
gpio = <&gpio4 3 0>;
enable-active-high;
};
}; };
sound { sound {
...@@ -329,12 +344,6 @@ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1 ...@@ -329,12 +344,6 @@ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
>; >;
}; };
pinctrl_led: ledgrp {
fsl,pins = <
MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
>;
};
pinctrl_kpp: kppgrp { pinctrl_kpp: kppgrp {
fsl,pins = < fsl,pins = <
MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
...@@ -346,6 +355,51 @@ MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0 ...@@ -346,6 +355,51 @@ MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0
>; >;
}; };
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
>;
};
pinctrl_pwm1: pwmgrp {
fsl,pins = <
MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
>;
};
pinctrl_uart1: uart1grp { pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
...@@ -488,6 +542,44 @@ MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */ ...@@ -488,6 +542,44 @@ MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */
status = "okay"; status = "okay";
}; };
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33500000>;
hactive = <800>;
vactive = <480>;
hback-porch = <89>;
hfront-porch = <164>;
vback-porch = <23>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&ssi2 { &ssi2 {
status = "okay"; status = "okay";
}; };
......
arch/arm/boot/dts/imx6sl.dtsi
View file @ 9cd70164
...@@ -226,11 +226,14 @@ uart2: serial@02024000 { ...@@ -226,11 +226,14 @@ uart2: serial@02024000 {
}; };
ssi1: ssi@02028000 { ssi1: ssi@02028000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sl-ssi", compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi"; "fsl,imx51-ssi";
reg = <0x02028000 0x4000>; reg = <0x02028000 0x4000>;
interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SSI1>; clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
<&clks IMX6SL_CLK_SSI1>;
clock-names = "ipg", "baud";
dmas = <&sdma 37 1 0>, dmas = <&sdma 37 1 0>,
<&sdma 38 1 0>; <&sdma 38 1 0>;
dma-names = "rx", "tx"; dma-names = "rx", "tx";
...@@ -239,11 +242,14 @@ ssi1: ssi@02028000 { ...@@ -239,11 +242,14 @@ ssi1: ssi@02028000 {
}; };
ssi2: ssi@0202c000 { ssi2: ssi@0202c000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sl-ssi", compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi"; "fsl,imx51-ssi";
reg = <0x0202c000 0x4000>; reg = <0x0202c000 0x4000>;
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SSI2>; clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
<&clks IMX6SL_CLK_SSI2>;
clock-names = "ipg", "baud";
dmas = <&sdma 41 1 0>, dmas = <&sdma 41 1 0>,
<&sdma 42 1 0>; <&sdma 42 1 0>;
dma-names = "rx", "tx"; dma-names = "rx", "tx";
...@@ -252,11 +258,14 @@ ssi2: ssi@0202c000 { ...@@ -252,11 +258,14 @@ ssi2: ssi@0202c000 {
}; };
ssi3: ssi@02030000 { ssi3: ssi@02030000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sl-ssi", compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi"; "fsl,imx51-ssi";
reg = <0x02030000 0x4000>; reg = <0x02030000 0x4000>;
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SSI3>; clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
<&clks IMX6SL_CLK_SSI3>;
clock-names = "ipg", "baud";
dmas = <&sdma 45 1 0>, dmas = <&sdma 45 1 0>,
<&sdma 46 1 0>; <&sdma 46 1 0>;
dma-names = "rx", "tx"; dma-names = "rx", "tx";
...@@ -529,6 +538,14 @@ reg_soc: regulator-vddsoc@140 { ...@@ -529,6 +538,14 @@ reg_soc: regulator-vddsoc@140 {
}; };
}; };
tempmon: tempmon {
compatible = "fsl,imx6q-tempmon";
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
fsl,tempmon-data = <&ocotp>;
clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
};
usbphy1: usbphy@020c9000 { usbphy1: usbphy@020c9000 {
compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>; reg = <0x020c9000 0x1000>;
...@@ -627,8 +644,14 @@ epdc: epdc@020f4000 { ...@@ -627,8 +644,14 @@ epdc: epdc@020f4000 {
}; };
lcdif: lcdif@020f8000 { lcdif: lcdif@020f8000 {
compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
reg = <0x020f8000 0x4000>; reg = <0x020f8000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
<&clks IMX6SL_CLK_LCDIF_AXI>,
<&clks IMX6SL_CLK_DUMMY>;
clock-names = "pix", "axi", "disp_axi";
status = "disabled";
}; };
dcp: dcp@020fc000 { dcp: dcp@020fc000 {
...@@ -784,7 +807,7 @@ weim: weim@021b8000 { ...@@ -784,7 +807,7 @@ weim: weim@021b8000 {
}; };
ocotp: ocotp@021bc000 { ocotp: ocotp@021bc000 {
compatible = "fsl,imx6sl-ocotp"; compatible = "fsl,imx6sl-ocotp", "syscon";
reg = <0x021bc000 0x4000>; reg = <0x021bc000 0x4000>;
}; };
......
arch/arm/boot/dts/imx6sx-sdb.dts
View file @ 9cd70164
...@@ -24,6 +24,13 @@ memory { ...@@ -24,6 +24,13 @@ memory {
reg = <0x80000000 0x40000000>; reg = <0x80000000 0x40000000>;
}; };
backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
gpio-keys { gpio-keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -90,6 +97,14 @@ reg_psu_5v: regulator@3 { ...@@ -90,6 +97,14 @@ reg_psu_5v: regulator@3 {
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
}; };
reg_lcd_3v3: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "lcd-3v3";
gpio = <&gpio3 27 0>;
enable-active-high;
};
}; };
sound { sound {
...@@ -251,6 +266,44 @@ codec: wm8962@1a { ...@@ -251,6 +266,44 @@ codec: wm8962@1a {
}; };
}; };
&lcdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33500000>;
hactive = <800>;
vactive = <480>;
hback-porch = <89>;
hfront-porch = <164>;
vback-porch = <23>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&ssi2 { &ssi2 {
status = "okay"; status = "okay";
}; };
...@@ -365,6 +418,46 @@ MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 ...@@ -365,6 +418,46 @@ MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
>; >;
}; };
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
>;
};
pinctrl_pwm3: pwm3grp-1 {
fsl,pins = <
MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
>;
};
pinctrl_vcc_sd3: vccsd3grp { pinctrl_vcc_sd3: vccsd3grp {
fsl,pins = < fsl,pins = <
MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
......
arch/arm/boot/dts/imx6sx.dtsi
View file @ 9cd70164
...@@ -298,6 +298,7 @@ esai: esai@02024000 { ...@@ -298,6 +298,7 @@ esai: esai@02024000 {
}; };
ssi1: ssi@02028000 { ssi1: ssi@02028000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
reg = <0x02028000 0x4000>; reg = <0x02028000 0x4000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
...@@ -311,6 +312,7 @@ ssi1: ssi@02028000 { ...@@ -311,6 +312,7 @@ ssi1: ssi@02028000 {
}; };
ssi2: ssi@0202c000 { ssi2: ssi@0202c000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
reg = <0x0202c000 0x4000>; reg = <0x0202c000 0x4000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
...@@ -324,6 +326,7 @@ ssi2: ssi@0202c000 { ...@@ -324,6 +326,7 @@ ssi2: ssi@0202c000 {
}; };
ssi3: ssi@02030000 { ssi3: ssi@02030000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
reg = <0x02030000 0x4000>; reg = <0x02030000 0x4000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
...@@ -418,7 +421,7 @@ gpt: gpt@02098000 { ...@@ -418,7 +421,7 @@ gpt: gpt@02098000 {
reg = <0x02098000 0x4000>; reg = <0x02098000 0x4000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_GPT_BUS>, clocks = <&clks IMX6SX_CLK_GPT_BUS>,
<&clks IMX6SX_CLK_GPT_SERIAL>; <&clks IMX6SX_CLK_GPT_3M>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
}; };
...@@ -1062,6 +1065,7 @@ csi2: csi@0221c000 { ...@@ -1062,6 +1065,7 @@ csi2: csi@0221c000 {
}; };
lcdif1: lcdif@02220000 { lcdif1: lcdif@02220000 {
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
reg = <0x02220000 0x4000>; reg = <0x02220000 0x4000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
...@@ -1072,6 +1076,7 @@ lcdif1: lcdif@02220000 { ...@@ -1072,6 +1076,7 @@ lcdif1: lcdif@02220000 {
}; };
lcdif2: lcdif@02224000 { lcdif2: lcdif@02224000 {
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
reg = <0x02224000 0x4000>; reg = <0x02224000 0x4000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
......
arch/arm/boot/dts/r8a7790-lager.dts
View file @ 9cd70164
...@@ -392,7 +392,7 @@ &iic3 { ...@@ -392,7 +392,7 @@ &iic3 {
status = "okay"; status = "okay";
vdd_dvfs: regulator@68 { vdd_dvfs: regulator@68 {
compatible = "diasemi,da9210"; compatible = "dlg,da9210";
reg = <0x68>; reg = <0x68>;
regulator-min-microvolt = <1000000>; regulator-min-microvolt = <1000000>;
......
arch/arm/boot/dts/r8a7791-koelsch.dts
View file @ 9cd70164
...@@ -437,7 +437,7 @@ &i2c6 { ...@@ -437,7 +437,7 @@ &i2c6 {
clock-frequency = <100000>; clock-frequency = <100000>;
vdd_dvfs: regulator@68 { vdd_dvfs: regulator@68 {
compatible = "diasemi,da9210"; compatible = "dlg,da9210";
reg = <0x68>; reg = <0x68>;
regulator-min-microvolt = <1000000>; regulator-min-microvolt = <1000000>;
......
arch/arm/boot/dts/vf610-colibri-eval-v3.dts 0 → 100644
View file @ 9cd70164
/*
* Copyright 2014 Toradex AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
/dts-v1/;
#include "vf610-colibri.dtsi"
/ {
model = "Toradex Colibri VF61 on Colibri Evaluation Board";
compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610";
chosen {
bootargs = "console=ttyLP0,115200";
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
bus-width = <4>;
status = "okay";
};
&fec1 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
arch/arm/boot/dts/vf610-colibri.dts → arch/arm/boot/dts/vf610-colibri.dtsi
View file @ 9cd70164
...@@ -7,16 +7,11 @@ ...@@ -7,16 +7,11 @@
* (at your option) any later version. * (at your option) any later version.
*/ */
/dts-v1/;
#include "vf610.dtsi" #include "vf610.dtsi"
/ { / {
model = "Toradex Colibri VF61 COM"; model = "Toradex Colibri VF61 COM";
compatible = "toradex,vf610-colibri", "fsl,vf610"; compatible = "toradex,vf610-colibri_vf61", "fsl,vf610";
chosen {
bootargs = "console=ttyLP0,115200";
};
memory { memory {
reg = <0x80000000 0x10000000>; reg = <0x80000000 0x10000000>;
...@@ -36,14 +31,12 @@ &esdhc1 { ...@@ -36,14 +31,12 @@ &esdhc1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>; pinctrl-0 = <&pinctrl_esdhc1>;
bus-width = <4>; bus-width = <4>;
status = "okay";
}; };
&fec1 { &fec1 {
phy-mode = "rmii"; phy-mode = "rmii";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>; pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
}; };
&L2 { &L2 {
...@@ -54,25 +47,32 @@ &L2 { ...@@ -54,25 +47,32 @@ &L2 {
&uart0 { &uart0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>; pinctrl-0 = <&pinctrl_uart0>;
status = "okay";
}; };
&uart1 { &uart1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>; pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
}; };
&uart2 { &uart2 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>; pinctrl-0 = <&pinctrl_uart2>;
};
&usbdev0 {
disable-over-current;
status = "okay";
};
&usbh1 {
disable-over-current;
status = "okay"; status = "okay";
}; };
&iomuxc { &iomuxc {
vf610-colibri { vf610-colibri {
pinctrl_esdhc1: esdhc1grp { pinctrl_esdhc1: esdhc1grp {
fsl,fsl,pins = < fsl,pins = <
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
VF610_PAD_PTA25__ESDHC1_CMD 0x31ef VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
......
arch/arm/boot/dts/vf610-twr.dts
View file @ 9cd70164
...@@ -76,7 +76,6 @@ sound { ...@@ -76,7 +76,6 @@ sound {
simple-audio-card,cpu { simple-audio-card,cpu {
sound-dai = <&sai2>; sound-dai = <&sai2>;
master-clkdir-out;
frame-master; frame-master;
bitclock-master; bitclock-master;
}; };
...@@ -221,8 +220,6 @@ VF610_PAD_PTB0__FTM0_CH0 0x1582 ...@@ -221,8 +220,6 @@ VF610_PAD_PTB0__FTM0_CH0 0x1582
VF610_PAD_PTB1__FTM0_CH1 0x1582 VF610_PAD_PTB1__FTM0_CH1 0x1582
VF610_PAD_PTB2__FTM0_CH2 0x1582 VF610_PAD_PTB2__FTM0_CH2 0x1582
VF610_PAD_PTB3__FTM0_CH3 0x1582 VF610_PAD_PTB3__FTM0_CH3 0x1582
VF610_PAD_PTB6__FTM0_CH6 0x1582
VF610_PAD_PTB7__FTM0_CH7 0x1582
>; >;
}; };
...@@ -244,6 +241,13 @@ VF610_PAD_PTB4__UART1_TX 0x21a2 ...@@ -244,6 +241,13 @@ VF610_PAD_PTB4__UART1_TX 0x21a2
VF610_PAD_PTB5__UART1_RX 0x21a1 VF610_PAD_PTB5__UART1_RX 0x21a1
>; >;
}; };
pinctrl_uart2: uart2grp {
fsl,pins = <
VF610_PAD_PTB6__UART2_TX 0x21a2
VF610_PAD_PTB7__UART2_RX 0x21a1
>;
};
}; };
}; };
...@@ -265,3 +269,19 @@ &uart1 { ...@@ -265,3 +269,19 @@ &uart1 {
pinctrl-0 = <&pinctrl_uart1>; pinctrl-0 = <&pinctrl_uart1>;
status = "okay"; status = "okay";
}; };
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbdev0 {
disable-over-current;
status = "okay";
};
&usbh1 {
disable-over-current;
status = "okay";
};
arch/arm/boot/dts/vf610.dtsi
View file @ 9cd70164
...@@ -27,6 +27,8 @@ aliases { ...@@ -27,6 +27,8 @@ aliases {
gpio2 = &gpio3; gpio2 = &gpio3;
gpio3 = &gpio4; gpio3 = &gpio4;
gpio4 = &gpio5; gpio4 = &gpio5;
usbphy0 = &usbphy0;
usbphy1 = &usbphy1;
}; };
cpus { cpus {
...@@ -297,9 +299,25 @@ gpio5: gpio@4004d000 { ...@@ -297,9 +299,25 @@ gpio5: gpio@4004d000 {
gpio-ranges = <&iomuxc 0 128 7>; gpio-ranges = <&iomuxc 0 128 7>;
}; };
anatop@40050000 { anatop: anatop@40050000 {
compatible = "fsl,vf610-anatop"; compatible = "fsl,vf610-anatop", "syscon";
reg = <0x40050000 0x1000>; reg = <0x40050000 0x400>;
};
usbphy0: usbphy@40050800 {
compatible = "fsl,vf610-usbphy";
reg = <0x40050800 0x400>;
interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBPHY0>;
fsl,anatop = <&anatop>;
};
usbphy1: usbphy@40050c00 {
compatible = "fsl,vf610-usbphy";
reg = <0x40050c00 0x400>;
interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBPHY1>;
fsl,anatop = <&anatop>;
}; };
i2c0: i2c@40066000 { i2c0: i2c@40066000 {
...@@ -321,6 +339,24 @@ clks: ccm@4006b000 { ...@@ -321,6 +339,24 @@ clks: ccm@4006b000 {
reg = <0x4006b000 0x1000>; reg = <0x4006b000 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
}; };
usbdev0: usb@40034000 {
compatible = "fsl,vf610-usb", "fsl,imx27-usb";
reg = <0x40034000 0x800>;
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBC0>;
fsl,usbphy = <&usbphy0>;
fsl,usbmisc = <&usbmisc0 0>;
dr_mode = "peripheral";
status = "disabled";
};
usbmisc0: usb@40034800 {
#index-cells = <1>;
compatible = "fsl,vf610-usbmisc";
reg = <0x40034800 0x200>;
clocks = <&clks VF610_CLK_USBC0>;
};
}; };
aips1: aips-bus@40080000 { aips1: aips-bus@40080000 {
...@@ -383,6 +419,24 @@ esdhc1: esdhc@400b2000 { ...@@ -383,6 +419,24 @@ esdhc1: esdhc@400b2000 {
status = "disabled"; status = "disabled";
}; };
usbh1: usb@400b4000 {
compatible = "fsl,vf610-usb", "fsl,imx27-usb";
reg = <0x400b4000 0x800>;
interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBC1>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc1 0>;
dr_mode = "host";
status = "disabled";
};
usbmisc1: usb@400b4800 {
#index-cells = <1>;
compatible = "fsl,vf610-usbmisc";
reg = <0x400b4800 0x200>;
clocks = <&clks VF610_CLK_USBC1>;
};
ftm: ftm@400b8000 { ftm: ftm@400b8000 {
compatible = "fsl,ftm-timer"; compatible = "fsl,ftm-timer";
reg = <0x400b8000 0x1000 0x400b9000 0x1000>; reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
......
arch/arm/configs/imx_v4_v5_defconfig
View file @ 9cd70164
...@@ -21,8 +21,6 @@ CONFIG_ARCH_MULTI_V4T=y ...@@ -21,8 +21,6 @@ CONFIG_ARCH_MULTI_V4T=y
CONFIG_ARCH_MULTI_V5=y CONFIG_ARCH_MULTI_V5=y
# CONFIG_ARCH_MULTI_V7 is not set # CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_MXC=y CONFIG_ARCH_MXC=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_ARCH_MX1ADS=y
CONFIG_MACH_SCB9328=y CONFIG_MACH_SCB9328=y
CONFIG_MACH_APF9328=y CONFIG_MACH_APF9328=y
CONFIG_MACH_MX21ADS=y CONFIG_MACH_MX21ADS=y
...@@ -30,10 +28,6 @@ CONFIG_MACH_MX25_3DS=y ...@@ -30,10 +28,6 @@ CONFIG_MACH_MX25_3DS=y
CONFIG_MACH_EUKREA_CPUIMX25SD=y CONFIG_MACH_EUKREA_CPUIMX25SD=y
CONFIG_MACH_IMX25_DT=y CONFIG_MACH_IMX25_DT=y
CONFIG_MACH_MX27ADS=y CONFIG_MACH_MX27ADS=y
CONFIG_MACH_PCM038=y
CONFIG_MACH_CPUIMX27=y
CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
CONFIG_MACH_MX27_3DS=y CONFIG_MACH_MX27_3DS=y
CONFIG_MACH_IMX27_VISSTRIM_M10=y CONFIG_MACH_IMX27_VISSTRIM_M10=y
CONFIG_MACH_PCA100=y CONFIG_MACH_PCA100=y
...@@ -43,8 +37,6 @@ CONFIG_PREEMPT=y ...@@ -43,8 +37,6 @@ CONFIG_PREEMPT=y
CONFIG_AEABI=y CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_FPE_NWFPE=y
CONFIG_FPE_NWFPE_XP=y
CONFIG_PM_DEBUG=y CONFIG_PM_DEBUG=y
CONFIG_NET=y CONFIG_NET=y
CONFIG_PACKET=y CONFIG_PACKET=y
...@@ -63,6 +55,7 @@ CONFIG_NETFILTER=y ...@@ -63,6 +55,7 @@ CONFIG_NETFILTER=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_MOUNT=y
CONFIG_IMX_WEIM=y
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
...@@ -78,8 +71,8 @@ CONFIG_MTD_NAND_MXC=y ...@@ -78,8 +71,8 @@ CONFIG_MTD_NAND_MXC=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y CONFIG_EEPROM_AT25=y
CONFIG_ATA=y
CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_PATA_IMX=y CONFIG_PATA_IMX=y
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
CONFIG_CS89x0=y CONFIG_CS89x0=y
...@@ -102,10 +95,8 @@ CONFIG_SERIAL_8250=m ...@@ -102,10 +95,8 @@ CONFIG_SERIAL_8250=m
CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_IMX_CONSOLE=y
# CONFIG_HW_RANDOM is not set # CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y CONFIG_I2C_CHARDEV=y
CONFIG_I2C_IMX=y CONFIG_I2C_IMX=y
CONFIG_SPI=y
CONFIG_SPI_IMX=y CONFIG_SPI_IMX=y
CONFIG_SPI_SPIDEV=y CONFIG_SPI_SPIDEV=y
CONFIG_GPIO_SYSFS=y CONFIG_GPIO_SYSFS=y
...@@ -132,10 +123,7 @@ CONFIG_VIDEO_CODA=y ...@@ -132,10 +123,7 @@ CONFIG_VIDEO_CODA=y
CONFIG_SOC_CAMERA_OV2640=y CONFIG_SOC_CAMERA_OV2640=y
CONFIG_FB=y CONFIG_FB=y
CONFIG_FB_IMX=y CONFIG_FB_IMX=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_L4F00242T03=y CONFIG_LCD_L4F00242T03=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y CONFIG_LOGO=y
CONFIG_SOUND=y CONFIG_SOUND=y
......
arch/arm/configs/imx_v6_v7_defconfig
View file @ 9cd70164
...@@ -32,8 +32,8 @@ CONFIG_MACH_IMX35_DT=y ...@@ -32,8 +32,8 @@ CONFIG_MACH_IMX35_DT=y
CONFIG_MACH_PCM043=y CONFIG_MACH_PCM043=y
CONFIG_MACH_MX35_3DS=y CONFIG_MACH_MX35_3DS=y
CONFIG_MACH_VPR200=y CONFIG_MACH_VPR200=y
CONFIG_SOC_IMX51=y
CONFIG_SOC_IMX50=y CONFIG_SOC_IMX50=y
CONFIG_SOC_IMX51=y
CONFIG_SOC_IMX53=y CONFIG_SOC_IMX53=y
CONFIG_SOC_IMX6Q=y CONFIG_SOC_IMX6Q=y
CONFIG_SOC_IMX6SL=y CONFIG_SOC_IMX6SL=y
...@@ -105,7 +105,6 @@ CONFIG_EEPROM_AT24=y ...@@ -105,7 +105,6 @@ CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y CONFIG_EEPROM_AT25=y
# CONFIG_SCSI_PROC_FS is not set # CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y CONFIG_SCSI_SCAN_ASYNC=y
...@@ -153,14 +152,12 @@ CONFIG_SERIAL_IMX_CONSOLE=y ...@@ -153,14 +152,12 @@ CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_SERIAL_FSL_LPUART=y CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MXC_RNGA=y
# CONFIG_I2C_COMPAT is not set # CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y CONFIG_I2C_CHARDEV=y
# CONFIG_I2C_HELPER_AUTO is not set # CONFIG_I2C_HELPER_AUTO is not set
CONFIG_I2C_ALGOPCF=m CONFIG_I2C_ALGOPCF=m
CONFIG_I2C_ALGOPCA=m CONFIG_I2C_ALGOPCA=m
CONFIG_I2C_IMX=y CONFIG_I2C_IMX=y
CONFIG_SPI=y
CONFIG_SPI_IMX=y CONFIG_SPI_IMX=y
CONFIG_GPIO_SYSFS=y CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_MC9S08DZ60=y CONFIG_GPIO_MC9S08DZ60=y
...@@ -198,7 +195,6 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y ...@@ -198,7 +195,6 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_L4F00242T03=y CONFIG_LCD_L4F00242T03=y
CONFIG_LCD_PLATFORM=y CONFIG_LCD_PLATFORM=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_GPIO=y CONFIG_BACKLIGHT_GPIO=y
CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y
...@@ -206,6 +202,7 @@ CONFIG_LOGO=y ...@@ -206,6 +202,7 @@ CONFIG_LOGO=y
CONFIG_SOUND=y CONFIG_SOUND=y
CONFIG_SND=y CONFIG_SND=y
CONFIG_SND_SOC=y CONFIG_SND_SOC=y
CONFIG_SND_SOC_FSL_SAI=y
CONFIG_SND_IMX_SOC=y CONFIG_SND_IMX_SOC=y
CONFIG_SND_SOC_PHYCORE_AC97=y CONFIG_SND_SOC_PHYCORE_AC97=y
CONFIG_SND_SOC_EUKREA_TLV320=y CONFIG_SND_SOC_EUKREA_TLV320=y
...@@ -213,6 +210,7 @@ CONFIG_SND_SOC_IMX_WM8962=y ...@@ -213,6 +210,7 @@ CONFIG_SND_SOC_IMX_WM8962=y
CONFIG_SND_SOC_IMX_SGTL5000=y CONFIG_SND_SOC_IMX_SGTL5000=y
CONFIG_SND_SOC_IMX_SPDIF=y CONFIG_SND_SOC_IMX_SPDIF=y
CONFIG_SND_SOC_IMX_MC13783=y CONFIG_SND_SOC_IMX_MC13783=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y CONFIG_USB_EHCI_MXC=y
...@@ -240,6 +238,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=y ...@@ -240,6 +238,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y
CONFIG_RTC_DRV_ISL1208=y
CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MC13XXX=y
CONFIG_RTC_DRV_MXC=y CONFIG_RTC_DRV_MXC=y
...@@ -254,7 +253,6 @@ CONFIG_DRM_IMX_FB_HELPER=y ...@@ -254,7 +253,6 @@ CONFIG_DRM_IMX_FB_HELPER=y
CONFIG_DRM_IMX_PARALLEL_DISPLAY=y CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
CONFIG_DRM_IMX_TVE=y CONFIG_DRM_IMX_TVE=y
CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_LDB=y
CONFIG_DRM_IMX_IPUV3_CORE=y
CONFIG_DRM_IMX_IPUV3=y CONFIG_DRM_IMX_IPUV3=y
CONFIG_DRM_IMX_HDMI=y CONFIG_DRM_IMX_HDMI=y
# CONFIG_IOMMU_SUPPORT is not set # CONFIG_IOMMU_SUPPORT is not set
......
arch/arm/mach-imx/Kconfig
View file @ 9cd70164
...@@ -69,6 +69,7 @@ config SOC_IMX1 ...@@ -69,6 +69,7 @@ config SOC_IMX1
select CPU_ARM920T select CPU_ARM920T
select IMX_HAVE_IOMUX_V1 select IMX_HAVE_IOMUX_V1
select MXC_AVIC select MXC_AVIC
select PINCTRL_IMX1
config SOC_IMX21 config SOC_IMX21
bool bool
...@@ -108,17 +109,6 @@ config SOC_IMX35 ...@@ -108,17 +109,6 @@ config SOC_IMX35
if ARCH_MULTI_V4T if ARCH_MULTI_V4T
comment "MX1 platforms:" comment "MX1 platforms:"
config MACH_MXLADS
bool
config ARCH_MX1ADS
bool "MX1ADS platform"
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select MACH_MXLADS
select SOC_IMX1
help
Say Y here if you are using Motorola MX1ADS/MXLADS boards
config MACH_SCB9328 config MACH_SCB9328
bool "Synertronixx scb9328" bool "Synertronixx scb9328"
...@@ -135,6 +125,13 @@ config MACH_APF9328 ...@@ -135,6 +125,13 @@ config MACH_APF9328
help help
Say Yes here if you are using the Armadeus APF9328 development board Say Yes here if you are using the Armadeus APF9328 development board
config MACH_IMX1_DT
bool "Support i.MX1 platforms from device tree"
select SOC_IMX1
help
Include support for Freescale i.MX1 based platforms
using the device tree for discovery.
endif endif
if ARCH_MULTI_V5 if ARCH_MULTI_V5
...@@ -223,86 +220,6 @@ config MACH_MX27ADS ...@@ -223,86 +220,6 @@ config MACH_MX27ADS
Include support for MX27ADS platform. This includes specific Include support for MX27ADS platform. This includes specific
configurations for the board and its peripherals. configurations for the board and its peripherals.
config MACH_PCM038
bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select IMX_HAVE_PLATFORM_SPI_IMX
select USB_ULPI_VIEWPORT if USB_ULPI
select SOC_IMX27
help
Include support for phyCORE-i.MX27 (aka pcm038) platform. This
includes specific configurations for the module and its peripherals.
choice
prompt "Baseboard"
depends on MACH_PCM038
default MACH_PCM970_BASEBOARD
config MACH_PCM970_BASEBOARD
bool "PHYTEC PCM970 development board"
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_MXC_MMC
help
This adds board specific devices that can be found on Phytec's
PCM970 evaluation board.
endchoice
config MACH_CPUIMX27
bool "Eukrea CPUIMX27 module"
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select USB_ULPI_VIEWPORT if USB_ULPI
select SOC_IMX27
help
Include support for Eukrea CPUIMX27 platform. This includes
specific configurations for the module and its peripherals.
config MACH_EUKREA_CPUIMX27_USESDHC2
bool "CPUIMX27 integrates SDHC2 module"
depends on MACH_CPUIMX27
select IMX_HAVE_PLATFORM_MXC_MMC
help
This adds support for the internal SDHC2 used on CPUIMX27
for wifi or eMMC.
config MACH_EUKREA_CPUIMX27_USEUART4
bool "CPUIMX27 integrates UART4 module"
depends on MACH_CPUIMX27
help
This adds support for the internal UART4 used on CPUIMX27
for bluetooth.
choice
prompt "Baseboard"
depends on MACH_CPUIMX27
default MACH_EUKREA_MBIMX27_BASEBOARD
config MACH_EUKREA_MBIMX27_BASEBOARD
bool "Eukrea MBIMX27 development board"
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select LEDS_GPIO_REGISTER
help
This adds board specific devices that can be found on Eukrea's
MBIMX27 evaluation board.
endchoice
config MACH_MX27_3DS config MACH_MX27_3DS
bool "MX27PDK platform" bool "MX27PDK platform"
select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_FSL_USB2_UDC
...@@ -359,18 +276,6 @@ config MACH_PCA100 ...@@ -359,18 +276,6 @@ config MACH_PCA100
Include support for phyCARD-s (aka pca100) platform. This Include support for phyCARD-s (aka pca100) platform. This
includes specific configurations for the module and its peripherals. includes specific configurations for the module and its peripherals.
config MACH_MXT_TD60
bool "Maxtrack i-MXT TD60"
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select SOC_IMX27
help
Include support for i-MXT (aka td60) platform. This
includes specific configurations for the module and its peripherals.
config MACH_IMX27_DT config MACH_IMX27_DT
bool "Support i.MX27 platforms from device tree" bool "Support i.MX27 platforms from device tree"
select SOC_IMX27 select SOC_IMX27
......
arch/arm/mach-imx/Makefile
View file @ 9cd70164
...@@ -16,7 +16,8 @@ obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y) ...@@ -16,7 +16,8 @@ obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y)
obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
clk-pfd.o clk-busy.o clk.o \ clk-pfd.o clk-busy.o clk.o \
clk-fixup-div.o clk-fixup-mux.o clk-fixup-div.o clk-fixup-mux.o \
clk-gate-exclusive.o
obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
...@@ -41,9 +42,9 @@ obj-y += ssi-fiq-ksym.o ...@@ -41,9 +42,9 @@ obj-y += ssi-fiq-ksym.o
endif endif
# i.MX1 based machines # i.MX1 based machines
obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o
obj-$(CONFIG_MACH_IMX1_DT) += imx1-dt.o
# i.MX21 based machines # i.MX21 based machines
obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
...@@ -56,14 +57,9 @@ obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o ...@@ -56,14 +57,9 @@ obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o
# i.MX27 based machines # i.MX27 based machines
obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
obj-$(CONFIG_MACH_PCA100) += mach-pca100.o obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
# i.MX31 based machines # i.MX31 based machines
......
arch/arm/mach-imx/anatop.c
View file @ 9cd70164
...@@ -104,6 +104,19 @@ void __init imx_init_revision_from_anatop(void) ...@@ -104,6 +104,19 @@ void __init imx_init_revision_from_anatop(void)
case 2: case 2:
revision = IMX_CHIP_REVISION_1_2; revision = IMX_CHIP_REVISION_1_2;
break; break;
case 3:
revision = IMX_CHIP_REVISION_1_3;
break;
case 4:
revision = IMX_CHIP_REVISION_1_4;
break;
case 5:
/*
* i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked
* as 'D' in Part Number last character.
*/
revision = IMX_CHIP_REVISION_1_5;
break;
default: default:
revision = IMX_CHIP_REVISION_UNKNOWN; revision = IMX_CHIP_REVISION_UNKNOWN;
} }
......
arch/arm/mach-imx/board-pcm038.h deleted 100644 → 0
View file @ 7e9b2828
/*
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
#define __ASM_ARCH_MXC_BOARD_PCM038_H__
#ifndef __ASSEMBLY__
/*
* This CPU module needs a baseboard to work. After basic initializing
* its own devices, it calls the baseboard's init function.
* TODO: Add your own baseboard init function and call it from
* inside pcm038_init().
*
* This example here is for the development board. Refer pcm970-baseboard.c
*/
extern void pcm970_baseboard_init(void);
#endif
#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */
arch/arm/mach-imx/clk-gate-exclusive.c 0 → 100644
View file @ 9cd70164
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/slab.h>
#include "clk.h"
/**
* struct clk_gate_exclusive - i.MX specific gate clock which is mutually
* exclusive with other gate clocks
*
* @gate: the parent class
* @exclusive_mask: mask of gate bits which are mutually exclusive to this
* gate clock
*
* The imx exclusive gate clock is a subclass of basic clk_gate
* with an addtional mask to indicate which other gate bits in the same
* register is mutually exclusive to this gate clock.
*/
struct clk_gate_exclusive {
struct clk_gate gate;
u32 exclusive_mask;
};
static int clk_gate_exclusive_enable(struct clk_hw *hw)
{
struct clk_gate *gate = container_of(hw, struct clk_gate, hw);
struct clk_gate_exclusive *exgate = container_of(gate,
struct clk_gate_exclusive, gate);
u32 val = readl(gate->reg);
if (val & exgate->exclusive_mask)
return -EBUSY;
return clk_gate_ops.enable(hw);
}
static void clk_gate_exclusive_disable(struct clk_hw *hw)
{
clk_gate_ops.disable(hw);
}
static int clk_gate_exclusive_is_enabled(struct clk_hw *hw)
{
return clk_gate_ops.is_enabled(hw);
}
static const struct clk_ops clk_gate_exclusive_ops = {
.enable = clk_gate_exclusive_enable,
.disable = clk_gate_exclusive_disable,
.is_enabled = clk_gate_exclusive_is_enabled,
};
struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
void __iomem *reg, u8 shift, u32 exclusive_mask)
{
struct clk_gate_exclusive *exgate;
struct clk_gate *gate;
struct clk *clk;
struct clk_init_data init;
if (exclusive_mask == 0)
return ERR_PTR(-EINVAL);
exgate = kzalloc(sizeof(*exgate), GFP_KERNEL);
if (!exgate)
return ERR_PTR(-ENOMEM);
gate = &exgate->gate;
init.name = name;
init.ops = &clk_gate_exclusive_ops;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = parent ? &parent : NULL;
init.num_parents = parent ? 1 : 0;
gate->reg = reg;
gate->bit_idx = shift;
gate->lock = &imx_ccm_lock;
gate->hw.init = &init;
exgate->exclusive_mask = exclusive_mask;
clk = clk_register(NULL, &gate->hw);
if (IS_ERR(clk))
kfree(exgate);
return clk;
}
arch/arm/mach-imx/clk-imx6q.c
View file @ 9cd70164
...@@ -64,7 +64,7 @@ static const char *cko2_sels[] = { ...@@ -64,7 +64,7 @@ static const char *cko2_sels[] = {
"ipu2", "vdo_axi", "osc", "gpu2d_core", "ipu2", "vdo_axi", "osc", "gpu2d_core",
"gpu3d_core", "usdhc2", "ssi1", "ssi2", "gpu3d_core", "usdhc2", "ssi1", "ssi2",
"ssi3", "gpu3d_shader", "vpu_axi", "can_root", "ssi3", "gpu3d_shader", "vpu_axi", "can_root",
"ldb_di0", "ldb_di1", "esai", "eim_slow", "ldb_di0", "ldb_di1", "esai_extal", "eim_slow",
"uart_serial", "spdif", "asrc", "hsi_tx", "uart_serial", "spdif", "asrc", "hsi_tx",
}; };
static const char *cko_sels[] = { "cko1", "cko2", }; static const char *cko_sels[] = { "cko1", "cko2", };
...@@ -73,6 +73,14 @@ static const char *lvds_sels[] = { ...@@ -73,6 +73,14 @@ static const char *lvds_sels[] = {
"pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
"pcie_ref_125m", "sata_ref_100m", "pcie_ref_125m", "sata_ref_100m",
}; };
static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
static struct clk *clk[IMX6QDL_CLK_END]; static struct clk *clk[IMX6QDL_CLK_END];
static struct clk_onecell_data clk_data; static struct clk_onecell_data clk_data;
...@@ -107,6 +115,10 @@ static struct clk_div_table video_div_table[] = { ...@@ -107,6 +115,10 @@ static struct clk_div_table video_div_table[] = {
}; };
static unsigned int share_count_esai; static unsigned int share_count_esai;
static unsigned int share_count_asrc;
static unsigned int share_count_ssi1;
static unsigned int share_count_ssi2;
static unsigned int share_count_ssi3;
static void __init imx6q_clocks_init(struct device_node *ccm_node) static void __init imx6q_clocks_init(struct device_node *ccm_node)
{ {
...@@ -119,6 +131,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -119,6 +131,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0); clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
/* Clock source from external clock via CLK1/2 PADs */
clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0);
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
base = of_iomap(np, 0); base = of_iomap(np, 0);
...@@ -132,14 +147,47 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -132,14 +147,47 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
video_div_table[2].div = 1; video_div_table[2].div = 1;
}; };
/* type name parent_name base div_mask */ clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); clk[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); clk[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); clk[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); clk[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
/* type name parent_name base div_mask */
clk[IMX6QDL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
clk[IMX6QDL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
clk[IMX6QDL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
clk[IMX6QDL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
clk[IMX6QDL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
clk[IMX6QDL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
clk[IMX6QDL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
clk[IMX6QDL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
/* Do not bypass PLLs initially */
clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]);
clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]);
clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]);
clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]);
clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]);
clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]);
clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]);
clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
/* /*
* Bit 20 is the reserved and read-only bit, we do this only for: * Bit 20 is the reserved and read-only bit, we do this only for:
...@@ -176,8 +224,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -176,8 +224,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
* the "output_enable" bit as a gate, even though it's really just * the "output_enable" bit as a gate, even though it's really just
* enabling clock output. * enabling clock output.
*/ */
clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10); clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12));
clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11); clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13));
clk[IMX6QDL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
clk[IMX6QDL_CLK_LVDS2_IN] = imx_clk_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11));
/* name parent_name reg idx */ /* name parent_name reg idx */
clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
...@@ -194,6 +245,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -194,6 +245,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
if (cpu_is_imx6dl()) { if (cpu_is_imx6dl()) {
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
...@@ -317,7 +369,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -317,7 +369,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
/* name parent_name reg shift */ /* name parent_name reg shift */
clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc);
clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
...@@ -331,8 +385,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -331,8 +385,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
else else
clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
clk[IMX6QDL_CLK_ESAI] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai); clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_ESAI_AHB] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai); clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ipg", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
if (cpu_is_imx6dl()) if (cpu_is_imx6dl())
...@@ -388,9 +443,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -388,9 +443,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
clk[IMX6QDL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
clk[IMX6QDL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
clk[IMX6QDL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
...@@ -404,6 +462,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -404,6 +462,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
/*
* The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it
* to clock gpt_ipg_per to ease the gpt driver code.
*/
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER];
imx_check_clocks(clk, ARRAY_SIZE(clk)); imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_data.clks = clk; clk_data.clks = clk;
......
arch/arm/mach-imx/clk-imx6sl.c
View file @ 9cd70164
...@@ -43,11 +43,13 @@ static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", ...@@ -43,11 +43,13 @@ static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy",
static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", }; static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", };
static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
static const char *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; static const char *csi_sels[] = { "osc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
static const char *lcdif_axi_sels[] = { "pll2_bus", "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", };
static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", }; static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
static const char *perclk_sels[] = { "ipg", "osc", }; static const char *perclk_sels[] = { "ipg", "osc", };
static const char *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", }; static const char *pxp_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd3", };
static const char *epdc_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd2", };
static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
...@@ -55,6 +57,20 @@ static const char *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_d ...@@ -55,6 +57,20 @@ static const char *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_d
static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
static const char *ecspi_sels[] = { "pll3_60m", "osc", }; static const char *ecspi_sels[] = { "pll3_60m", "osc", };
static const char *uart_sels[] = { "pll3_80m", "osc", }; static const char *uart_sels[] = { "pll3_80m", "osc", };
static const char *lvds_sels[] = {
"pll1_sys", "pll2_bus", "pll2_pfd0", "pll2_pfd1", "pll2_pfd2", "dummy", "pll4_audio", "pll5_video",
"dummy", "enet_ref", "dummy", "dummy", "pll3_usb_otg", "pll7_usb_host", "pll3_pfd0", "pll3_pfd1",
"pll3_pfd2", "pll3_pfd3", "osc", "dummy", "dummy", "dummy", "dummy", "dummy",
"dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
};
static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
static struct clk_div_table clk_enet_ref_table[] = { static struct clk_div_table clk_enet_ref_table[] = {
{ .val = 0, .div = 20, }, { .val = 0, .div = 20, },
...@@ -79,6 +95,10 @@ static struct clk_div_table video_div_table[] = { ...@@ -79,6 +95,10 @@ static struct clk_div_table video_div_table[] = {
{ } { }
}; };
static unsigned int share_count_ssi1;
static unsigned int share_count_ssi2;
static unsigned int share_count_ssi3;
static struct clk *clks[IMX6SL_CLK_END]; static struct clk *clks[IMX6SL_CLK_END];
static struct clk_onecell_data clk_data; static struct clk_onecell_data clk_data;
static void __iomem *ccm_base; static void __iomem *ccm_base;
...@@ -175,20 +195,59 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) ...@@ -175,20 +195,59 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
/* Clock source from external clock via CLK1 PAD */
clks[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop"); np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
base = of_iomap(np, 0); base = of_iomap(np, 0);
WARN_ON(!base); WARN_ON(!base);
anatop_base = base; anatop_base = base;
/* type name parent base div_mask */ clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); clks[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); clks[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); clks[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); clks[IMX6SL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3);
/* type name parent_name base div_mask */
clks[IMX6SL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
clks[IMX6SL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
clks[IMX6SL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
clks[IMX6SL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
clks[IMX6SL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
clks[IMX6SL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
clks[IMX6SL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
clks[IMX6SL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
clks[IMX6SL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
clks[IMX6SL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
clks[IMX6SL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
clks[IMX6SL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
clks[IMX6SL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
clks[IMX6SL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
/* Do not bypass PLLs initially */
clk_set_parent(clks[IMX6SL_PLL1_BYPASS], clks[IMX6SL_CLK_PLL1]);
clk_set_parent(clks[IMX6SL_PLL2_BYPASS], clks[IMX6SL_CLK_PLL2]);
clk_set_parent(clks[IMX6SL_PLL3_BYPASS], clks[IMX6SL_CLK_PLL3]);
clk_set_parent(clks[IMX6SL_PLL4_BYPASS], clks[IMX6SL_CLK_PLL4]);
clk_set_parent(clks[IMX6SL_PLL5_BYPASS], clks[IMX6SL_CLK_PLL5]);
clk_set_parent(clks[IMX6SL_PLL6_BYPASS], clks[IMX6SL_CLK_PLL6]);
clk_set_parent(clks[IMX6SL_PLL7_BYPASS], clks[IMX6SL_CLK_PLL7]);
clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
clks[IMX6SL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
clks[IMX6SL_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
clks[IMX6SL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
/* /*
* usbphy1 and usbphy2 are implemented as dummy gates using reserve * usbphy1 and usbphy2 are implemented as dummy gates using reserve
...@@ -241,8 +300,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) ...@@ -241,8 +300,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels));
clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, lcdif_axi_sels, ARRAY_SIZE(lcdif_axi_sels));
clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
...@@ -251,8 +310,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) ...@@ -251,8 +310,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup); clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup);
clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, pxp_axi_sels, ARRAY_SIZE(pxp_axi_sels));
clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels));
clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels));
clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels)); clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels));
clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels)); clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels));
...@@ -337,9 +396,12 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) ...@@ -337,9 +396,12 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14); clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14);
clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18); clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20); clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
clks[IMX6SL_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22); clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
clks[IMX6SL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
clks[IMX6SL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
clks[IMX6SL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24); clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24);
clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26); clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26);
clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
...@@ -375,6 +437,13 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) ...@@ -375,6 +437,13 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
/* Audio-related clocks configuration */ /* Audio-related clocks configuration */
clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]); clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
/* set PLL5 video as lcdif pix parent clock */
clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL],
clks[IMX6SL_CLK_PLL2_PFD2]);
/* Set initial power mode */ /* Set initial power mode */
imx6q_set_lpm(WAIT_CLOCKED); imx6q_set_lpm(WAIT_CLOCKED);
} }
......
arch/arm/mach-imx/clk-imx6sx.c
View file @ 9cd70164
...@@ -81,6 +81,14 @@ static const char *lvds_sels[] = { ...@@ -81,6 +81,14 @@ static const char *lvds_sels[] = {
"arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div", "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
"dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2", "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2",
}; };
static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
static struct clk *clks[IMX6SX_CLK_CLK_END]; static struct clk *clks[IMX6SX_CLK_CLK_END];
static struct clk_onecell_data clk_data; static struct clk_onecell_data clk_data;
...@@ -143,18 +151,54 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) ...@@ -143,18 +151,54 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
/* Clock source from external clock via CLK1 PAD */
clks[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
base = of_iomap(np, 0); base = of_iomap(np, 0);
WARN_ON(!base); WARN_ON(!base);
/* type name parent_name base div_mask */ clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clks[IMX6SX_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); clks[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clks[IMX6SX_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); clks[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clks[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); clks[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clks[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); clks[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clks[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); clks[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clks[IMX6SX_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); clks[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clks[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3);
/* type name parent_name base div_mask */
clks[IMX6SX_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
clks[IMX6SX_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
clks[IMX6SX_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
clks[IMX6SX_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
clks[IMX6SX_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
clks[IMX6SX_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
clks[IMX6SX_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
clks[IMX6SX_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
clks[IMX6SX_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
clks[IMX6SX_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
clks[IMX6SX_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
clks[IMX6SX_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
clks[IMX6SX_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
clks[IMX6SX_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
/* Do not bypass PLLs initially */
clk_set_parent(clks[IMX6SX_PLL1_BYPASS], clks[IMX6SX_CLK_PLL1]);
clk_set_parent(clks[IMX6SX_PLL2_BYPASS], clks[IMX6SX_CLK_PLL2]);
clk_set_parent(clks[IMX6SX_PLL3_BYPASS], clks[IMX6SX_CLK_PLL3]);
clk_set_parent(clks[IMX6SX_PLL4_BYPASS], clks[IMX6SX_CLK_PLL4]);
clk_set_parent(clks[IMX6SX_PLL5_BYPASS], clks[IMX6SX_CLK_PLL5]);
clk_set_parent(clks[IMX6SX_PLL6_BYPASS], clks[IMX6SX_CLK_PLL6]);
clk_set_parent(clks[IMX6SX_PLL7_BYPASS], clks[IMX6SX_CLK_PLL7]);
clks[IMX6SX_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
clks[IMX6SX_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
clks[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
clks[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
clks[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
clks[IMX6SX_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
clks[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
/* /*
* Bit 20 is the reserved and read-only bit, we do this only for: * Bit 20 is the reserved and read-only bit, we do this only for:
...@@ -176,7 +220,8 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) ...@@ -176,7 +220,8 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5); clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5);
clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate("lvds1_out", "lvds1_sel", base + 0x160, 10); clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
clks[IMX6SX_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
base + 0xe0, 0, 2, 0, clk_enet_ref_table, base + 0xe0, 0, 2, 0, clk_enet_ref_table,
......
arch/arm/mach-imx/clk-pllv3.c
View file @ 9cd70164
...@@ -23,8 +23,6 @@ ...@@ -23,8 +23,6 @@
#define PLL_DENOM_OFFSET 0x20 #define PLL_DENOM_OFFSET 0x20
#define BM_PLL_POWER (0x1 << 12) #define BM_PLL_POWER (0x1 << 12)
#define BM_PLL_ENABLE (0x1 << 13)
#define BM_PLL_BYPASS (0x1 << 16)
#define BM_PLL_LOCK (0x1 << 31) #define BM_PLL_LOCK (0x1 << 31)
/** /**
...@@ -84,10 +82,6 @@ static int clk_pllv3_prepare(struct clk_hw *hw) ...@@ -84,10 +82,6 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
if (ret) if (ret)
return ret; return ret;
val = readl_relaxed(pll->base);
val &= ~BM_PLL_BYPASS;
writel_relaxed(val, pll->base);
return 0; return 0;
} }
...@@ -97,7 +91,6 @@ static void clk_pllv3_unprepare(struct clk_hw *hw) ...@@ -97,7 +91,6 @@ static void clk_pllv3_unprepare(struct clk_hw *hw)
u32 val; u32 val;
val = readl_relaxed(pll->base); val = readl_relaxed(pll->base);
val |= BM_PLL_BYPASS;
if (pll->powerup_set) if (pll->powerup_set)
val &= ~BM_PLL_POWER; val &= ~BM_PLL_POWER;
else else
...@@ -105,28 +98,6 @@ static void clk_pllv3_unprepare(struct clk_hw *hw) ...@@ -105,28 +98,6 @@ static void clk_pllv3_unprepare(struct clk_hw *hw)
writel_relaxed(val, pll->base); writel_relaxed(val, pll->base);
} }
static int clk_pllv3_enable(struct clk_hw *hw)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
u32 val;
val = readl_relaxed(pll->base);
val |= BM_PLL_ENABLE;
writel_relaxed(val, pll->base);
return 0;
}
static void clk_pllv3_disable(struct clk_hw *hw)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
u32 val;
val = readl_relaxed(pll->base);
val &= ~BM_PLL_ENABLE;
writel_relaxed(val, pll->base);
}
static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate) unsigned long parent_rate)
{ {
...@@ -169,8 +140,6 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, ...@@ -169,8 +140,6 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
static const struct clk_ops clk_pllv3_ops = { static const struct clk_ops clk_pllv3_ops = {
.prepare = clk_pllv3_prepare, .prepare = clk_pllv3_prepare,
.unprepare = clk_pllv3_unprepare, .unprepare = clk_pllv3_unprepare,
.enable = clk_pllv3_enable,
.disable = clk_pllv3_disable,
.recalc_rate = clk_pllv3_recalc_rate, .recalc_rate = clk_pllv3_recalc_rate,
.round_rate = clk_pllv3_round_rate, .round_rate = clk_pllv3_round_rate,
.set_rate = clk_pllv3_set_rate, .set_rate = clk_pllv3_set_rate,
...@@ -225,8 +194,6 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, ...@@ -225,8 +194,6 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
static const struct clk_ops clk_pllv3_sys_ops = { static const struct clk_ops clk_pllv3_sys_ops = {
.prepare = clk_pllv3_prepare, .prepare = clk_pllv3_prepare,
.unprepare = clk_pllv3_unprepare, .unprepare = clk_pllv3_unprepare,
.enable = clk_pllv3_enable,
.disable = clk_pllv3_disable,
.recalc_rate = clk_pllv3_sys_recalc_rate, .recalc_rate = clk_pllv3_sys_recalc_rate,
.round_rate = clk_pllv3_sys_round_rate, .round_rate = clk_pllv3_sys_round_rate,
.set_rate = clk_pllv3_sys_set_rate, .set_rate = clk_pllv3_sys_set_rate,
...@@ -299,8 +266,6 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, ...@@ -299,8 +266,6 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
static const struct clk_ops clk_pllv3_av_ops = { static const struct clk_ops clk_pllv3_av_ops = {
.prepare = clk_pllv3_prepare, .prepare = clk_pllv3_prepare,
.unprepare = clk_pllv3_unprepare, .unprepare = clk_pllv3_unprepare,
.enable = clk_pllv3_enable,
.disable = clk_pllv3_disable,
.recalc_rate = clk_pllv3_av_recalc_rate, .recalc_rate = clk_pllv3_av_recalc_rate,
.round_rate = clk_pllv3_av_round_rate, .round_rate = clk_pllv3_av_round_rate,
.set_rate = clk_pllv3_av_set_rate, .set_rate = clk_pllv3_av_set_rate,
...@@ -315,8 +280,6 @@ static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw, ...@@ -315,8 +280,6 @@ static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
static const struct clk_ops clk_pllv3_enet_ops = { static const struct clk_ops clk_pllv3_enet_ops = {
.prepare = clk_pllv3_prepare, .prepare = clk_pllv3_prepare,
.unprepare = clk_pllv3_unprepare, .unprepare = clk_pllv3_unprepare,
.enable = clk_pllv3_enable,
.disable = clk_pllv3_disable,
.recalc_rate = clk_pllv3_enet_recalc_rate, .recalc_rate = clk_pllv3_enet_recalc_rate,
}; };
......
arch/arm/mach-imx/clk-vf610.c
View file @ 9cd70164
...@@ -58,6 +58,8 @@ ...@@ -58,6 +58,8 @@
#define PFD_PLL1_BASE (anatop_base + 0x2b0) #define PFD_PLL1_BASE (anatop_base + 0x2b0)
#define PFD_PLL2_BASE (anatop_base + 0x100) #define PFD_PLL2_BASE (anatop_base + 0x100)
#define PFD_PLL3_BASE (anatop_base + 0xf0) #define PFD_PLL3_BASE (anatop_base + 0xf0)
#define PLL3_CTRL (anatop_base + 0x10)
#define PLL7_CTRL (anatop_base + 0x20)
static void __iomem *anatop_base; static void __iomem *anatop_base;
static void __iomem *ccm_base; static void __iomem *ccm_base;
...@@ -98,9 +100,15 @@ static struct clk_div_table pll4_main_div_table[] = { ...@@ -98,9 +100,15 @@ static struct clk_div_table pll4_main_div_table[] = {
static struct clk *clk[VF610_CLK_END]; static struct clk *clk[VF610_CLK_END];
static struct clk_onecell_data clk_data; static struct clk_onecell_data clk_data;
static unsigned int const clks_init_on[] __initconst = {
VF610_CLK_SYS_BUS,
VF610_CLK_DDR_SEL,
};
static void __init vf610_clocks_init(struct device_node *ccm_node) static void __init vf610_clocks_init(struct device_node *ccm_node)
{ {
struct device_node *np; struct device_node *np;
int i;
clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000);
...@@ -148,6 +156,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) ...@@ -148,6 +156,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6); clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
/* pll6: default 960Mhz */ /* pll6: default 960Mhz */
clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1); clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
/* pll7: USB1 PLL at 480MHz */
clk[VF610_CLK_PLL7_MAIN] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_main", "fast_clk_sel", PLL7_CTRL, 0x2);
clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5); clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5); clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels)); clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
...@@ -160,8 +171,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) ...@@ -160,8 +171,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock); clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1); clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4)); clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_main", PLL3_CTRL, 6);
clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4)); clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_main", PLL7_CTRL, 6);
clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4));
clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4));
clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4); clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4);
clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4); clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4);
...@@ -322,6 +336,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) ...@@ -322,6 +336,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]);
clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]); clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]);
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clk[clks_init_on[i]]);
/* Add the clocks to provider list */ /* Add the clocks to provider list */
clk_data.clks = clk; clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk); clk_data.clk_num = ARRAY_SIZE(clk);
......
arch/arm/mach-imx/clk.h
View file @ 9cd70164
...@@ -36,6 +36,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name, ...@@ -36,6 +36,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
struct clk * imx_obtain_fixed_clock( struct clk * imx_obtain_fixed_clock(
const char *name, unsigned long rate); const char *name, unsigned long rate);
struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
void __iomem *reg, u8 shift, u32 exclusive_mask);
static inline struct clk *imx_clk_gate2(const char *name, const char *parent, static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
void __iomem *reg, u8 shift) void __iomem *reg, u8 shift)
{ {
......
arch/arm/mach-imx/common.h
View file @ 9cd70164
...@@ -98,11 +98,9 @@ void imx_set_cpu_arg(int cpu, u32 arg); ...@@ -98,11 +98,9 @@ void imx_set_cpu_arg(int cpu, u32 arg);
void v7_secondary_startup(void); void v7_secondary_startup(void);
void imx_scu_map_io(void); void imx_scu_map_io(void);
void imx_smp_prepare(void); void imx_smp_prepare(void);
void imx_scu_standby_enable(void);
#else #else
static inline void imx_scu_map_io(void) {} static inline void imx_scu_map_io(void) {}
static inline void imx_smp_prepare(void) {} static inline void imx_smp_prepare(void) {}
static inline void imx_scu_standby_enable(void) {}
#endif #endif
void imx_src_init(void); void imx_src_init(void);
void imx_gpc_init(void); void imx_gpc_init(void);
......
arch/arm/mach-imx/cpuidle-imx6q.c
View file @ 9cd70164
...@@ -66,10 +66,6 @@ static struct cpuidle_driver imx6q_cpuidle_driver = { ...@@ -66,10 +66,6 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
int __init imx6q_cpuidle_init(void) int __init imx6q_cpuidle_init(void)
{ {
/* Need to enable SCU standby for entering WAIT modes */
if (!cpu_is_imx6sx())
imx_scu_standby_enable();
/* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */ /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
imx6q_set_int_mem_clk_lpm(true); imx6q_set_int_mem_clk_lpm(true);
......
arch/arm/mach-imx/eukrea-baseboards.h
View file @ 9cd70164
...@@ -27,23 +27,15 @@ ...@@ -27,23 +27,15 @@
* This CPU module needs a baseboard to work. After basic initializing * This CPU module needs a baseboard to work. After basic initializing
* its own devices, it calls baseboard's init function. * its own devices, it calls baseboard's init function.
* TODO: Add your own baseboard init function and call it from * TODO: Add your own baseboard init function and call it from
* inside eukrea_cpuimx25_init() eukrea_cpuimx27_init() * inside eukrea_cpuimx25_init() or eukrea_cpuimx35_init()
* eukrea_cpuimx35_init() eukrea_cpuimx51_init()
* or eukrea_cpuimx51sd_init().
* *
* This example here is for the development board. Refer * This example here is for the development board. Refer
* mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25 * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
* mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27
* mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35 * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
* mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
* mach-mx5/eukrea_mbimxsd-baseboard.c for cpuimx51sd
*/ */
extern void eukrea_mbimxsd25_baseboard_init(void); extern void eukrea_mbimxsd25_baseboard_init(void);
extern void eukrea_mbimx27_baseboard_init(void);
extern void eukrea_mbimxsd35_baseboard_init(void); extern void eukrea_mbimxsd35_baseboard_init(void);
extern void eukrea_mbimx51_baseboard_init(void);
extern void eukrea_mbimxsd51_baseboard_init(void);
#endif #endif
......
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c deleted 100644 → 0
View file @ 7e9b2828
/*
* Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com
*
* Based on pcm970-baseboard.c which is :
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <linux/backlight.h>
#include <video/platform_lcd.h>
#include <asm/mach/arch.h>
#include "common.h"
#include "devices-imx27.h"
#include "hardware.h"
#include "iomux-mx27.h"
static const int eukrea_mbimx27_pins[] __initconst = {
/* UART2 */
PE3_PF_UART2_CTS,
PE4_PF_UART2_RTS,
PE6_PF_UART2_TXD,
PE7_PF_UART2_RXD,
/* UART3 */
PE8_PF_UART3_TXD,
PE9_PF_UART3_RXD,
PE10_PF_UART3_CTS,
PE11_PF_UART3_RTS,
/* UART4 */
#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
PB26_AF_UART4_RTS,
PB28_AF_UART4_TXD,
PB29_AF_UART4_CTS,
PB31_AF_UART4_RXD,
#endif
/* SDHC1*/
PE18_PF_SD1_D0,
PE19_PF_SD1_D1,
PE20_PF_SD1_D2,
PE21_PF_SD1_D3,
PE22_PF_SD1_CMD,
PE23_PF_SD1_CLK,
/* display */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
PA31_PF_OE_ACD,
/* SPI1 */
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
/* SSI4 */
#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
|| defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
PC16_PF_SSI4_FS,
PC17_PF_SSI4_RXD | GPIO_PUEN,
PC18_PF_SSI4_TXD | GPIO_PUEN,
PC19_PF_SSI4_CLK,
#endif
};
static const uint32_t eukrea_mbimx27_keymap[] = {
KEY(0, 0, KEY_UP),
KEY(0, 1, KEY_DOWN),
KEY(1, 0, KEY_RIGHT),
KEY(1, 1, KEY_LEFT),
};
static const struct matrix_keymap_data
eukrea_mbimx27_keymap_data __initconst = {
.keymap = eukrea_mbimx27_keymap,
.keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap),
};
static const struct gpio_led eukrea_mbimx27_gpio_leds[] __initconst = {
{
.name = "led1",
.default_trigger = "heartbeat",
.active_low = 1,
.gpio = GPIO_PORTF | 16,
},
{
.name = "led2",
.default_trigger = "none",
.active_low = 1,
.gpio = GPIO_PORTF | 19,
},
};
static const struct gpio_led_platform_data
eukrea_mbimx27_gpio_led_info __initconst = {
.leds = eukrea_mbimx27_gpio_leds,
.num_leds = ARRAY_SIZE(eukrea_mbimx27_gpio_leds),
};
static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
{
.mode = {
.name = "CMO-QVGA",
.refresh = 60,
.xres = 320,
.yres = 240,
.pixclock = 156000,
.hsync_len = 30,
.left_margin = 38,
.right_margin = 20,
.vsync_len = 3,
.upper_margin = 15,
.lower_margin = 4,
},
.pcr = 0xFAD08B80,
.bpp = 16,
}, {
.mode = {
.name = "DVI-VGA",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 32000,
.hsync_len = 1,
.left_margin = 35,
.right_margin = 0,
.vsync_len = 1,
.upper_margin = 7,
.lower_margin = 0,
},
.pcr = 0xFA208B80,
.bpp = 16,
}, {
.mode = {
.name = "DVI-SVGA",
.refresh = 60,
.xres = 800,
.yres = 600,
.pixclock = 25000,
.hsync_len = 1,
.left_margin = 35,
.right_margin = 0,
.vsync_len = 1,
.upper_margin = 7,
.lower_margin = 0,
},
.pcr = 0xFA208B80,
.bpp = 16,
},
};
static const struct imx_fb_platform_data eukrea_mbimx27_fb_data __initconst = {
.mode = eukrea_mbimx27_modes,
.num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
.pwmr = 0x00A903FF,
.lscr1 = 0x00120300,
.dmacr = 0x00040060,
};
static void eukrea_mbimx27_bl_set_intensity(int intensity)
{
if (intensity)
gpio_direction_output(GPIO_PORTE | 5, 1);
else
gpio_direction_output(GPIO_PORTE | 5, 0);
}
static struct generic_bl_info eukrea_mbimx27_bl_info = {
.name = "eukrea_mbimx27-bl",
.max_intensity = 0xff,
.default_intensity = 0xff,
.set_bl_intensity = eukrea_mbimx27_bl_set_intensity,
};
static struct platform_device eukrea_mbimx27_bl_dev = {
.name = "generic-bl",
.id = 1,
.dev = {
.platform_data = &eukrea_mbimx27_bl_info,
},
};
static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd,
unsigned int power)
{
if (power)
gpio_direction_output(GPIO_PORTA | 25, 1);
else
gpio_direction_output(GPIO_PORTA | 25, 0);
}
static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = {
.set_power = eukrea_mbimx27_lcd_power_set,
};
static struct platform_device eukrea_mbimx27_lcd_powerdev = {
.name = "platform-lcd",
.dev.platform_data = &eukrea_mbimx27_lcd_power_data,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
#define ADS7846_PENDOWN (GPIO_PORTD | 25)
static void __maybe_unused ads7846_dev_init(void)
{
if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
return;
}
gpio_direction_input(ADS7846_PENDOWN);
}
static int ads7846_get_pendown_state(void)
{
return !gpio_get_value(ADS7846_PENDOWN);
}
static struct ads7846_platform_data ads7846_config __initdata = {
.get_pendown_state = ads7846_get_pendown_state,
.keep_vref_on = 1,
};
static struct spi_board_info __maybe_unused
eukrea_mbimx27_spi_board_info[] __initdata = {
[0] = {
.modalias = "ads7846",
.bus_num = 0,
.chip_select = 0,
.max_speed_hz = 1500000,
/* irq number is run-time assigned */
.platform_data = &ads7846_config,
.mode = SPI_MODE_2,
},
};
static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = {
.chipselect = eukrea_mbimx27_spi_cs,
.num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
};
static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = {
{
I2C_BOARD_INFO("tlv320aic23", 0x1a),
},
};
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.dat3_card_detect = 1,
};
static const
struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata __initconst = {
.flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
};
/*
* system init for baseboard usage. Will be called by cpuimx27 init.
*
* Add platform devices present on this baseboard and init
* them from CPU side as far as required to use them later on
*/
void __init eukrea_mbimx27_baseboard_init(void)
{
mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
imx27_add_imx_uart1(&uart_pdata);
imx27_add_imx_uart2(&uart_pdata);
#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
imx27_add_imx_uart3(&uart_pdata);
#endif
imx27_add_imx_fb(&eukrea_mbimx27_fb_data);
imx27_add_mxc_mmc(0, &sdhc_pdata);
i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
imx27_add_imx_ssi(0, &eukrea_mbimx27_ssi_pdata);
#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
|| defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
/* ADS7846 Touchscreen controller init */
mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
ads7846_dev_init();
#endif
/* SPI_CS0 init */
mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
eukrea_mbimx27_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(4, 25));
spi_register_board_info(eukrea_mbimx27_spi_board_info,
ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
/* Leds configuration */
mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
/* Backlight */
mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
gpio_request(GPIO_PORTE | 5, "backlight");
platform_device_register(&eukrea_mbimx27_bl_dev);
/* LCD Reset */
mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT);
gpio_request(GPIO_PORTA | 25, "lcd_enable");
platform_device_register(&eukrea_mbimx27_lcd_powerdev);
imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data);
gpio_led_register_device(-1, &eukrea_mbimx27_gpio_led_info);
imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
}
arch/arm/mach-imx/imx1-dt.c 0 → 100644
View file @ 9cd70164
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "common.h"
static const char * const imx1_dt_board_compat[] __initconst = {
"fsl,imx1",
NULL
};
DT_MACHINE_START(IMX1_DT, "Freescale i.MX1 (Device Tree Support)")
.map_io = mx1_map_io,
.init_early = imx1_init_early,
.init_irq = mx1_init_irq,
.dt_compat = imx1_dt_board_compat,
.restart = mxc_restart,
MACHINE_END
arch/arm/mach-imx/iomux-imx31.c
View file @ 9cd70164
...@@ -64,7 +64,6 @@ int mxc_iomux_mode(unsigned int pin_mode) ...@@ -64,7 +64,6 @@ int mxc_iomux_mode(unsigned int pin_mode)
return ret; return ret;
} }
EXPORT_SYMBOL(mxc_iomux_mode);
/* /*
* This function configures the pad value for a IOMUX pin. * This function configures the pad value for a IOMUX pin.
...@@ -90,7 +89,6 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) ...@@ -90,7 +89,6 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
spin_unlock(&gpio_mux_lock); spin_unlock(&gpio_mux_lock);
} }
EXPORT_SYMBOL(mxc_iomux_set_pad);
/* /*
* allocs a single pin: * allocs a single pin:
...@@ -116,7 +114,6 @@ int mxc_iomux_alloc_pin(unsigned int pin, const char *label) ...@@ -116,7 +114,6 @@ int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
return 0; return 0;
} }
EXPORT_SYMBOL(mxc_iomux_alloc_pin);
int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
const char *label) const char *label)
...@@ -137,7 +134,6 @@ int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, ...@@ -137,7 +134,6 @@ int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
mxc_iomux_release_multiple_pins(pin_list, i); mxc_iomux_release_multiple_pins(pin_list, i);
return ret; return ret;
} }
EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
void mxc_iomux_release_pin(unsigned int pin) void mxc_iomux_release_pin(unsigned int pin)
{ {
...@@ -146,7 +142,6 @@ void mxc_iomux_release_pin(unsigned int pin) ...@@ -146,7 +142,6 @@ void mxc_iomux_release_pin(unsigned int pin)
if (pad < (PIN_MAX + 1)) if (pad < (PIN_MAX + 1))
clear_bit(pad, mxc_pin_alloc_map); clear_bit(pad, mxc_pin_alloc_map);
} }
EXPORT_SYMBOL(mxc_iomux_release_pin);
void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count) void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
{ {
...@@ -158,7 +153,6 @@ void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count) ...@@ -158,7 +153,6 @@ void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
p++; p++;
} }
} }
EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
/* /*
* This function enables/disables the general purpose function for a particular * This function enables/disables the general purpose function for a particular
...@@ -178,4 +172,3 @@ void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en) ...@@ -178,4 +172,3 @@ void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
__raw_writel(l, IOMUXGPR); __raw_writel(l, IOMUXGPR);
spin_unlock(&gpio_mux_lock); spin_unlock(&gpio_mux_lock);
} }
EXPORT_SYMBOL(mxc_iomux_set_gpr);
arch/arm/mach-imx/iomux-v1.c
View file @ 9cd70164
...@@ -153,7 +153,6 @@ int mxc_gpio_mode(int gpio_mode) ...@@ -153,7 +153,6 @@ int mxc_gpio_mode(int gpio_mode)
return 0; return 0;
} }
EXPORT_SYMBOL(mxc_gpio_mode);
static int imx_iomuxv1_setup_multiple(const int *list, unsigned count) static int imx_iomuxv1_setup_multiple(const int *list, unsigned count)
{ {
...@@ -178,7 +177,6 @@ int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, ...@@ -178,7 +177,6 @@ int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
ret = imx_iomuxv1_setup_multiple(pin_list, count); ret = imx_iomuxv1_setup_multiple(pin_list, count);
return ret; return ret;
} }
EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
int __init imx_iomuxv1_init(void __iomem *base, int numports) int __init imx_iomuxv1_init(void __iomem *base, int numports)
{ {
......
arch/arm/mach-imx/iomux-v3.c
View file @ 9cd70164
...@@ -55,7 +55,6 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad) ...@@ -55,7 +55,6 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
return 0; return 0;
} }
EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
{ {
...@@ -71,7 +70,6 @@ int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) ...@@ -71,7 +70,6 @@ int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
} }
return 0; return 0;
} }
EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
void mxc_iomux_v3_init(void __iomem *iomux_v3_base) void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
{ {
......
arch/arm/mach-imx/mach-armadillo5x0.c
View file @ 9cd70164
...@@ -537,7 +537,7 @@ static void __init armadillo5x0_init(void) ...@@ -537,7 +537,7 @@ static void __init armadillo5x0_init(void)
gpio_free(ARMADILLO5X0_RTC_GPIO); gpio_free(ARMADILLO5X0_RTC_GPIO);
} }
if (armadillo5x0_i2c_rtc.irq == 0) if (armadillo5x0_i2c_rtc.irq == 0)
pr_warning("armadillo5x0_init: failed to get RTC IRQ\n"); pr_warn("armadillo5x0_init: failed to get RTC IRQ\n");
i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1); i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
/* USB */ /* USB */
......
arch/arm/mach-imx/mach-cpuimx27.c deleted 100644 → 0
View file @ 7e9b2828
/*
* Copyright (C) 2009 Eric Benard - eric@eukrea.com
*
* Based on pcm038.c which is :
* Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/mtd/plat-ram.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include "common.h"
#include "devices-imx27.h"
#include "ehci.h"
#include "eukrea-baseboards.h"
#include "hardware.h"
#include "iomux-mx27.h"
#include "ulpi.h"
static const int eukrea_cpuimx27_pins[] __initconst = {
/* UART1 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
/* UART4 */
#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
PB26_AF_UART4_RTS,
PB28_AF_UART4_TXD,
PB29_AF_UART4_CTS,
PB31_AF_UART4_RXD,
#endif
/* FEC */
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
/* I2C1 */
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
/* SDHC2 */
#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
PB4_PF_SD2_D0,
PB5_PF_SD2_D1,
PB6_PF_SD2_D2,
PB7_PF_SD2_D3,
PB8_PF_SD2_CMD,
PB9_PF_SD2_CLK,
#endif
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
/* Quad UART's IRQ */
GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN,
GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN,
GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN,
GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN,
#endif
/* OTG */
PC7_PF_USBOTG_DATA5,
PC8_PF_USBOTG_DATA6,
PC9_PF_USBOTG_DATA0,
PC10_PF_USBOTG_DATA2,
PC11_PF_USBOTG_DATA1,
PC12_PF_USBOTG_DATA4,
PC13_PF_USBOTG_DATA3,
PE0_PF_USBOTG_NXT,
PE1_PF_USBOTG_STP,
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
/* USBH2 */
PA0_PF_USBH2_CLK,
PA1_PF_USBH2_DIR,
PA2_PF_USBH2_DATA7,
PA3_PF_USBH2_NXT,
PA4_PF_USBH2_STP,
PD19_AF_USBH2_DATA4,
PD20_AF_USBH2_DATA3,
PD21_AF_USBH2_DATA6,
PD22_AF_USBH2_DATA0,
PD23_AF_USBH2_DATA2,
PD24_AF_USBH2_DATA1,
PD26_AF_USBH2_DATA5,
};
static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
.width = 2,
};
static struct resource eukrea_cpuimx27_flash_resource = {
.start = 0xc0000000,
.end = 0xc3ffffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &eukrea_cpuimx27_flash_data,
},
.num_resources = 1,
.resource = &eukrea_cpuimx27_flash_resource,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static const struct mxc_nand_platform_data
cpuimx27_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
};
static struct platform_device *platform_devices[] __initdata = {
&eukrea_cpuimx27_nor_mtd_device,
};
static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
.bitrate = 100000,
};
static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
{
I2C_BOARD_INFO("pcf8563", 0x51),
},
};
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
static struct plat_serial8250_port serial_platform_data[] = {
{
.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
/* irq number is run-time assigned */
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
/* irq number is run-time assigned */
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
/* irq number is run-time assigned */
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
/* irq number is run-time assigned */
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
}
};
static struct platform_device serial_device = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = serial_platform_data,
},
};
#endif
static int eukrea_cpuimx27_otg_init(struct platform_device *pdev)
{
return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
}
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.init = eukrea_cpuimx27_otg_init,
.portsc = MXC_EHCI_MODE_ULPI,
};
static int eukrea_cpuimx27_usbh2_init(struct platform_device *pdev)
{
return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
}
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = eukrea_cpuimx27_usbh2_init,
.portsc = MXC_EHCI_MODE_ULPI,
};
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
static bool otg_mode_host __initdata;
static int __init eukrea_cpuimx27_otg_mode(char *options)
{
if (!strcmp(options, "host"))
otg_mode_host = true;
else if (!strcmp(options, "device"))
otg_mode_host = false;
else
pr_info("otg_mode neither \"host\" nor \"device\". "
"Defaulting to device\n");
return 1;
}
__setup("otg_mode=", eukrea_cpuimx27_otg_mode);
static void __init eukrea_cpuimx27_init(void)
{
imx27_soc_init();
mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
imx27_add_imx_uart0(&uart_pdata);
imx27_add_mxc_nand(&cpuimx27_nand_board_info);
i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
imx27_add_imx_i2c(0, &cpuimx27_i2c1_data);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_imx2_wdt();
imx27_add_mxc_w1();
#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
/* SDHC2 can be used for Wifi */
imx27_add_mxc_mmc(1, NULL);
#endif
#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
/* in which case UART4 is also used for Bluetooth */
imx27_add_imx_uart3(&uart_pdata);
#endif
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
serial_platform_data[0].irq = IMX_GPIO_NR(2, 23);
serial_platform_data[1].irq = IMX_GPIO_NR(2, 22);
serial_platform_data[2].irq = IMX_GPIO_NR(2, 27);
serial_platform_data[3].irq = IMX_GPIO_NR(2, 30);
platform_device_register(&serial_device);
#endif
if (otg_mode_host) {
otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
ULPI_OTG_DRVVBUS_EXT);
if (otg_pdata.otg)
imx27_add_mxc_ehci_otg(&otg_pdata);
} else {
imx27_add_fsl_usb2_udc(&otg_device_pdata);
}
usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
ULPI_OTG_DRVVBUS_EXT);
if (usbh2_pdata.otg)
imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
eukrea_mbimx27_baseboard_init();
#endif
}
static void __init eukrea_cpuimx27_timer_init(void)
{
mx27_clocks_init(26000000);
}
MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
.atag_offset = 0x100,
.map_io = mx27_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
.init_time = eukrea_cpuimx27_timer_init,
.init_machine = eukrea_cpuimx27_init,
.restart = mxc_restart,
MACHINE_END
arch/arm/mach-imx/mach-imx6sx.c
View file @ 9cd70164
...@@ -42,6 +42,9 @@ static void __init imx6sx_init_irq(void) ...@@ -42,6 +42,9 @@ static void __init imx6sx_init_irq(void)
static void __init imx6sx_init_late(void) static void __init imx6sx_init_late(void)
{ {
imx6q_cpuidle_init(); imx6q_cpuidle_init();
if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
} }
static const char * const imx6sx_dt_compat[] __initconst = { static const char * const imx6sx_dt_compat[] __initconst = {
......
arch/arm/mach-imx/mach-mx1ads.c deleted 100644 → 0
View file @ 7e9b2828
/*
* arch/arm/mach-imx/mach-mx1ads.c
*
* Initially based on:
* linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c
* Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
*
* 2004 (c) MontaVista Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/i2c.h>
#include <linux/i2c/pcf857x.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "common.h"
#include "devices-imx1.h"
#include "hardware.h"
#include "iomux-mx1.h"
static const int mx1ads_pins[] __initconst = {
/* UART1 */
PC9_PF_UART1_CTS,
PC10_PF_UART1_RTS,
PC11_PF_UART1_TXD,
PC12_PF_UART1_RXD,
/* UART2 */
PB28_PF_UART2_CTS,
PB29_PF_UART2_RTS,
PB30_PF_UART2_TXD,
PB31_PF_UART2_RXD,
/* I2C */
PA15_PF_I2C_SDA,
PA16_PF_I2C_SCL,
/* SPI */
PC13_PF_SPI1_SPI_RDY,
PC14_PF_SPI1_SCLK,
PC15_PF_SPI1_SS,
PC16_PF_SPI1_MISO,
PC17_PF_SPI1_MOSI,
};
/*
* UARTs platform data
*/
static const struct imxuart_platform_data uart0_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static const struct imxuart_platform_data uart1_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
/*
* Physmap flash
*/
static const struct physmap_flash_data mx1ads_flash_data __initconst = {
.width = 4, /* bankwidth in bytes */
};
static const struct resource flash_resource __initconst = {
.start = MX1_CS0_PHYS,
.end = MX1_CS0_PHYS + SZ_32M - 1,
.flags = IORESOURCE_MEM,
};
/*
* I2C
*/
static struct pcf857x_platform_data pcf857x_data[] = {
{
.gpio_base = 4 * 32,
}, {
.gpio_base = 4 * 32 + 16,
}
};
static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = {
.bitrate = 100000,
};
static struct i2c_board_info mx1ads_i2c_devices[] = {
{
I2C_BOARD_INFO("pcf8575", 0x22),
.platform_data = &pcf857x_data[0],
}, {
I2C_BOARD_INFO("pcf8575", 0x24),
.platform_data = &pcf857x_data[1],
},
};
/*
* Board init
*/
static void __init mx1ads_init(void)
{
imx1_soc_init();
mxc_gpio_setup_multiple_pins(mx1ads_pins,
ARRAY_SIZE(mx1ads_pins), "mx1ads");
/* UART */
imx1_add_imx_uart0(&uart0_pdata);
imx1_add_imx_uart1(&uart1_pdata);
/* Physmap flash */
platform_device_register_resndata(NULL, "physmap-flash", 0,
&flash_resource, 1,
&mx1ads_flash_data, sizeof(mx1ads_flash_data));
/* I2C */
i2c_register_board_info(0, mx1ads_i2c_devices,
ARRAY_SIZE(mx1ads_i2c_devices));
imx1_add_imx_i2c(&mx1ads_i2c_data);
}
static void __init mx1ads_timer_init(void)
{
mx1_clocks_init(32000);
}
MACHINE_START(MX1ADS, "Freescale MX1ADS")
/* Maintainer: Sascha Hauer, Pengutronix */
.atag_offset = 0x100,
.map_io = mx1_map_io,
.init_early = imx1_init_early,
.init_irq = mx1_init_irq,
.init_time = mx1ads_timer_init,
.init_machine = mx1ads_init,
.restart = mxc_restart,
MACHINE_END
MACHINE_START(MXLADS, "Freescale MXLADS")
.atag_offset = 0x100,
.map_io = mx1_map_io,
.init_early = imx1_init_early,
.init_irq = mx1_init_irq,
.init_time = mx1ads_timer_init,
.init_machine = mx1ads_init,
.restart = mxc_restart,
MACHINE_END
arch/arm/mach-imx/mach-mx31_3ds.c
View file @ 9cd70164
...@@ -307,7 +307,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev, ...@@ -307,7 +307,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev,
ret = gpio_request_array(mx31_3ds_sdhc1_gpios, ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
if (ret) { if (ret) {
pr_warning("Unable to request the SD/MMC GPIOs.\n"); pr_warn("Unable to request the SD/MMC GPIOs.\n");
return ret; return ret;
} }
...@@ -316,7 +316,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev, ...@@ -316,7 +316,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev,
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
"sdhc1-detect", data); "sdhc1-detect", data);
if (ret) { if (ret) {
pr_warning("Unable to request the SD/MMC card-detect IRQ.\n"); pr_warn("Unable to request the SD/MMC card-detect IRQ.\n");
goto gpio_free; goto gpio_free;
} }
......
arch/arm/mach-imx/mach-mx31lite.c
View file @ 9cd70164
...@@ -270,7 +270,7 @@ static void __init mx31lite_init(void) ...@@ -270,7 +270,7 @@ static void __init mx31lite_init(void)
/* SMSC9117 IRQ pin */ /* SMSC9117 IRQ pin */
ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
if (ret) if (ret)
pr_warning("could not get LAN irq gpio\n"); pr_warn("could not get LAN irq gpio\n");
else { else {
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6)); gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
smsc911x_resources[1].start = smsc911x_resources[1].start =
......
arch/arm/mach-imx/mach-mxt_td60.c deleted 100644 → 0
View file @ 7e9b2828
/*
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <linux/gpio.h>
#include <linux/platform_data/pca953x.h>
#include "common.h"
#include "devices-imx27.h"
#include "hardware.h"
#include "iomux-mx27.h"
static const int mxt_td60_pins[] __initconst = {
/* UART0 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
/* UART1 */
PE3_PF_UART2_CTS,
PE4_PF_UART2_RTS,
PE6_PF_UART2_TXD,
PE7_PF_UART2_RXD,
/* UART2 */
PE8_PF_UART3_TXD,
PE9_PF_UART3_RXD,
PE10_PF_UART3_CTS,
PE11_PF_UART3_RTS,
/* FEC */
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
/* I2C1 */
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
/* I2C2 */
PC5_PF_I2C2_SDA,
PC6_PF_I2C2_SCL,
/* FB */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA25_PF_CLS,
PA27_PF_SPL_SPR,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
PA31_PF_OE_ACD,
/* OWIRE */
PE16_AF_OWIRE,
/* SDHC1*/
PE18_PF_SD1_D0,
PE19_PF_SD1_D1,
PE20_PF_SD1_D2,
PE21_PF_SD1_D3,
PE22_PF_SD1_CMD,
PE23_PF_SD1_CLK,
PF8_AF_ATA_IORDY,
/* SDHC2*/
PB4_PF_SD2_D0,
PB5_PF_SD2_D1,
PB6_PF_SD2_D2,
PB7_PF_SD2_D3,
PB8_PF_SD2_CMD,
PB9_PF_SD2_CLK,
};
static const struct mxc_nand_platform_data
mxt_td60_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
};
static const struct imxi2c_platform_data mxt_td60_i2c0_data __initconst = {
.bitrate = 100000,
};
/* PCA9557 */
static int mxt_td60_pca9557_setup(struct i2c_client *client,
unsigned gpio_base, unsigned ngpio,
void *context)
{
static int mxt_td60_gpio_value[] = {
-1, -1, -1, -1, -1, -1, -1, 1
};
int n;
for (n = 0; n < ARRAY_SIZE(mxt_td60_gpio_value); ++n) {
gpio_request(gpio_base + n, "MXT_TD60 GPIO Exp");
if (mxt_td60_gpio_value[n] < 0)
gpio_direction_input(gpio_base + n);
else
gpio_direction_output(gpio_base + n,
mxt_td60_gpio_value[n]);
gpio_export(gpio_base + n, 0);
}
return 0;
}
static struct pca953x_platform_data mxt_td60_pca9557_pdata = {
.gpio_base = 240, /* place PCA9557 after all MX27 gpio pins */
.invert = 0, /* Do not invert */
.setup = mxt_td60_pca9557_setup,
};
static struct i2c_board_info mxt_td60_i2c_devices[] = {
{
I2C_BOARD_INFO("pca9557", 0x18),
.platform_data = &mxt_td60_pca9557_pdata,
},
};
static const struct imxi2c_platform_data mxt_td60_i2c1_data __initconst = {
.bitrate = 100000,
};
static struct i2c_board_info mxt_td60_i2c2_devices[] = {
};
static struct imx_fb_videomode mxt_td60_modes[] = {
{
.mode = {
.name = "Chimei LW700AT9003",
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = 30303,
.hsync_len = 64,
.left_margin = 0x67,
.right_margin = 0x68,
.vsync_len = 16,
.upper_margin = 0x0f,
.lower_margin = 0x0f,
},
.bpp = 16,
.pcr = 0xFA208B83,
},
};
static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = {
.mode = mxt_td60_modes,
.num_modes = ARRAY_SIZE(mxt_td60_modes),
/*
* - HSYNC active high
* - VSYNC active high
* - clk notenabled while idle
* - clock inverted
* - data not inverted
* - data enable low active
* - enable sharp mode
*/
.pwmr = 0x00A903FF,
.lscr1 = 0x00120300,
.dmacr = 0x00020010,
};
static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
return request_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), detect_irq,
IRQF_TRIGGER_FALLING, "sdhc1-card-detect", data);
}
static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
{
free_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), data);
}
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
.init = mxt_td60_sdhc1_init,
.exit = mxt_td60_sdhc1_exit,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static void __init mxt_td60_board_init(void)
{
imx27_soc_init();
mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
"MXT_TD60");
imx27_add_imx_uart0(&uart_pdata);
imx27_add_imx_uart1(&uart_pdata);
imx27_add_imx_uart2(&uart_pdata);
imx27_add_mxc_nand(&mxt_td60_nand_board_info);
i2c_register_board_info(0, mxt_td60_i2c_devices,
ARRAY_SIZE(mxt_td60_i2c_devices));
i2c_register_board_info(1, mxt_td60_i2c2_devices,
ARRAY_SIZE(mxt_td60_i2c2_devices));
imx27_add_imx_i2c(0, &mxt_td60_i2c0_data);
imx27_add_imx_i2c(1, &mxt_td60_i2c1_data);
imx27_add_imx_fb(&mxt_td60_fb_data);
imx27_add_mxc_mmc(0, &sdhc1_pdata);
imx27_add_fec(NULL);
}
static void __init mxt_td60_timer_init(void)
{
mx27_clocks_init(26000000);
}
MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
/* maintainer: Maxtrack Industrial */
.atag_offset = 0x100,
.map_io = mx27_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
.init_time = mxt_td60_timer_init,
.init_machine = mxt_td60_board_init,
.restart = mxc_restart,
MACHINE_END
arch/arm/mach-imx/mach-pcm037.c
View file @ 9cd70164
...@@ -58,7 +58,7 @@ static int __init pcm037_variant_setup(char *str) ...@@ -58,7 +58,7 @@ static int __init pcm037_variant_setup(char *str)
if (!strcmp("eet", str)) if (!strcmp("eet", str))
pcm037_instance = PCM037_EET; pcm037_instance = PCM037_EET;
else if (strcmp("pcm970", str)) else if (strcmp("pcm970", str))
pr_warning("Unknown pcm037 baseboard variant %s\n", str); pr_warn("Unknown pcm037 baseboard variant %s\n", str);
return 1; return 1;
} }
...@@ -624,7 +624,7 @@ static void __init pcm037_init(void) ...@@ -624,7 +624,7 @@ static void __init pcm037_init(void)
/* LAN9217 IRQ pin */ /* LAN9217 IRQ pin */
ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
if (ret) if (ret)
pr_warning("could not get LAN irq gpio\n"); pr_warn("could not get LAN irq gpio\n");
else { else {
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)); gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
smsc911x_resources[1].start = smsc911x_resources[1].start =
......
arch/arm/mach-imx/mach-pcm038.c deleted 100644 → 0
View file @ 7e9b2828
/*
* Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/i2c.h>
#include <linux/platform_data/at24.h>
#include <linux/io.h>
#include <linux/mtd/plat-ram.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/regulator/machine.h>
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "board-pcm038.h"
#include "common.h"
#include "devices-imx27.h"
#include "ehci.h"
#include "hardware.h"
#include "iomux-mx27.h"
#include "ulpi.h"
static const int pcm038_pins[] __initconst = {
/* UART1 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
/* UART2 */
PE3_PF_UART2_CTS,
PE4_PF_UART2_RTS,
PE6_PF_UART2_TXD,
PE7_PF_UART2_RXD,
/* UART3 */
PE8_PF_UART3_TXD,
PE9_PF_UART3_RXD,
PE10_PF_UART3_CTS,
PE11_PF_UART3_RTS,
/* FEC */
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
/* I2C2 */
PC5_PF_I2C2_SDA,
PC6_PF_I2C2_SCL,
/* SPI1 */
PD25_PF_CSPI1_RDY,
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
/* SSI1 */
PC20_PF_SSI1_FS,
PC21_PF_SSI1_RXD,
PC22_PF_SSI1_TXD,
PC23_PF_SSI1_CLK,
/* SSI4 */
PC16_PF_SSI4_FS,
PC17_PF_SSI4_RXD,
PC18_PF_SSI4_TXD,
PC19_PF_SSI4_CLK,
/* USB host */
PA0_PF_USBH2_CLK,
PA1_PF_USBH2_DIR,
PA2_PF_USBH2_DATA7,
PA3_PF_USBH2_NXT,
PA4_PF_USBH2_STP,
PD19_AF_USBH2_DATA4,
PD20_AF_USBH2_DATA3,
PD21_AF_USBH2_DATA6,
PD22_AF_USBH2_DATA0,
PD23_AF_USBH2_DATA2,
PD24_AF_USBH2_DATA1,
PD26_AF_USBH2_DATA5,
};
/*
* Phytec's PCM038 comes with 2MiB battery buffered SRAM,
* 16 bit width
*/
static struct platdata_mtd_ram pcm038_sram_data = {
.bankwidth = 2,
};
static struct resource pcm038_sram_resource = {
.start = MX27_CS1_BASE_ADDR,
.end = MX27_CS1_BASE_ADDR + 512 * 1024 - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device pcm038_sram_mtd_device = {
.name = "mtd-ram",
.id = 0,
.dev = {
.platform_data = &pcm038_sram_data,
},
.num_resources = 1,
.resource = &pcm038_sram_resource,
};
/*
* Phytec's phyCORE-i.MX27 comes with 32MiB flash,
* 16 bit width
*/
static struct physmap_flash_data pcm038_flash_data = {
.width = 2,
};
static struct resource pcm038_flash_resource = {
.start = 0xc0000000,
.end = 0xc1ffffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device pcm038_nor_mtd_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &pcm038_flash_data,
},
.num_resources = 1,
.resource = &pcm038_flash_resource,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static const struct mxc_nand_platform_data
pcm038_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
};
static struct platform_device *platform_devices[] __initdata = {
&pcm038_nor_mtd_device,
&pcm038_sram_mtd_device,
};
/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
* setup other stuffs to access the sram. */
static void __init pcm038_init_sram(void)
{
__raw_writel(0x0000d843, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(1)));
__raw_writel(0x22252521, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(1)));
__raw_writel(0x22220a00, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(1)));
}
static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = {
.bitrate = 100000,
};
static struct at24_platform_data board_eeprom = {
.byte_len = 4096,
.page_size = 32,
.flags = AT24_FLAG_ADDR16,
};
static struct i2c_board_info pcm038_i2c_devices[] = {
{
I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
.platform_data = &board_eeprom,
}, {
I2C_BOARD_INFO("pcf8563", 0x51),
}, {
I2C_BOARD_INFO("lm75", 0x4a),
}
};
static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
static const struct spi_imx_master pcm038_spi0_data __initconst = {
.chipselect = pcm038_spi_cs,
.num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
};
static struct regulator_consumer_supply sdhc1_consumers[] = {
{
.dev_name = "imx21-mmc.1",
.supply = "sdhc_vcc",
},
};
static struct regulator_init_data sdhc1_data = {
.constraints = {
.min_uV = 3000000,
.max_uV = 3400000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
.valid_modes_mask = REGULATOR_MODE_NORMAL |
REGULATOR_MODE_FAST,
.always_on = 0,
.boot_on = 0,
},
.num_consumer_supplies = ARRAY_SIZE(sdhc1_consumers),
.consumer_supplies = sdhc1_consumers,
};
static struct regulator_consumer_supply cam_consumers[] = {
{
.dev_name = NULL,
.supply = "imx_cam_vcc",
},
};
static struct regulator_init_data cam_data = {
.constraints = {
.min_uV = 3000000,
.max_uV = 3400000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
.valid_modes_mask = REGULATOR_MODE_NORMAL |
REGULATOR_MODE_FAST,
.always_on = 0,
.boot_on = 0,
},
.num_consumer_supplies = ARRAY_SIZE(cam_consumers),
.consumer_supplies = cam_consumers,
};
static struct mc13xxx_regulator_init_data pcm038_regulators[] = {
{
.id = MC13783_REG_VCAM,
.init_data = &cam_data,
}, {
.id = MC13783_REG_VMMC1,
.init_data = &sdhc1_data,
},
};
static struct mc13xxx_platform_data pcm038_pmic = {
.regulators = {
.regulators = pcm038_regulators,
.num_regulators = ARRAY_SIZE(pcm038_regulators),
},
.flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
};
static struct spi_board_info pcm038_spi_board_info[] __initdata = {
{
.modalias = "mc13783",
/* irq number is run-time assigned */
.max_speed_hz = 300000,
.bus_num = 0,
.chip_select = 0,
.platform_data = &pcm038_pmic,
.mode = SPI_CS_HIGH,
}
};
static int pcm038_usbh2_init(struct platform_device *pdev)
{
return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
MXC_EHCI_INTERFACE_DIFF_UNI);
}
static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
.init = pcm038_usbh2_init,
.portsc = MXC_EHCI_MODE_ULPI,
};
static void __init pcm038_init(void)
{
imx27_soc_init();
mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
"PCM038");
pcm038_init_sram();
imx27_add_imx_uart0(&uart_pdata);
imx27_add_imx_uart1(&uart_pdata);
imx27_add_imx_uart2(&uart_pdata);
mxc_gpio_mode(PE16_AF_OWIRE);
imx27_add_mxc_nand(&pcm038_nand_board_info);
/* only the i2c master 1 is used on this CPU card */
i2c_register_board_info(1, pcm038_i2c_devices,
ARRAY_SIZE(pcm038_i2c_devices));
imx27_add_imx_i2c(1, &pcm038_i2c1_data);
/* PE18 for user-LED D40 */
mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
/* MC13783 IRQ */
mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
imx27_add_spi_imx0(&pcm038_spi0_data);
pcm038_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(2, 23));
spi_register_board_info(pcm038_spi_board_info,
ARRAY_SIZE(pcm038_spi_board_info));
imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_imx2_wdt();
imx27_add_mxc_w1();
#ifdef CONFIG_MACH_PCM970_BASEBOARD
pcm970_baseboard_init();
#endif
}
static void __init pcm038_timer_init(void)
{
mx27_clocks_init(26000000);
}
MACHINE_START(PCM038, "phyCORE-i.MX27")
.atag_offset = 0x100,
.map_io = mx27_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
.init_time = pcm038_timer_init,
.init_machine = pcm038_init,
.restart = mxc_restart,
MACHINE_END
arch/arm/mach-imx/mxc.h
View file @ 9cd70164
...@@ -43,6 +43,8 @@ ...@@ -43,6 +43,8 @@
#define IMX_CHIP_REVISION_1_1 0x11 #define IMX_CHIP_REVISION_1_1 0x11
#define IMX_CHIP_REVISION_1_2 0x12 #define IMX_CHIP_REVISION_1_2 0x12
#define IMX_CHIP_REVISION_1_3 0x13 #define IMX_CHIP_REVISION_1_3 0x13
#define IMX_CHIP_REVISION_1_4 0x14
#define IMX_CHIP_REVISION_1_5 0x15
#define IMX_CHIP_REVISION_2_0 0x20 #define IMX_CHIP_REVISION_2_0 0x20
#define IMX_CHIP_REVISION_2_1 0x21 #define IMX_CHIP_REVISION_2_1 0x21
#define IMX_CHIP_REVISION_2_2 0x22 #define IMX_CHIP_REVISION_2_2 0x22
......
arch/arm/mach-imx/pcm970-baseboard.c deleted 100644 → 0
View file @ 7e9b2828
/*
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/can/platform/sja1000.h>
#include <asm/mach/arch.h>
#include "common.h"
#include "devices-imx27.h"
#include "hardware.h"
#include "iomux-mx27.h"
static const int pcm970_pins[] __initconst = {
/* SDHC */
PB4_PF_SD2_D0,
PB5_PF_SD2_D1,
PB6_PF_SD2_D2,
PB7_PF_SD2_D3,
PB8_PF_SD2_CMD,
PB9_PF_SD2_CLK,
/* display */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA24_PF_REV,
PA25_PF_CLS,
PA26_PF_PS,
PA27_PF_SPL_SPR,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
PA31_PF_OE_ACD,
/*
* it seems the data line misses a pullup, so we must enable
* the internal pullup as a local workaround
*/
PD17_PF_I2C_DATA | GPIO_PUEN,
PD18_PF_I2C_CLK,
/* Camera */
PB10_PF_CSI_D0,
PB11_PF_CSI_D1,
PB12_PF_CSI_D2,
PB13_PF_CSI_D3,
PB14_PF_CSI_D4,
PB15_PF_CSI_MCLK,
PB16_PF_CSI_PIXCLK,
PB17_PF_CSI_D5,
PB18_PF_CSI_D6,
PB19_PF_CSI_D7,
PB20_PF_CSI_VSYNC,
PB21_PF_CSI_HSYNC,
};
static int pcm970_sdhc2_get_ro(struct device *dev)
{
return gpio_get_value(GPIO_PORTC + 28);
}
static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data)
{
int ret;
ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
IRQF_TRIGGER_FALLING, "imx-mmc-detect", data);
if (ret)
return ret;
ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
if (ret) {
free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
return ret;
}
gpio_direction_input(GPIO_PORTC + 28);
return 0;
}
static void pcm970_sdhc2_exit(struct device *dev, void *data)
{
free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
gpio_free(GPIO_PORTC + 28);
}
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.get_ro = pcm970_sdhc2_get_ro,
.init = pcm970_sdhc2_init,
.exit = pcm970_sdhc2_exit,
};
static struct imx_fb_videomode pcm970_modes[] = {
{
.mode = {
.name = "Sharp-LQ035Q7",
.refresh = 60,
.xres = 240,
.yres = 320,
.pixclock = 188679, /* in ps (5.3MHz) */
.hsync_len = 7,
.left_margin = 5,
.right_margin = 16,
.vsync_len = 1,
.upper_margin = 7,
.lower_margin = 9,
},
/*
* - HSYNC active high
* - VSYNC active high
* - clk notenabled while idle
* - clock not inverted
* - data not inverted
* - data enable low active
* - enable sharp mode
*/
.pcr = 0xF00080C0,
.bpp = 16,
}, {
.mode = {
.name = "TX090",
.refresh = 60,
.xres = 240,
.yres = 320,
.pixclock = 38255,
.left_margin = 144,
.right_margin = 0,
.upper_margin = 7,
.lower_margin = 40,
.hsync_len = 96,
.vsync_len = 1,
},
/*
* - HSYNC active low (1 << 22)
* - VSYNC active low (1 << 23)
* - clk notenabled while idle
* - clock not inverted
* - data not inverted
* - data enable low active
* - enable sharp mode
*/
.pcr = 0xF0008080 | (1<<22) | (1<<23) | (1<<19),
.bpp = 32,
},
};
static const struct imx_fb_platform_data pcm038_fb_data __initconst = {
.mode = pcm970_modes,
.num_modes = ARRAY_SIZE(pcm970_modes),
.pwmr = 0x00A903FF,
.lscr1 = 0x00120300,
.dmacr = 0x00020010,
};
static struct resource pcm970_sja1000_resources[] = {
{
.start = MX27_CS4_BASE_ADDR,
.end = MX27_CS4_BASE_ADDR + 0x100 - 1,
.flags = IORESOURCE_MEM,
}, {
/* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};
static struct sja1000_platform_data pcm970_sja1000_platform_data = {
.osc_freq = 16000000,
.ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
.cdr = CDR_CBP,
};
static struct platform_device pcm970_sja1000 = {
.name = "sja1000_platform",
.dev = {
.platform_data = &pcm970_sja1000_platform_data,
},
.resource = pcm970_sja1000_resources,
.num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
};
/*
* system init for baseboard usage. Will be called by pcm038 init.
*
* Add platform devices present on this baseboard and init
* them from CPU side as far as required to use them later on
*/
void __init pcm970_baseboard_init(void)
{
mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins),
"PCM970");
imx27_add_imx_fb(&pcm038_fb_data);
mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
imx27_add_mxc_mmc(1, &sdhc_pdata);
pcm970_sja1000_resources[1].start = gpio_to_irq(IMX_GPIO_NR(5, 19));
pcm970_sja1000_resources[1].end = gpio_to_irq(IMX_GPIO_NR(5, 19));
platform_device_register(&pcm970_sja1000);
}
arch/arm/mach-imx/platsmp.c
View file @ 9cd70164
...@@ -20,8 +20,6 @@ ...@@ -20,8 +20,6 @@
#include "common.h" #include "common.h"
#include "hardware.h" #include "hardware.h"
#define SCU_STANDBY_ENABLE (1 << 5)
u32 g_diag_reg; u32 g_diag_reg;
static void __iomem *scu_base; static void __iomem *scu_base;
...@@ -45,14 +43,6 @@ void __init imx_scu_map_io(void) ...@@ -45,14 +43,6 @@ void __init imx_scu_map_io(void)
scu_base = IMX_IO_ADDRESS(base); scu_base = IMX_IO_ADDRESS(base);
} }
void imx_scu_standby_enable(void)
{
u32 val = readl_relaxed(scu_base);
val |= SCU_STANDBY_ENABLE;
writel_relaxed(val, scu_base);
}
static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle) static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{ {
imx_set_cpu_jump(cpu, v7_secondary_startup); imx_set_cpu_jump(cpu, v7_secondary_startup);
......
arch/arm/mach-imx/time.c
View file @ 9cd70164
...@@ -60,17 +60,22 @@ ...@@ -60,17 +60,22 @@
#define MX2_TSTAT_CAPT (1 << 1) #define MX2_TSTAT_CAPT (1 << 1)
#define MX2_TSTAT_COMP (1 << 0) #define MX2_TSTAT_COMP (1 << 0)
/* MX31, MX35, MX25, MX5 */ /* MX31, MX35, MX25, MX5, MX6 */
#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
#define V2_TCTL_CLK_IPG (1 << 6) #define V2_TCTL_CLK_IPG (1 << 6)
#define V2_TCTL_CLK_PER (2 << 6) #define V2_TCTL_CLK_PER (2 << 6)
#define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
#define V2_TCTL_FRR (1 << 9) #define V2_TCTL_FRR (1 << 9)
#define V2_TCTL_24MEN (1 << 10)
#define V2_TPRER_PRE24M 12
#define V2_IR 0x0c #define V2_IR 0x0c
#define V2_TSTAT 0x08 #define V2_TSTAT 0x08
#define V2_TSTAT_OF1 (1 << 0) #define V2_TSTAT_OF1 (1 << 0)
#define V2_TCN 0x24 #define V2_TCN 0x24
#define V2_TCMP 0x10 #define V2_TCMP 0x10
#define V2_TIMER_RATE_OSC_DIV8 3000000
#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) #define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
#define timer_is_v2() (!timer_is_v1()) #define timer_is_v2() (!timer_is_v1())
...@@ -312,10 +317,22 @@ static void __init _mxc_timer_init(int irq, ...@@ -312,10 +317,22 @@ static void __init _mxc_timer_init(int irq,
__raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TCTL);
__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
if (timer_is_v2()) if (timer_is_v2()) {
tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
else if (clk_get_rate(clk_per) == V2_TIMER_RATE_OSC_DIV8) {
tctl_val |= V2_TCTL_CLK_OSC_DIV8;
if (cpu_is_imx6dl() || cpu_is_imx6sx()) {
/* 24 / 8 = 3 MHz */
__raw_writel(7 << V2_TPRER_PRE24M,
timer_base + MXC_TPRER);
tctl_val |= V2_TCTL_24MEN;
}
} else {
tctl_val |= V2_TCTL_CLK_PER;
}
} else {
tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
}
__raw_writel(tctl_val, timer_base + MXC_TCTL); __raw_writel(tctl_val, timer_base + MXC_TCTL);
...@@ -349,9 +366,13 @@ static void __init mxc_timer_init_dt(struct device_node *np) ...@@ -349,9 +366,13 @@ static void __init mxc_timer_init_dt(struct device_node *np)
WARN_ON(!timer_base); WARN_ON(!timer_base);
irq = irq_of_parse_and_map(np, 0); irq = irq_of_parse_and_map(np, 0);
clk_per = of_clk_get_by_name(np, "per");
clk_ipg = of_clk_get_by_name(np, "ipg"); clk_ipg = of_clk_get_by_name(np, "ipg");
/* Try osc_per first, and fall back to per otherwise */
clk_per = of_clk_get_by_name(np, "osc_per");
if (IS_ERR(clk_per))
clk_per = of_clk_get_by_name(np, "per");
_mxc_timer_init(irq, clk_per, clk_ipg); _mxc_timer_init(irq, clk_per, clk_ipg);
} }
CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt); CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt);
......
drivers/mfd/da9055-core.c
View file @ 9cd70164
...@@ -296,73 +296,73 @@ static struct resource da9055_ld05_6_resource = { ...@@ -296,73 +296,73 @@ static struct resource da9055_ld05_6_resource = {
static const struct mfd_cell da9055_devs[] = { static const struct mfd_cell da9055_devs[] = {
{ {
.of_compatible = "dialog,da9055-gpio", .of_compatible = "dlg,da9055-gpio",
.name = "da9055-gpio", .name = "da9055-gpio",
}, },
{ {
.of_compatible = "dialog,da9055-regulator", .of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator", .name = "da9055-regulator",
.id = 1, .id = 1,
}, },
{ {
.of_compatible = "dialog,da9055-regulator", .of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator", .name = "da9055-regulator",
.id = 2, .id = 2,
}, },
{ {
.of_compatible = "dialog,da9055-regulator", .of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator", .name = "da9055-regulator",
.id = 3, .id = 3,
}, },
{ {
.of_compatible = "dialog,da9055-regulator", .of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator", .name = "da9055-regulator",
.id = 4, .id = 4,
}, },
{ {
.of_compatible = "dialog,da9055-regulator", .of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator", .name = "da9055-regulator",
.id = 5, .id = 5,
}, },
{ {
.of_compatible = "dialog,da9055-regulator", .of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator", .name = "da9055-regulator",
.id = 6, .id = 6,
}, },
{ {
.of_compatible = "dialog,da9055-regulator", .of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator", .name = "da9055-regulator",
.id = 7, .id = 7,
.resources = &da9055_ld05_6_resource, .resources = &da9055_ld05_6_resource,
.num_resources = 1, .num_resources = 1,
}, },
{ {
.of_compatible = "dialog,da9055-regulator", .of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator", .name = "da9055-regulator",
.resources = &da9055_ld05_6_resource, .resources = &da9055_ld05_6_resource,
.num_resources = 1, .num_resources = 1,
.id = 8, .id = 8,
}, },
{ {
.of_compatible = "dialog,da9055-onkey", .of_compatible = "dlg,da9055-onkey",
.name = "da9055-onkey", .name = "da9055-onkey",
.resources = &da9055_onkey_resource, .resources = &da9055_onkey_resource,
.num_resources = 1, .num_resources = 1,
}, },
{ {
.of_compatible = "dialog,da9055-rtc", .of_compatible = "dlg,da9055-rtc",
.name = "da9055-rtc", .name = "da9055-rtc",
.resources = da9055_rtc_resource, .resources = da9055_rtc_resource,
.num_resources = ARRAY_SIZE(da9055_rtc_resource), .num_resources = ARRAY_SIZE(da9055_rtc_resource),
}, },
{ {
.of_compatible = "dialog,da9055-hwmon", .of_compatible = "dlg,da9055-hwmon",
.name = "da9055-hwmon", .name = "da9055-hwmon",
.resources = &da9055_hwmon_resource, .resources = &da9055_hwmon_resource,
.num_resources = 1, .num_resources = 1,
}, },
{ {
.of_compatible = "dialog,da9055-watchdog", .of_compatible = "dlg,da9055-watchdog",
.name = "da9055-watchdog", .name = "da9055-watchdog",
}, },
}; };
......
include/dt-bindings/clock/imx6qdl-clock.h
View file @ 9cd70164
...@@ -128,7 +128,7 @@ ...@@ -128,7 +128,7 @@
#define IMX6Q_CLK_ECSPI5 116 #define IMX6Q_CLK_ECSPI5 116
#define IMX6DL_CLK_I2C4 116 #define IMX6DL_CLK_I2C4 116
#define IMX6QDL_CLK_ENET 117 #define IMX6QDL_CLK_ENET 117
#define IMX6QDL_CLK_ESAI 118 #define IMX6QDL_CLK_ESAI_EXTAL 118
#define IMX6QDL_CLK_GPT_IPG 119 #define IMX6QDL_CLK_GPT_IPG 119
#define IMX6QDL_CLK_GPT_IPG_PER 120 #define IMX6QDL_CLK_GPT_IPG_PER 120
#define IMX6QDL_CLK_GPU2D_CORE 121 #define IMX6QDL_CLK_GPU2D_CORE 121
...@@ -218,7 +218,36 @@ ...@@ -218,7 +218,36 @@
#define IMX6QDL_CLK_LVDS2_SEL 205 #define IMX6QDL_CLK_LVDS2_SEL 205
#define IMX6QDL_CLK_LVDS1_GATE 206 #define IMX6QDL_CLK_LVDS1_GATE 206
#define IMX6QDL_CLK_LVDS2_GATE 207 #define IMX6QDL_CLK_LVDS2_GATE 207
#define IMX6QDL_CLK_ESAI_AHB 208 #define IMX6QDL_CLK_ESAI_IPG 208
#define IMX6QDL_CLK_END 209 #define IMX6QDL_CLK_ESAI_MEM 209
#define IMX6QDL_CLK_ASRC_IPG 210
#define IMX6QDL_CLK_ASRC_MEM 211
#define IMX6QDL_CLK_LVDS1_IN 212
#define IMX6QDL_CLK_LVDS2_IN 213
#define IMX6QDL_CLK_ANACLK1 214
#define IMX6QDL_CLK_ANACLK2 215
#define IMX6QDL_PLL1_BYPASS_SRC 216
#define IMX6QDL_PLL2_BYPASS_SRC 217
#define IMX6QDL_PLL3_BYPASS_SRC 218
#define IMX6QDL_PLL4_BYPASS_SRC 219
#define IMX6QDL_PLL5_BYPASS_SRC 220
#define IMX6QDL_PLL6_BYPASS_SRC 221
#define IMX6QDL_PLL7_BYPASS_SRC 222
#define IMX6QDL_CLK_PLL1 223
#define IMX6QDL_CLK_PLL2 224
#define IMX6QDL_CLK_PLL3 225
#define IMX6QDL_CLK_PLL4 226
#define IMX6QDL_CLK_PLL5 227
#define IMX6QDL_CLK_PLL6 228
#define IMX6QDL_CLK_PLL7 229
#define IMX6QDL_PLL1_BYPASS 230
#define IMX6QDL_PLL2_BYPASS 231
#define IMX6QDL_PLL3_BYPASS 232
#define IMX6QDL_PLL4_BYPASS 233
#define IMX6QDL_PLL5_BYPASS 234
#define IMX6QDL_PLL6_BYPASS 235
#define IMX6QDL_PLL7_BYPASS 236
#define IMX6QDL_CLK_GPT_3M 237
#define IMX6QDL_CLK_END 238
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
include/dt-bindings/clock/imx6sl-clock.h
View file @ 9cd70164
...@@ -146,6 +146,34 @@ ...@@ -146,6 +146,34 @@
#define IMX6SL_CLK_PLL4_AUDIO_DIV 133 #define IMX6SL_CLK_PLL4_AUDIO_DIV 133
#define IMX6SL_CLK_SPBA 134 #define IMX6SL_CLK_SPBA 134
#define IMX6SL_CLK_ENET 135 #define IMX6SL_CLK_ENET 135
#define IMX6SL_CLK_END 136 #define IMX6SL_CLK_LVDS1_SEL 136
#define IMX6SL_CLK_LVDS1_OUT 137
#define IMX6SL_CLK_LVDS1_IN 138
#define IMX6SL_CLK_ANACLK1 139
#define IMX6SL_PLL1_BYPASS_SRC 140
#define IMX6SL_PLL2_BYPASS_SRC 141
#define IMX6SL_PLL3_BYPASS_SRC 142
#define IMX6SL_PLL4_BYPASS_SRC 143
#define IMX6SL_PLL5_BYPASS_SRC 144
#define IMX6SL_PLL6_BYPASS_SRC 145
#define IMX6SL_PLL7_BYPASS_SRC 146
#define IMX6SL_CLK_PLL1 147
#define IMX6SL_CLK_PLL2 148
#define IMX6SL_CLK_PLL3 149
#define IMX6SL_CLK_PLL4 150
#define IMX6SL_CLK_PLL5 151
#define IMX6SL_CLK_PLL6 152
#define IMX6SL_CLK_PLL7 153
#define IMX6SL_PLL1_BYPASS 154
#define IMX6SL_PLL2_BYPASS 155
#define IMX6SL_PLL3_BYPASS 156
#define IMX6SL_PLL4_BYPASS 157
#define IMX6SL_PLL5_BYPASS 158
#define IMX6SL_PLL6_BYPASS 159
#define IMX6SL_PLL7_BYPASS 160
#define IMX6SL_CLK_SSI1_IPG 161
#define IMX6SL_CLK_SSI2_IPG 162
#define IMX6SL_CLK_SSI3_IPG 163
#define IMX6SL_CLK_END 164
#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
include/dt-bindings/clock/imx6sx-clock.h
View file @ 9cd70164
...@@ -251,6 +251,29 @@ ...@@ -251,6 +251,29 @@
#define IMX6SX_CLK_SAI2_IPG 238 #define IMX6SX_CLK_SAI2_IPG 238
#define IMX6SX_CLK_ESAI_IPG 239 #define IMX6SX_CLK_ESAI_IPG 239
#define IMX6SX_CLK_ESAI_MEM 240 #define IMX6SX_CLK_ESAI_MEM 240
#define IMX6SX_CLK_CLK_END 241 #define IMX6SX_CLK_LVDS1_IN 241
#define IMX6SX_CLK_ANACLK1 242
#define IMX6SX_PLL1_BYPASS_SRC 243
#define IMX6SX_PLL2_BYPASS_SRC 244
#define IMX6SX_PLL3_BYPASS_SRC 245
#define IMX6SX_PLL4_BYPASS_SRC 246
#define IMX6SX_PLL5_BYPASS_SRC 247
#define IMX6SX_PLL6_BYPASS_SRC 248
#define IMX6SX_PLL7_BYPASS_SRC 249
#define IMX6SX_CLK_PLL1 250
#define IMX6SX_CLK_PLL2 251
#define IMX6SX_CLK_PLL3 252
#define IMX6SX_CLK_PLL4 253
#define IMX6SX_CLK_PLL5 254
#define IMX6SX_CLK_PLL6 255
#define IMX6SX_CLK_PLL7 256
#define IMX6SX_PLL1_BYPASS 257
#define IMX6SX_PLL2_BYPASS 258
#define IMX6SX_PLL3_BYPASS 259
#define IMX6SX_PLL4_BYPASS 260
#define IMX6SX_PLL5_BYPASS 261
#define IMX6SX_PLL6_BYPASS 262
#define IMX6SX_PLL7_BYPASS 263
#define IMX6SX_CLK_CLK_END 264
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
include/dt-bindings/clock/vf610-clock.h
View file @ 9cd70164
...@@ -166,6 +166,9 @@ ...@@ -166,6 +166,9 @@
#define VF610_CLK_DMAMUX3 153 #define VF610_CLK_DMAMUX3 153
#define VF610_CLK_FLEXCAN0_EN 154 #define VF610_CLK_FLEXCAN0_EN 154
#define VF610_CLK_FLEXCAN1_EN 155 #define VF610_CLK_FLEXCAN1_EN 155
#define VF610_CLK_END 156 #define VF610_CLK_PLL7_MAIN 156
#define VF610_CLK_USBPHY0 157
#define VF610_CLK_USBPHY1 158
#define VF610_CLK_END 159
#endif /* __DT_BINDINGS_CLOCK_VF610_H */ #endif /* __DT_BINDINGS_CLOCK_VF610_H */
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