Commit 9e259f93 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM 32-bit SoC platform updates from Olof Johansson:
 "Most of the SoC updates in this cycle are cleanups and moves to more
  modern infrastructure:

   - Davinci was moved to common clock framework

   - OMAP1-based Amstrad E3 "Superphone" saw a bunch of cleanups to the
     keyboard interface (bitbanged AT keyboard via GPIO).

   - Removal of some stale code for Renesas platforms

   - Power management improvements for i.MX6LL"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (112 commits)
  ARM: uniphier: select RESET_CONTROLLER
  arm64: uniphier: select RESET_CONTROLLER
  ARM: uniphier: remove empty Makefile
  ARM: exynos: Clear global variable on init error path
  ARM: exynos: Remove outdated maintainer information
  ARM: shmobile: Always enable ARCH_TIMER on SoCs with A7 and/or A15
  ARM: shmobile: r8a7779: hide unused r8a7779_platform_cpu_kill
  soc: r9a06g032: don't build SMP files for non-SMP config
  ARM: shmobile: Add the R9A06G032 SMP enabler driver
  ARM: at91: pm: configure wakeup sources for ULP1 mode
  ARM: at91: pm: add PMC fast startup registers defines
  ARM: at91: pm: Add ULP1 mode support
  ARM: at91: pm: Use ULP0 naming instead of slow clock
  ARM: hisi: handle of_iomap and fix missing of_node_put
  ARM: hisi: check of_iomap and fix missing of_node_put
  ARM: hisi: fix error handling and missing of_node_put
  ARM: mx5: Set the DBGEN bit in ARM_GPC register
  ARM: imx51: Configure M4IF to avoid visual artifacts
  ARM: imx: call imx6sx_cpuidle_init() conditionally for 6sll
  ARM: imx: fix i.MX6SLL build
  ...
parents 5563ae9b f0fc40af
...@@ -1295,11 +1295,6 @@ F: arch/arm/mach-aspeed/ ...@@ -1295,11 +1295,6 @@ F: arch/arm/mach-aspeed/
F: arch/arm/boot/dts/aspeed-* F: arch/arm/boot/dts/aspeed-*
N: aspeed N: aspeed
ARM/ATMEL AT91 Clock Support
M: Boris Brezillon <boris.brezillon@bootlin.com>
S: Maintained
F: drivers/clk/at91
ARM/CALXEDA HIGHBANK ARCHITECTURE ARM/CALXEDA HIGHBANK ARCHITECTURE
M: Rob Herring <robh@kernel.org> M: Rob Herring <robh@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
...@@ -1481,6 +1476,16 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git ...@@ -1481,6 +1476,16 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
F: arch/arm/mach-imx/*vf610* F: arch/arm/mach-imx/*vf610*
F: arch/arm/boot/dts/vf* F: arch/arm/boot/dts/vf*
ARM/FREESCALE LAYERSCAPE ARM ARCHITECTURE
M: Shawn Guo <shawnguo@kernel.org>
M: Li Yang <leoyang.li@nxp.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
F: arch/arm/boot/dts/ls1021a*
F: arch/arm64/boot/dts/freescale/fsl-*
F: arch/arm64/boot/dts/freescale/qoriq-*
ARM/GLOMATION GESBC9312SX MACHINE SUPPORT ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org> M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
...@@ -10571,6 +10576,7 @@ F: arch/arm/plat-omap/ ...@@ -10571,6 +10576,7 @@ F: arch/arm/plat-omap/
F: arch/arm/configs/omap1_defconfig F: arch/arm/configs/omap1_defconfig
F: drivers/i2c/busses/i2c-omap.c F: drivers/i2c/busses/i2c-omap.c
F: include/linux/platform_data/i2c-omap.h F: include/linux/platform_data/i2c-omap.h
F: include/linux/platform_data/ams-delta-fiq.h
OMAP2+ SUPPORT OMAP2+ SUPPORT
M: Tony Lindgren <tony@atomide.com> M: Tony Lindgren <tony@atomide.com>
......
...@@ -603,13 +603,16 @@ config ARCH_S3C24XX ...@@ -603,13 +603,16 @@ config ARCH_S3C24XX
config ARCH_DAVINCI config ARCH_DAVINCI
bool "TI DaVinci" bool "TI DaVinci"
select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_HAS_HOLES_MEMORYMODEL
select CLKDEV_LOOKUP select COMMON_CLK
select CPU_ARM926T select CPU_ARM926T
select GENERIC_ALLOCATOR select GENERIC_ALLOCATOR
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP select GENERIC_IRQ_CHIP
select GPIOLIB select GPIOLIB
select HAVE_IDE select HAVE_IDE
select PM_GENERIC_DOMAINS if PM
select PM_GENERIC_DOMAINS_OF if PM && OF
select RESET_CONTROLLER
select USE_OF select USE_OF
select ZONE_DMA select ZONE_DMA
help help
......
...@@ -204,6 +204,14 @@ choice ...@@ -204,6 +204,14 @@ choice
depends on ARCH_BCM_HR2 depends on ARCH_BCM_HR2
select DEBUG_UART_8250 select DEBUG_UART_8250
config DEBUG_BCM_IPROC_UART3
bool "Kernel low-level debugging on BCM IPROC UART3"
depends on ARCH_BCM_CYGNUS
select DEBUG_UART_8250
help
Say Y here if you want the debug print routines to direct
their output to the third serial port on these devices.
config DEBUG_BCM_KONA_UART config DEBUG_BCM_KONA_UART
bool "Kernel low-level debugging messages via BCM KONA UART" bool "Kernel low-level debugging messages via BCM KONA UART"
depends on ARCH_BCM_MOBILE depends on ARCH_BCM_MOBILE
...@@ -1562,14 +1570,15 @@ config DEBUG_UART_PHYS ...@@ -1562,14 +1570,15 @@ config DEBUG_UART_PHYS
default 0x18000400 if DEBUG_BCM_HR2 default 0x18000400 if DEBUG_BCM_HR2
default 0x18010000 if DEBUG_SIRFATLAS7_UART0 default 0x18010000 if DEBUG_SIRFATLAS7_UART0
default 0x18020000 if DEBUG_SIRFATLAS7_UART1 default 0x18020000 if DEBUG_SIRFATLAS7_UART1
default 0x18023000 if DEBUG_BCM_IPROC_UART3
default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1 default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
default 0x20001000 if DEBUG_HIP01_UART default 0x20001000 if DEBUG_HIP01_UART
default 0x20060000 if DEBUG_RK29_UART0 default 0x20060000 if DEBUG_RK29_UART0
default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
default 0x20068000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3 default 0x20068000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
default 0x20201000 if DEBUG_BCM2835 default 0x20201000 if DEBUG_BCM2835
default 0x3f201000 if DEBUG_BCM2836
default 0x3e000000 if DEBUG_BCM_KONA_UART default 0x3e000000 if DEBUG_BCM_KONA_UART
default 0x3f201000 if DEBUG_BCM2836
default 0x4000e400 if DEBUG_LL_UART_EFM32 default 0x4000e400 if DEBUG_LL_UART_EFM32
default 0x40028000 if DEBUG_AT91_SAMV7_USART1 default 0x40028000 if DEBUG_AT91_SAMV7_USART1
default 0x40081000 if DEBUG_LPC18XX_UART0 default 0x40081000 if DEBUG_LPC18XX_UART0
...@@ -1682,6 +1691,7 @@ config DEBUG_UART_VIRT ...@@ -1682,6 +1691,7 @@ config DEBUG_UART_VIRT
default 0xf1002000 if DEBUG_MT8127_UART0 default 0xf1002000 if DEBUG_MT8127_UART0
default 0xf1006000 if DEBUG_MT6589_UART0 default 0xf1006000 if DEBUG_MT6589_UART0
default 0xf1009000 if DEBUG_MT8135_UART3 default 0xf1009000 if DEBUG_MT8135_UART3
default 0xf1023000 if DEBUG_BCM_IPROC_UART3
default 0xf11f1000 if DEBUG_VERSATILE default 0xf11f1000 if DEBUG_VERSATILE
default 0xf1600000 if DEBUG_INTEGRATOR default 0xf1600000 if DEBUG_INTEGRATOR
default 0xf1c28000 if DEBUG_SUNXI_UART0 default 0xf1c28000 if DEBUG_SUNXI_UART0
...@@ -1797,7 +1807,7 @@ config DEBUG_UART_8250_WORD ...@@ -1797,7 +1807,7 @@ config DEBUG_UART_8250_WORD
DEBUG_KEYSTONE_UART0 || DEBUG_KEYSTONE_UART1 || \ DEBUG_KEYSTONE_UART0 || DEBUG_KEYSTONE_UART1 || \
DEBUG_ALPINE_UART0 || \ DEBUG_ALPINE_UART0 || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \ DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
DEBUG_DAVINCI_DA8XX_UART2 || \ DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_BCM_IPROC_UART3 || \
DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2
config DEBUG_UART_8250_PALMCHIP config DEBUG_UART_8250_PALMCHIP
......
...@@ -219,7 +219,6 @@ machine-$(CONFIG_ARCH_TANGO) += tango ...@@ -219,7 +219,6 @@ machine-$(CONFIG_ARCH_TANGO) += tango
machine-$(CONFIG_ARCH_TEGRA) += tegra machine-$(CONFIG_ARCH_TEGRA) += tegra
machine-$(CONFIG_ARCH_U300) += u300 machine-$(CONFIG_ARCH_U300) += u300
machine-$(CONFIG_ARCH_U8500) += ux500 machine-$(CONFIG_ARCH_U8500) += ux500
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_VERSATILE) += versatile machine-$(CONFIG_ARCH_VERSATILE) += versatile
machine-$(CONFIG_ARCH_VEXPRESS) += vexpress machine-$(CONFIG_ARCH_VEXPRESS) += vexpress
machine-$(CONFIG_ARCH_VT8500) += vt8500 machine-$(CONFIG_ARCH_VT8500) += vt8500
......
...@@ -31,21 +31,25 @@ ...@@ -31,21 +31,25 @@
static unsigned long cpu_boot_addr; static unsigned long cpu_boot_addr;
static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2) static void tf_generic_smc(u32 type, u32 arg1, u32 arg2)
{ {
register u32 r0 asm("r0") = type;
register u32 r1 asm("r1") = arg1;
register u32 r2 asm("r2") = arg2;
asm volatile( asm volatile(
".arch_extension sec\n\t" ".arch_extension sec\n\t"
"stmfd sp!, {r4 - r11, lr}\n\t" "stmfd sp!, {r4 - r11}\n\t"
__asmeq("%0", "r0") __asmeq("%0", "r0")
__asmeq("%1", "r1") __asmeq("%1", "r1")
__asmeq("%2", "r2") __asmeq("%2", "r2")
"mov r3, #0\n\t" "mov r3, #0\n\t"
"mov r4, #0\n\t" "mov r4, #0\n\t"
"smc #0\n\t" "smc #0\n\t"
"ldmfd sp!, {r4 - r11, pc}" "ldmfd sp!, {r4 - r11}\n\t"
: :
: "r" (type), "r" (arg1), "r" (arg2) : "r" (r0), "r" (r1), "r" (r2)
: "memory"); : "memory", "r3", "r12", "lr");
} }
static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr) static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
......
/* SPDX-License-Identifier: GPL-2.0 */
/* /*
* Renesas SCIF(A) debugging macro include header * Renesas SCIF(A) debugging macro include header
* *
...@@ -5,10 +6,6 @@ ...@@ -5,10 +6,6 @@
* *
* Copyright (C) 2012-2013 Renesas Electronics Corporation * Copyright (C) 2012-2013 Renesas Electronics Corporation
* Copyright (C) 1994-1999 Russell King * Copyright (C) 1994-1999 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/ */
#define SCIF_PHYS CONFIG_DEBUG_UART_PHYS #define SCIF_PHYS CONFIG_DEBUG_UART_PHYS
......
...@@ -40,15 +40,16 @@ extern void at91_pinctrl_gpio_resume(void); ...@@ -40,15 +40,16 @@ extern void at91_pinctrl_gpio_resume(void);
#endif #endif
static const match_table_t pm_modes __initconst = { static const match_table_t pm_modes __initconst = {
{ 0, "standby" }, { AT91_PM_STANDBY, "standby" },
{ AT91_PM_SLOW_CLOCK, "ulp0" }, { AT91_PM_ULP0, "ulp0" },
{ AT91_PM_ULP1, "ulp1" },
{ AT91_PM_BACKUP, "backup" }, { AT91_PM_BACKUP, "backup" },
{ -1, NULL }, { -1, NULL },
}; };
static struct at91_pm_data pm_data = { static struct at91_pm_data pm_data = {
.standby_mode = 0, .standby_mode = AT91_PM_STANDBY,
.suspend_mode = AT91_PM_SLOW_CLOCK, .suspend_mode = AT91_PM_ULP0,
}; };
#define at91_ramc_read(id, field) \ #define at91_ramc_read(id, field) \
...@@ -79,6 +80,90 @@ static struct at91_pm_bu { ...@@ -79,6 +80,90 @@ static struct at91_pm_bu {
phys_addr_t resume; phys_addr_t resume;
} *pm_bu; } *pm_bu;
struct wakeup_source_info {
unsigned int pmc_fsmr_bit;
unsigned int shdwc_mr_bit;
bool set_polarity;
};
static const struct wakeup_source_info ws_info[] = {
{ .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
{ .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
{ .pmc_fsmr_bit = AT91_PMC_USBAL },
{ .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
};
static const struct of_device_id sama5d2_ws_ids[] = {
{ .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
{ .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] },
{ .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
{ .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
{ .compatible = "usb-ohci", .data = &ws_info[2] },
{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
{ .compatible = "usb-ehci", .data = &ws_info[2] },
{ .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
{ /* sentinel */ }
};
static int at91_pm_config_ws(unsigned int pm_mode, bool set)
{
const struct wakeup_source_info *wsi;
const struct of_device_id *match;
struct platform_device *pdev;
struct device_node *np;
unsigned int mode = 0, polarity = 0, val = 0;
if (pm_mode != AT91_PM_ULP1)
return 0;
if (!pm_data.pmc || !pm_data.shdwc)
return -EPERM;
if (!set) {
writel(mode, pm_data.pmc + AT91_PMC_FSMR);
return 0;
}
/* SHDWC.WUIR */
val = readl(pm_data.shdwc + 0x0c);
mode |= (val & 0x3ff);
polarity |= ((val >> 16) & 0x3ff);
/* SHDWC.MR */
val = readl(pm_data.shdwc + 0x04);
/* Loop through defined wakeup sources. */
for_each_matching_node_and_match(np, sama5d2_ws_ids, &match) {
pdev = of_find_device_by_node(np);
if (!pdev)
continue;
if (device_may_wakeup(&pdev->dev)) {
wsi = match->data;
/* Check if enabled on SHDWC. */
if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
goto put_node;
mode |= wsi->pmc_fsmr_bit;
if (wsi->set_polarity)
polarity |= wsi->pmc_fsmr_bit;
}
put_node:
of_node_put(np);
}
if (mode) {
writel(mode, pm_data.pmc + AT91_PMC_FSMR);
writel(polarity, pm_data.pmc + AT91_PMC_FSPR);
} else {
pr_err("AT91: PM: no ULP1 wakeup sources found!");
}
return mode ? 0 : -EPERM;
}
/* /*
* Called after processes are frozen, but before we shutdown devices. * Called after processes are frozen, but before we shutdown devices.
*/ */
...@@ -97,7 +182,7 @@ static int at91_pm_begin(suspend_state_t state) ...@@ -97,7 +182,7 @@ static int at91_pm_begin(suspend_state_t state)
pm_data.mode = -1; pm_data.mode = -1;
} }
return 0; return at91_pm_config_ws(pm_data.mode, true);
} }
/* /*
...@@ -145,7 +230,7 @@ static int at91_pm_verify_clocks(void) ...@@ -145,7 +230,7 @@ static int at91_pm_verify_clocks(void)
*/ */
int at91_suspend_entering_slow_clock(void) int at91_suspend_entering_slow_clock(void)
{ {
return (pm_data.mode >= AT91_PM_SLOW_CLOCK); return (pm_data.mode >= AT91_PM_ULP0);
} }
EXPORT_SYMBOL(at91_suspend_entering_slow_clock); EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
...@@ -186,7 +271,7 @@ static void at91_pm_suspend(suspend_state_t state) ...@@ -186,7 +271,7 @@ static void at91_pm_suspend(suspend_state_t state)
* event sources; and reduces DRAM power. But otherwise it's identical to * event sources; and reduces DRAM power. But otherwise it's identical to
* PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks. * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
* *
* AT91_PM_SLOW_CLOCK is like STANDBY plus slow clock mode, so drivers must * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
* suspend more deeply, the master clock switches to the clk32k and turns off * suspend more deeply, the master clock switches to the clk32k and turns off
* the main oscillator * the main oscillator
* *
...@@ -204,7 +289,7 @@ static int at91_pm_enter(suspend_state_t state) ...@@ -204,7 +289,7 @@ static int at91_pm_enter(suspend_state_t state)
/* /*
* Ensure that clocks are in a valid state. * Ensure that clocks are in a valid state.
*/ */
if ((pm_data.mode >= AT91_PM_SLOW_CLOCK) && if (pm_data.mode >= AT91_PM_ULP0 &&
!at91_pm_verify_clocks()) !at91_pm_verify_clocks())
goto error; goto error;
...@@ -233,6 +318,7 @@ static int at91_pm_enter(suspend_state_t state) ...@@ -233,6 +318,7 @@ static int at91_pm_enter(suspend_state_t state)
*/ */
static void at91_pm_end(void) static void at91_pm_end(void)
{ {
at91_pm_config_ws(pm_data.mode, false);
} }
...@@ -478,31 +564,28 @@ static void __init at91_pm_sram_init(void) ...@@ -478,31 +564,28 @@ static void __init at91_pm_sram_init(void)
&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
} }
static void __init at91_pm_backup_init(void) static bool __init at91_is_pm_mode_active(int pm_mode)
{
return (pm_data.standby_mode == pm_mode ||
pm_data.suspend_mode == pm_mode);
}
static int __init at91_pm_backup_init(void)
{ {
struct gen_pool *sram_pool; struct gen_pool *sram_pool;
struct device_node *np; struct device_node *np;
struct platform_device *pdev = NULL; struct platform_device *pdev = NULL;
int ret = -ENODEV;
if ((pm_data.standby_mode != AT91_PM_BACKUP) && if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
(pm_data.suspend_mode != AT91_PM_BACKUP)) return 0;
return;
pm_bu = NULL; pm_bu = NULL;
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc");
if (!np) {
pr_warn("%s: failed to find shdwc!\n", __func__);
return;
}
pm_data.shdwc = of_iomap(np, 0);
of_node_put(np);
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
if (!np) { if (!np) {
pr_warn("%s: failed to find sfrbu!\n", __func__); pr_warn("%s: failed to find sfrbu!\n", __func__);
goto sfrbu_fail; return ret;
} }
pm_data.sfrbu = of_iomap(np, 0); pm_data.sfrbu = of_iomap(np, 0);
...@@ -529,6 +612,7 @@ static void __init at91_pm_backup_init(void) ...@@ -529,6 +612,7 @@ static void __init at91_pm_backup_init(void)
pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
if (!pm_bu) { if (!pm_bu) {
pr_warn("%s: unable to alloc securam!\n", __func__); pr_warn("%s: unable to alloc securam!\n", __func__);
ret = -ENOMEM;
goto securam_fail; goto securam_fail;
} }
...@@ -536,19 +620,60 @@ static void __init at91_pm_backup_init(void) ...@@ -536,19 +620,60 @@ static void __init at91_pm_backup_init(void)
pm_bu->canary = __pa_symbol(&canary); pm_bu->canary = __pa_symbol(&canary);
pm_bu->resume = __pa_symbol(cpu_resume); pm_bu->resume = __pa_symbol(cpu_resume);
return; return 0;
sfrbu_fail:
iounmap(pm_data.shdwc);
pm_data.shdwc = NULL;
securam_fail: securam_fail:
iounmap(pm_data.sfrbu); iounmap(pm_data.sfrbu);
pm_data.sfrbu = NULL; pm_data.sfrbu = NULL;
return ret;
}
if (pm_data.standby_mode == AT91_PM_BACKUP) static void __init at91_pm_use_default_mode(int pm_mode)
pm_data.standby_mode = AT91_PM_SLOW_CLOCK; {
if (pm_data.suspend_mode == AT91_PM_BACKUP) if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP)
pm_data.suspend_mode = AT91_PM_SLOW_CLOCK; return;
if (pm_data.standby_mode == pm_mode)
pm_data.standby_mode = AT91_PM_ULP0;
if (pm_data.suspend_mode == pm_mode)
pm_data.suspend_mode = AT91_PM_ULP0;
}
static void __init at91_pm_modes_init(void)
{
struct device_node *np;
int ret;
if (!at91_is_pm_mode_active(AT91_PM_BACKUP) &&
!at91_is_pm_mode_active(AT91_PM_ULP1))
return;
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc");
if (!np) {
pr_warn("%s: failed to find shdwc!\n", __func__);
goto ulp1_default;
}
pm_data.shdwc = of_iomap(np, 0);
of_node_put(np);
ret = at91_pm_backup_init();
if (ret) {
if (!at91_is_pm_mode_active(AT91_PM_ULP1))
goto unmap;
else
goto backup_default;
}
return;
unmap:
iounmap(pm_data.shdwc);
pm_data.shdwc = NULL;
ulp1_default:
at91_pm_use_default_mode(AT91_PM_ULP1);
backup_default:
at91_pm_use_default_mode(AT91_PM_BACKUP);
} }
struct pmc_info { struct pmc_info {
...@@ -644,7 +769,7 @@ void __init sama5d2_pm_init(void) ...@@ -644,7 +769,7 @@ void __init sama5d2_pm_init(void)
if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
return; return;
at91_pm_backup_init(); at91_pm_modes_init();
sama5_pm_init(); sama5_pm_init();
} }
......
...@@ -21,8 +21,10 @@ ...@@ -21,8 +21,10 @@
#define AT91_MEMCTRL_SDRAMC 1 #define AT91_MEMCTRL_SDRAMC 1
#define AT91_MEMCTRL_DDRSDR 2 #define AT91_MEMCTRL_DDRSDR 2
#define AT91_PM_SLOW_CLOCK 0x01 #define AT91_PM_STANDBY 0x00
#define AT91_PM_BACKUP 0x02 #define AT91_PM_ULP0 0x01
#define AT91_PM_ULP1 0x02
#define AT91_PM_BACKUP 0x03
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
struct at91_pm_data { struct at91_pm_data {
......
...@@ -41,6 +41,15 @@ tmp2 .req r5 ...@@ -41,6 +41,15 @@ tmp2 .req r5
beq 1b beq 1b
.endm .endm
/*
* Wait for main oscillator selection is done
*/
.macro wait_moscsels
1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MOSCSELS
beq 1b
.endm
/* /*
* Wait until PLLA has locked. * Wait until PLLA has locked.
*/ */
...@@ -112,19 +121,20 @@ ENTRY(at91_pm_suspend_in_sram) ...@@ -112,19 +121,20 @@ ENTRY(at91_pm_suspend_in_sram)
bl at91_sramc_self_refresh bl at91_sramc_self_refresh
ldr r0, .pm_mode ldr r0, .pm_mode
cmp r0, #AT91_PM_SLOW_CLOCK cmp r0, #AT91_PM_STANDBY
beq slow_clock beq standby
cmp r0, #AT91_PM_BACKUP cmp r0, #AT91_PM_BACKUP
beq backup_mode beq backup_mode
bl at91_ulp_mode
b exit_suspend
standby:
/* Wait for interrupt */ /* Wait for interrupt */
ldr pmc, .pmc_base ldr pmc, .pmc_base
at91_cpu_idle at91_cpu_idle
b exit_suspend b exit_suspend
slow_clock:
bl at91_slowck_mode
b exit_suspend
backup_mode: backup_mode:
bl at91_backup_mode bl at91_backup_mode
b exit_suspend b exit_suspend
...@@ -151,7 +161,102 @@ ENTRY(at91_backup_mode) ...@@ -151,7 +161,102 @@ ENTRY(at91_backup_mode)
str tmp1, [r0, #0] str tmp1, [r0, #0]
ENDPROC(at91_backup_mode) ENDPROC(at91_backup_mode)
ENTRY(at91_slowck_mode) .macro at91_pm_ulp0_mode
ldr pmc, .pmc_base
/* Turn off the crystal oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
bic tmp1, tmp1, #AT91_PMC_MOSCEN
orr tmp1, tmp1, #AT91_PMC_KEY
str tmp1, [pmc, #AT91_CKGR_MOR]
/* Wait for interrupt */
at91_cpu_idle
/* Turn on the crystal oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
orr tmp1, tmp1, #AT91_PMC_MOSCEN
orr tmp1, tmp1, #AT91_PMC_KEY
str tmp1, [pmc, #AT91_CKGR_MOR]
wait_moscrdy
.endm
/**
* Note: This procedure only applies on the platform which uses
* the external crystal oscillator as a main clock source.
*/
.macro at91_pm_ulp1_mode
ldr pmc, .pmc_base
/* Switch the main clock source to 12-MHz RC oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
bic tmp1, tmp1, #AT91_PMC_MOSCSEL
bic tmp1, tmp1, #AT91_PMC_KEY_MASK
orr tmp1, tmp1, #AT91_PMC_KEY
str tmp1, [pmc, #AT91_CKGR_MOR]
wait_moscsels
/* Disable the crystal oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
bic tmp1, tmp1, #AT91_PMC_MOSCEN
bic tmp1, tmp1, #AT91_PMC_KEY_MASK
orr tmp1, tmp1, #AT91_PMC_KEY
str tmp1, [pmc, #AT91_CKGR_MOR]
/* Switch the master clock source to main clock */
ldr tmp1, [pmc, #AT91_PMC_MCKR]
bic tmp1, tmp1, #AT91_PMC_CSS
orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
str tmp1, [pmc, #AT91_PMC_MCKR]
wait_mckrdy
/* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
orr tmp1, tmp1, #AT91_PMC_WAITMODE
bic tmp1, tmp1, #AT91_PMC_KEY_MASK
orr tmp1, tmp1, #AT91_PMC_KEY
str tmp1, [pmc, #AT91_CKGR_MOR]
wait_mckrdy
/* Enable the crystal oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
orr tmp1, tmp1, #AT91_PMC_MOSCEN
bic tmp1, tmp1, #AT91_PMC_KEY_MASK
orr tmp1, tmp1, #AT91_PMC_KEY
str tmp1, [pmc, #AT91_CKGR_MOR]
wait_moscrdy
/* Switch the master clock source to slow clock */
ldr tmp1, [pmc, #AT91_PMC_MCKR]
bic tmp1, tmp1, #AT91_PMC_CSS
str tmp1, [pmc, #AT91_PMC_MCKR]
wait_mckrdy
/* Switch main clock source to crystal oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
orr tmp1, tmp1, #AT91_PMC_MOSCSEL
bic tmp1, tmp1, #AT91_PMC_KEY_MASK
orr tmp1, tmp1, #AT91_PMC_KEY
str tmp1, [pmc, #AT91_CKGR_MOR]
wait_moscsels
/* Switch the master clock source to main clock */
ldr tmp1, [pmc, #AT91_PMC_MCKR]
bic tmp1, tmp1, #AT91_PMC_CSS
orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
str tmp1, [pmc, #AT91_PMC_MCKR]
wait_mckrdy
.endm
ENTRY(at91_ulp_mode)
ldr pmc, .pmc_base ldr pmc, .pmc_base
/* Save Master clock setting */ /* Save Master clock setting */
...@@ -174,22 +279,19 @@ ENTRY(at91_slowck_mode) ...@@ -174,22 +279,19 @@ ENTRY(at91_slowck_mode)
orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */ orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
str tmp1, [pmc, #AT91_CKGR_PLLAR] str tmp1, [pmc, #AT91_CKGR_PLLAR]
/* Turn off the main oscillator */ ldr r0, .pm_mode
ldr tmp1, [pmc, #AT91_CKGR_MOR] cmp r0, #AT91_PM_ULP1
bic tmp1, tmp1, #AT91_PMC_MOSCEN beq ulp1_mode
orr tmp1, tmp1, #AT91_PMC_KEY
str tmp1, [pmc, #AT91_CKGR_MOR]
/* Wait for interrupt */ at91_pm_ulp0_mode
at91_cpu_idle b ulp_exit
/* Turn on the main oscillator */ ulp1_mode:
ldr tmp1, [pmc, #AT91_CKGR_MOR] at91_pm_ulp1_mode
orr tmp1, tmp1, #AT91_PMC_MOSCEN b ulp_exit
orr tmp1, tmp1, #AT91_PMC_KEY
str tmp1, [pmc, #AT91_CKGR_MOR]
wait_moscrdy ulp_exit:
ldr pmc, .pmc_base
/* Restore PLLA setting */ /* Restore PLLA setting */
ldr tmp1, .saved_pllar ldr tmp1, .saved_pllar
...@@ -212,7 +314,7 @@ ENTRY(at91_slowck_mode) ...@@ -212,7 +314,7 @@ ENTRY(at91_slowck_mode)
wait_mckrdy wait_mckrdy
mov pc, lr mov pc, lr
ENDPROC(at91_slowck_mode) ENDPROC(at91_ulp_mode)
/* /*
* void at91_sramc_self_refresh(unsigned int is_active) * void at91_sramc_self_refresh(unsigned int is_active)
......
...@@ -59,6 +59,7 @@ config MACH_DA8XX_DT ...@@ -59,6 +59,7 @@ config MACH_DA8XX_DT
default y default y
depends on ARCH_DAVINCI_DA850 depends on ARCH_DAVINCI_DA850
select PINCTRL select PINCTRL
select TIMER_OF
help help
Say y here to include support for TI DaVinci DA850 based using Say y here to include support for TI DaVinci DA850 based using
Flattened Device Tree. More information at Documentation/devicetree Flattened Device Tree. More information at Documentation/devicetree
...@@ -231,18 +232,6 @@ config DAVINCI_MUX_WARNINGS ...@@ -231,18 +232,6 @@ config DAVINCI_MUX_WARNINGS
to change the pin multiplexing setup. When there are no warnings to change the pin multiplexing setup. When there are no warnings
printed, it's safe to deselect DAVINCI_MUX for your product. printed, it's safe to deselect DAVINCI_MUX for your product.
config DAVINCI_RESET_CLOCKS
bool "Reset unused clocks during boot"
depends on ARCH_DAVINCI
help
Say Y if you want to reset unused clocks during boot.
This option saves power, but assumes all drivers are
using the clock framework. Broken drivers that do not
yet use clock framework may not work with this option.
If you are booting from another operating system, you
probably do not want this option enabled until your
device drivers work properly.
endmenu endmenu
endif endif
...@@ -5,8 +5,8 @@ ...@@ -5,8 +5,8 @@
# #
# Common objects # Common objects
obj-y := time.o clock.o serial.o psc.o \ obj-y := time.o serial.o usb.o \
usb.o common.o sram.o aemif.o common.o sram.o
obj-$(CONFIG_DAVINCI_MUX) += mux.o obj-$(CONFIG_DAVINCI_MUX) += mux.o
......
/*
* AEMIF support for DaVinci SoCs
*
* Copyright (C) 2010 Texas Instruments Incorporated. http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/time.h>
#include <linux/platform_data/mtd-davinci-aemif.h>
#include <linux/platform_data/mtd-davinci.h>
/* Timing value configuration */
#define TA(x) ((x) << 2)
#define RHOLD(x) ((x) << 4)
#define RSTROBE(x) ((x) << 7)
#define RSETUP(x) ((x) << 13)
#define WHOLD(x) ((x) << 17)
#define WSTROBE(x) ((x) << 20)
#define WSETUP(x) ((x) << 26)
#define TA_MAX 0x3
#define RHOLD_MAX 0x7
#define RSTROBE_MAX 0x3f
#define RSETUP_MAX 0xf
#define WHOLD_MAX 0x7
#define WSTROBE_MAX 0x3f
#define WSETUP_MAX 0xf
#define TIMING_MASK (TA(TA_MAX) | \
RHOLD(RHOLD_MAX) | \
RSTROBE(RSTROBE_MAX) | \
RSETUP(RSETUP_MAX) | \
WHOLD(WHOLD_MAX) | \
WSTROBE(WSTROBE_MAX) | \
WSETUP(WSETUP_MAX))
static inline unsigned int davinci_aemif_readl(void __iomem *base, int offset)
{
return readl_relaxed(base + offset);
}
static inline void davinci_aemif_writel(void __iomem *base,
int offset, unsigned long value)
{
writel_relaxed(value, base + offset);
}
/*
* aemif_calc_rate - calculate timing data.
* @wanted: The cycle time needed in nanoseconds.
* @clk: The input clock rate in kHz.
* @max: The maximum divider value that can be programmed.
*
* On success, returns the calculated timing value minus 1 for easy
* programming into AEMIF timing registers, else negative errno.
*/
static int aemif_calc_rate(int wanted, unsigned long clk, int max)
{
int result;
result = DIV_ROUND_UP((wanted * clk), NSEC_PER_MSEC) - 1;
pr_debug("%s: result %d from %ld, %d\n", __func__, result, clk, wanted);
/* It is generally OK to have a more relaxed timing than requested... */
if (result < 0)
result = 0;
/* ... But configuring tighter timings is not an option. */
else if (result > max)
result = -EINVAL;
return result;
}
/**
* davinci_aemif_setup_timing - setup timing values for a given AEMIF interface
* @t: timing values to be progammed
* @base: The virtual base address of the AEMIF interface
* @cs: chip-select to program the timing values for
* @clkrate: the AEMIF clkrate
*
* This function programs the given timing values (in real clock) into the
* AEMIF registers taking the AEMIF clock into account.
*
* This function does not use any locking while programming the AEMIF
* because it is expected that there is only one user of a given
* chip-select.
*
* Returns 0 on success, else negative errno.
*/
static int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
void __iomem *base, unsigned cs,
unsigned long clkrate)
{
unsigned set, val;
int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
unsigned offset = A1CR_OFFSET + cs * 4;
if (!t)
return 0; /* Nothing to do */
clkrate /= 1000; /* turn clock into kHz for ease of use */
ta = aemif_calc_rate(t->ta, clkrate, TA_MAX);
rhold = aemif_calc_rate(t->rhold, clkrate, RHOLD_MAX);
rstrobe = aemif_calc_rate(t->rstrobe, clkrate, RSTROBE_MAX);
rsetup = aemif_calc_rate(t->rsetup, clkrate, RSETUP_MAX);
whold = aemif_calc_rate(t->whold, clkrate, WHOLD_MAX);
wstrobe = aemif_calc_rate(t->wstrobe, clkrate, WSTROBE_MAX);
wsetup = aemif_calc_rate(t->wsetup, clkrate, WSETUP_MAX);
if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 ||
whold < 0 || wstrobe < 0 || wsetup < 0) {
pr_err("%s: cannot get suitable timings\n", __func__);
return -EINVAL;
}
set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) |
WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup);
val = __raw_readl(base + offset);
val &= ~TIMING_MASK;
val |= set;
__raw_writel(val, base + offset);
return 0;
}
/**
* davinci_aemif_setup - setup AEMIF interface by davinci_nand_pdata
* @pdev - link to platform device to setup settings for
*
* This function does not use any locking while programming the AEMIF
* because it is expected that there is only one user of a given
* chip-select.
*
* Returns 0 on success, else negative errno.
*/
int davinci_aemif_setup(struct platform_device *pdev)
{
struct davinci_nand_pdata *pdata = dev_get_platdata(&pdev->dev);
uint32_t val;
unsigned long clkrate;
struct resource *res;
void __iomem *base;
struct clk *clk;
int ret = 0;
clk = clk_get(&pdev->dev, "aemif");
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
return ret;
}
ret = clk_prepare_enable(clk);
if (ret < 0) {
dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
ret);
goto err_put;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!res) {
dev_err(&pdev->dev, "cannot get IORESOURCE_MEM\n");
ret = -ENOMEM;
goto err;
}
base = ioremap(res->start, resource_size(res));
if (!base) {
dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res);
ret = -ENOMEM;
goto err;
}
/*
* Setup Async configuration register in case we did not boot
* from NAND and so bootloader did not bother to set it up.
*/
val = davinci_aemif_readl(base, A1CR_OFFSET + pdata->core_chipsel * 4);
/*
* Extended Wait is not valid and Select Strobe mode is not
* used
*/
val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK);
if (pdata->options & NAND_BUSWIDTH_16)
val |= 0x1;
davinci_aemif_writel(base, A1CR_OFFSET + pdata->core_chipsel * 4, val);
clkrate = clk_get_rate(clk);
if (pdata->timing)
ret = davinci_aemif_setup_timing(pdata->timing, base,
pdata->core_chipsel, clkrate);
if (ret < 0)
dev_dbg(&pdev->dev, "NAND timing values setup fail\n");
iounmap(base);
err:
clk_disable_unprepare(clk);
err_put:
clk_put(clk);
return ret;
}
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
#include <linux/platform_data/mtd-davinci-aemif.h> #include <linux/platform_data/mtd-davinci-aemif.h>
#include <linux/platform_data/spi-davinci.h> #include <linux/platform_data/spi-davinci.h>
#include <linux/platform_data/usb-davinci.h> #include <linux/platform_data/usb-davinci.h>
#include <linux/platform_data/ti-aemif.h>
#include <linux/regulator/machine.h> #include <linux/regulator/machine.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
...@@ -110,15 +111,9 @@ static __init void da830_evm_usb_init(void) ...@@ -110,15 +111,9 @@ static __init void da830_evm_usb_init(void)
{ {
int ret; int ret;
/* USB_REFCLKIN is not used. */ ret = da8xx_register_usb_phy_clocks();
ret = da8xx_register_usb20_phy_clk(false);
if (ret) if (ret)
pr_warn("%s: USB 2.0 PHY CLK registration failed: %d\n", pr_warn("%s: USB PHY CLK registration failed: %d\n",
__func__, ret);
ret = da8xx_register_usb11_phy_clk(false);
if (ret)
pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n",
__func__, ret); __func__, ret);
ret = da8xx_register_usb_phy(); ret = da8xx_register_usb_phy();
...@@ -339,14 +334,48 @@ static struct resource da830_evm_nand_resources[] = { ...@@ -339,14 +334,48 @@ static struct resource da830_evm_nand_resources[] = {
}, },
}; };
static struct platform_device da830_evm_nand_device = { static struct platform_device da830_evm_aemif_devices[] = {
.name = "davinci_nand", {
.id = 1, .name = "davinci_nand",
.dev = { .id = 1,
.platform_data = &da830_evm_nand_pdata, .dev = {
.platform_data = &da830_evm_nand_pdata,
},
.num_resources = ARRAY_SIZE(da830_evm_nand_resources),
.resource = da830_evm_nand_resources,
},
};
static struct resource da830_evm_aemif_resource[] = {
{
.start = DA8XX_AEMIF_CTL_BASE,
.end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct aemif_abus_data da830_evm_aemif_abus_data[] = {
{
.cs = 3,
}, },
.num_resources = ARRAY_SIZE(da830_evm_nand_resources), };
.resource = da830_evm_nand_resources,
static struct aemif_platform_data da830_evm_aemif_pdata = {
.abus_data = da830_evm_aemif_abus_data,
.num_abus_data = ARRAY_SIZE(da830_evm_aemif_abus_data),
.sub_devices = da830_evm_aemif_devices,
.num_sub_devices = ARRAY_SIZE(da830_evm_aemif_devices),
.cs_offset = 2,
};
static struct platform_device da830_evm_aemif_device = {
.name = "ti-aemif",
.id = -1,
.dev = {
.platform_data = &da830_evm_aemif_pdata,
},
.resource = da830_evm_aemif_resource,
.num_resources = ARRAY_SIZE(da830_evm_aemif_resource),
}; };
/* /*
...@@ -377,12 +406,9 @@ static inline void da830_evm_init_nand(int mux_mode) ...@@ -377,12 +406,9 @@ static inline void da830_evm_init_nand(int mux_mode)
if (ret) if (ret)
pr_warn("%s: emif25 mux setup failed: %d\n", __func__, ret); pr_warn("%s: emif25 mux setup failed: %d\n", __func__, ret);
ret = platform_device_register(&da830_evm_nand_device); ret = platform_device_register(&da830_evm_aemif_device);
if (ret) if (ret)
pr_warn("%s: NAND device not registered\n", __func__); pr_warn("%s: AEMIF device not registered\n", __func__);
if (davinci_aemif_setup(&da830_evm_nand_device))
pr_warn("%s: Cannot configure AEMIF\n", __func__);
gpio_direction_output(mux_mode, 1); gpio_direction_output(mux_mode, 1);
} }
...@@ -557,6 +583,8 @@ static __init void da830_evm_init(void) ...@@ -557,6 +583,8 @@ static __init void da830_evm_init(void)
struct davinci_soc_info *soc_info = &davinci_soc_info; struct davinci_soc_info *soc_info = &davinci_soc_info;
int ret; int ret;
da830_register_clocks();
ret = da830_register_gpio(); ret = da830_register_gpio();
if (ret) if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret); pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
......
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
#include <linux/platform_data/gpio-davinci.h> #include <linux/platform_data/gpio-davinci.h>
#include <linux/platform_data/mtd-davinci.h> #include <linux/platform_data/mtd-davinci.h>
#include <linux/platform_data/mtd-davinci-aemif.h> #include <linux/platform_data/mtd-davinci-aemif.h>
#include <linux/platform_data/ti-aemif.h>
#include <linux/platform_data/spi-davinci.h> #include <linux/platform_data/spi-davinci.h>
#include <linux/platform_data/uio_pruss.h> #include <linux/platform_data/uio_pruss.h>
#include <linux/regulator/machine.h> #include <linux/regulator/machine.h>
...@@ -185,16 +186,6 @@ static struct resource da850_evm_norflash_resource[] = { ...@@ -185,16 +186,6 @@ static struct resource da850_evm_norflash_resource[] = {
}, },
}; };
static struct platform_device da850_evm_norflash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &da850_evm_norflash_data,
},
.num_resources = 1,
.resource = da850_evm_norflash_resource,
};
/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash /* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
* (128K blocks). It may be used instead of the (default) SPI flash * (128K blocks). It may be used instead of the (default) SPI flash
* to boot, using TI's tools to install the secondary boot loader * to boot, using TI's tools to install the secondary boot loader
...@@ -266,37 +257,58 @@ static struct resource da850_evm_nandflash_resource[] = { ...@@ -266,37 +257,58 @@ static struct resource da850_evm_nandflash_resource[] = {
}, },
}; };
static struct platform_device da850_evm_nandflash_device = { static struct resource da850_evm_aemif_resource[] = {
.name = "davinci_nand", {
.id = 1, .start = DA8XX_AEMIF_CTL_BASE,
.dev = { .end = DA8XX_AEMIF_CTL_BASE + SZ_32K,
.platform_data = &da850_evm_nandflash_data, .flags = IORESOURCE_MEM,
}, }
.num_resources = ARRAY_SIZE(da850_evm_nandflash_resource),
.resource = da850_evm_nandflash_resource,
}; };
static struct platform_device *da850_evm_devices[] = { static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
&da850_evm_nandflash_device, {
&da850_evm_norflash_device, .cs = 3,
}
}; };
#define DA8XX_AEMIF_CE2CFG_OFFSET 0x10 static struct platform_device da850_evm_aemif_devices[] = {
#define DA8XX_AEMIF_ASIZE_16BIT 0x1 {
.name = "davinci_nand",
static void __init da850_evm_init_nor(void) .id = 1,
{ .dev = {
void __iomem *aemif_addr; .platform_data = &da850_evm_nandflash_data,
},
aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K); .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource),
.resource = da850_evm_nandflash_resource,
},
{
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &da850_evm_norflash_data,
},
.num_resources = 1,
.resource = da850_evm_norflash_resource,
}
};
/* Configure data bus width of CS2 to 16 bit */ static struct aemif_platform_data da850_evm_aemif_pdata = {
writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) | .cs_offset = 2,
DA8XX_AEMIF_ASIZE_16BIT, .abus_data = da850_evm_aemif_abus_data,
aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET); .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data),
.sub_devices = da850_evm_aemif_devices,
.num_sub_devices = ARRAY_SIZE(da850_evm_aemif_devices),
};
iounmap(aemif_addr); static struct platform_device da850_evm_aemif_device = {
} .name = "ti-aemif",
.id = -1,
.dev = {
.platform_data = &da850_evm_aemif_pdata,
},
.resource = da850_evm_aemif_resource,
.num_resources = ARRAY_SIZE(da850_evm_aemif_resource),
};
static const short da850_evm_nand_pins[] = { static const short da850_evm_nand_pins[] = {
DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
...@@ -339,13 +351,10 @@ static inline void da850_evm_setup_nor_nand(void) ...@@ -339,13 +351,10 @@ static inline void da850_evm_setup_nor_nand(void)
pr_warn("%s: NOR mux setup failed: %d\n", pr_warn("%s: NOR mux setup failed: %d\n",
__func__, ret); __func__, ret);
da850_evm_init_nor(); ret = platform_device_register(&da850_evm_aemif_device);
if (ret)
platform_add_devices(da850_evm_devices, pr_warn("%s: registering aemif failed: %d\n",
ARRAY_SIZE(da850_evm_devices)); __func__, ret);
if (davinci_aemif_setup(&da850_evm_nandflash_device))
pr_warn("%s: Cannot configure AEMIF.\n", __func__);
} }
} }
...@@ -1340,6 +1349,8 @@ static __init void da850_evm_init(void) ...@@ -1340,6 +1349,8 @@ static __init void da850_evm_init(void)
{ {
int ret; int ret;
da850_register_clocks();
ret = da850_register_gpio(); ret = da850_register_gpio();
if (ret) if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret); pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
......
...@@ -394,6 +394,8 @@ static __init void dm355_evm_init(void) ...@@ -394,6 +394,8 @@ static __init void dm355_evm_init(void)
struct clk *aemif; struct clk *aemif;
int ret; int ret;
dm355_register_clocks();
ret = dm355_gpio_register(); ret = dm355_gpio_register();
if (ret) if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret); pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
......
...@@ -234,6 +234,8 @@ static __init void dm355_leopard_init(void) ...@@ -234,6 +234,8 @@ static __init void dm355_leopard_init(void)
struct clk *aemif; struct clk *aemif;
int ret; int ret;
dm355_register_clocks();
ret = dm355_gpio_register(); ret = dm355_gpio_register();
if (ret) if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret); pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
......
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
#include <linux/spi/spi.h> #include <linux/spi/spi.h>
#include <linux/spi/eeprom.h> #include <linux/spi/eeprom.h>
#include <linux/v4l2-dv-timings.h> #include <linux/v4l2-dv-timings.h>
#include <linux/platform_data/ti-aemif.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
...@@ -159,16 +160,49 @@ static struct resource davinci_nand_resources[] = { ...@@ -159,16 +160,49 @@ static struct resource davinci_nand_resources[] = {
}, },
}; };
static struct platform_device davinci_nand_device = { static struct platform_device davinci_aemif_devices[] = {
.name = "davinci_nand", {
.id = 0, .name = "davinci_nand",
.num_resources = ARRAY_SIZE(davinci_nand_resources), .id = 0,
.resource = davinci_nand_resources, .num_resources = ARRAY_SIZE(davinci_nand_resources),
.dev = { .resource = davinci_nand_resources,
.platform_data = &davinci_nand_data, .dev = {
.platform_data = &davinci_nand_data,
},
}
};
static struct resource davinci_aemif_resources[] = {
{
.start = DM365_ASYNC_EMIF_CONTROL_BASE,
.end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, },
}; };
static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
{
.cs = 1,
},
};
static struct aemif_platform_data davinci_aemif_pdata = {
.abus_data = da850_evm_aemif_abus_data,
.num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data),
.sub_devices = davinci_aemif_devices,
.num_sub_devices = ARRAY_SIZE(davinci_aemif_devices),
};
static struct platform_device davinci_aemif_device = {
.name = "ti-aemif",
.id = -1,
.dev = {
.platform_data = &davinci_aemif_pdata,
},
.resource = davinci_aemif_resources,
.num_resources = ARRAY_SIZE(davinci_aemif_resources),
};
static struct at24_platform_data eeprom_info = { static struct at24_platform_data eeprom_info = {
.byte_len = (256*1024) / 8, .byte_len = (256*1024) / 8,
.page_size = 64, .page_size = 64,
...@@ -537,10 +571,6 @@ static void __init evm_init_i2c(void) ...@@ -537,10 +571,6 @@ static void __init evm_init_i2c(void)
i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
} }
static struct platform_device *dm365_evm_nand_devices[] __initdata = {
&davinci_nand_device,
};
static inline int have_leds(void) static inline int have_leds(void)
{ {
#ifdef CONFIG_LEDS_CLASS #ifdef CONFIG_LEDS_CLASS
...@@ -628,6 +658,7 @@ static void __init evm_init_cpld(void) ...@@ -628,6 +658,7 @@ static void __init evm_init_cpld(void)
u8 mux, resets; u8 mux, resets;
const char *label; const char *label;
struct clk *aemif_clk; struct clk *aemif_clk;
int rc;
/* Make sure we can configure the CPLD through CS1. Then /* Make sure we can configure the CPLD through CS1. Then
* leave it on for later access to MMC and LED registers. * leave it on for later access to MMC and LED registers.
...@@ -660,8 +691,10 @@ static void __init evm_init_cpld(void) ...@@ -660,8 +691,10 @@ static void __init evm_init_cpld(void)
/* external keypad mux */ /* external keypad mux */
mux |= BIT(7); mux |= BIT(7);
platform_add_devices(dm365_evm_nand_devices, rc = platform_device_register(&davinci_aemif_device);
ARRAY_SIZE(dm365_evm_nand_devices)); if (rc)
pr_warn("%s(): error registering the aemif device: %d\n",
__func__, rc);
} else { } else {
/* no OneNAND support yet */ /* no OneNAND support yet */
} }
...@@ -742,6 +775,8 @@ static __init void dm365_evm_init(void) ...@@ -742,6 +775,8 @@ static __init void dm365_evm_init(void)
{ {
int ret; int ret;
dm365_register_clocks();
ret = dm365_gpio_register(); ret = dm365_gpio_register();
if (ret) if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret); pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
......
...@@ -42,6 +42,7 @@ ...@@ -42,6 +42,7 @@
#include <linux/platform_data/mmc-davinci.h> #include <linux/platform_data/mmc-davinci.h>
#include <linux/platform_data/usb-davinci.h> #include <linux/platform_data/usb-davinci.h>
#include <linux/platform_data/mtd-davinci-aemif.h> #include <linux/platform_data/mtd-davinci-aemif.h>
#include <linux/platform_data/ti-aemif.h>
#include "davinci.h" #include "davinci.h"
...@@ -174,14 +175,47 @@ static struct resource davinci_evm_nandflash_resource[] = { ...@@ -174,14 +175,47 @@ static struct resource davinci_evm_nandflash_resource[] = {
}, },
}; };
static struct platform_device davinci_evm_nandflash_device = { static struct resource davinci_evm_aemif_resource[] = {
.name = "davinci_nand", {
.id = 0, .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
.dev = { .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.platform_data = &davinci_evm_nandflash_data, .flags = IORESOURCE_MEM,
},
};
static struct aemif_abus_data davinci_evm_aemif_abus_data[] = {
{
.cs = 1,
},
};
static struct platform_device davinci_evm_nandflash_devices[] = {
{
.name = "davinci_nand",
.id = 0,
.dev = {
.platform_data = &davinci_evm_nandflash_data,
},
.num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
.resource = davinci_evm_nandflash_resource,
},
};
static struct aemif_platform_data davinci_evm_aemif_pdata = {
.abus_data = davinci_evm_aemif_abus_data,
.num_abus_data = ARRAY_SIZE(davinci_evm_aemif_abus_data),
.sub_devices = davinci_evm_nandflash_devices,
.num_sub_devices = ARRAY_SIZE(davinci_evm_nandflash_devices),
};
static struct platform_device davinci_evm_aemif_device = {
.name = "ti-aemif",
.id = -1,
.dev = {
.platform_data = &davinci_evm_aemif_pdata,
}, },
.num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource), .resource = davinci_evm_aemif_resource,
.resource = davinci_evm_nandflash_resource, .num_resources = ARRAY_SIZE(davinci_evm_aemif_resource),
}; };
static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32); static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
...@@ -773,6 +807,8 @@ static __init void davinci_evm_init(void) ...@@ -773,6 +807,8 @@ static __init void davinci_evm_init(void)
struct clk *aemif_clk; struct clk *aemif_clk;
struct davinci_soc_info *soc_info = &davinci_soc_info; struct davinci_soc_info *soc_info = &davinci_soc_info;
dm644x_register_clocks();
dm644x_init_devices(); dm644x_init_devices();
ret = dm644x_gpio_register(); ret = dm644x_gpio_register();
...@@ -793,12 +829,7 @@ static __init void davinci_evm_init(void) ...@@ -793,12 +829,7 @@ static __init void davinci_evm_init(void)
/* only one device will be jumpered and detected */ /* only one device will be jumpered and detected */
if (HAS_NAND) { if (HAS_NAND) {
platform_device_register(&davinci_evm_nandflash_device); platform_device_register(&davinci_evm_aemif_device);
if (davinci_aemif_setup(&davinci_evm_nandflash_device))
pr_warn("%s: Cannot configure AEMIF\n",
__func__);
#ifdef CONFIG_I2C #ifdef CONFIG_I2C
evm_leds[7].default_trigger = "nand-disk"; evm_leds[7].default_trigger = "nand-disk";
#endif #endif
......
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#include <linux/i2c.h> #include <linux/i2c.h>
#include <linux/platform_data/at24.h> #include <linux/platform_data/at24.h>
#include <linux/platform_data/pcf857x.h> #include <linux/platform_data/pcf857x.h>
#include <linux/platform_data/ti-aemif.h>
#include <media/i2c/tvp514x.h> #include <media/i2c/tvp514x.h>
#include <media/i2c/adv7343.h> #include <media/i2c/adv7343.h>
...@@ -106,18 +107,49 @@ static struct resource davinci_nand_resources[] = { ...@@ -106,18 +107,49 @@ static struct resource davinci_nand_resources[] = {
}, },
}; };
static struct platform_device davinci_nand_device = { static struct platform_device davinci_aemif_devices[] = {
.name = "davinci_nand", {
.id = 0, .name = "davinci_nand",
.id = 0,
.num_resources = ARRAY_SIZE(davinci_nand_resources),
.resource = davinci_nand_resources,
.dev = {
.platform_data = &davinci_nand_data,
},
},
};
.num_resources = ARRAY_SIZE(davinci_nand_resources), static struct resource davinci_aemif_resources[] = {
.resource = davinci_nand_resources, {
.start = DM646X_ASYNC_EMIF_CONTROL_BASE,
.end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
.dev = { static struct aemif_abus_data davinci_aemif_abus_data[] = {
.platform_data = &davinci_nand_data, {
.cs = 1,
}, },
}; };
static struct aemif_platform_data davinci_aemif_pdata = {
.abus_data = davinci_aemif_abus_data,
.num_abus_data = ARRAY_SIZE(davinci_aemif_abus_data),
.sub_devices = davinci_aemif_devices,
.num_sub_devices = ARRAY_SIZE(davinci_aemif_devices),
};
static struct platform_device davinci_aemif_device = {
.name = "ti-aemif",
.id = -1,
.dev = {
.platform_data = &davinci_aemif_pdata,
},
.resource = davinci_aemif_resources,
.num_resources = ARRAY_SIZE(davinci_aemif_resources),
};
#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ #define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
IS_ENABLED(CONFIG_PATA_BK3710)) IS_ENABLED(CONFIG_PATA_BK3710))
...@@ -776,6 +808,8 @@ static __init void evm_init(void) ...@@ -776,6 +808,8 @@ static __init void evm_init(void)
int ret; int ret;
struct davinci_soc_info *soc_info = &davinci_soc_info; struct davinci_soc_info *soc_info = &davinci_soc_info;
dm646x_register_clocks();
ret = dm646x_gpio_register(); ret = dm646x_gpio_register();
if (ret) if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret); pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
...@@ -791,10 +825,8 @@ static __init void evm_init(void) ...@@ -791,10 +825,8 @@ static __init void evm_init(void)
if (machine_is_davinci_dm6467tevm()) if (machine_is_davinci_dm6467tevm())
davinci_nand_data.timing = &dm6467tevm_nandflash_timing; davinci_nand_data.timing = &dm6467tevm_nandflash_timing;
platform_device_register(&davinci_nand_device); if (platform_device_register(&davinci_aemif_device))
pr_warn("%s: Cannot register AEMIF device.\n", __func__);
if (davinci_aemif_setup(&davinci_nand_device))
pr_warn("%s: Cannot configure AEMIF.\n", __func__);
dm646x_init_edma(dm646x_edma_rsv); dm646x_init_edma(dm646x_edma_rsv);
......
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
#include <mach/da8xx.h> #include <mach/da8xx.h>
#include <linux/platform_data/mtd-davinci.h> #include <linux/platform_data/mtd-davinci.h>
#include <linux/platform_data/mtd-davinci-aemif.h> #include <linux/platform_data/mtd-davinci-aemif.h>
#include <linux/platform_data/ti-aemif.h>
#include <mach/mux.h> #include <mach/mux.h>
#include <linux/platform_data/spi-davinci.h> #include <linux/platform_data/spi-davinci.h>
...@@ -422,27 +423,53 @@ static struct resource mityomapl138_nandflash_resource[] = { ...@@ -422,27 +423,53 @@ static struct resource mityomapl138_nandflash_resource[] = {
}, },
}; };
static struct platform_device mityomapl138_nandflash_device = { static struct platform_device mityomapl138_aemif_devices[] = {
.name = "davinci_nand", {
.id = 1, .name = "davinci_nand",
.dev = { .id = 1,
.platform_data = &mityomapl138_nandflash_data, .dev = {
.platform_data = &mityomapl138_nandflash_data,
},
.num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
.resource = mityomapl138_nandflash_resource,
},
};
static struct resource mityomapl138_aemif_resources[] = {
{
.start = DA8XX_AEMIF_CTL_BASE,
.end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
.flags = IORESOURCE_MEM,
}, },
.num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
.resource = mityomapl138_nandflash_resource,
}; };
static struct platform_device *mityomapl138_devices[] __initdata = { static struct aemif_abus_data mityomapl138_aemif_abus_data[] = {
&mityomapl138_nandflash_device, {
.cs = 1,
},
};
static struct aemif_platform_data mityomapl138_aemif_pdata = {
.abus_data = mityomapl138_aemif_abus_data,
.num_abus_data = ARRAY_SIZE(mityomapl138_aemif_abus_data),
.sub_devices = mityomapl138_aemif_devices,
.num_sub_devices = ARRAY_SIZE(mityomapl138_aemif_devices),
};
static struct platform_device mityomapl138_aemif_device = {
.name = "ti-aemif",
.id = -1,
.dev = {
.platform_data = &mityomapl138_aemif_pdata,
},
.resource = mityomapl138_aemif_resources,
.num_resources = ARRAY_SIZE(mityomapl138_aemif_resources),
}; };
static void __init mityomapl138_setup_nand(void) static void __init mityomapl138_setup_nand(void)
{ {
platform_add_devices(mityomapl138_devices, if (platform_device_register(&mityomapl138_aemif_device))
ARRAY_SIZE(mityomapl138_devices)); pr_warn("%s: Cannot register AEMIF device\n", __func__);
if (davinci_aemif_setup(&mityomapl138_nandflash_device))
pr_warn("%s: Cannot configure AEMIF\n", __func__);
} }
static const short mityomap_mii_pins[] = { static const short mityomap_mii_pins[] = {
...@@ -503,6 +530,8 @@ static void __init mityomapl138_init(void) ...@@ -503,6 +530,8 @@ static void __init mityomapl138_init(void)
{ {
int ret; int ret;
da850_register_clocks();
/* for now, no special EDMA channels are reserved */ /* for now, no special EDMA channels are reserved */
ret = da850_register_edma(NULL); ret = da850_register_edma(NULL);
if (ret) if (ret)
......
...@@ -175,6 +175,8 @@ static __init void davinci_ntosd2_init(void) ...@@ -175,6 +175,8 @@ static __init void davinci_ntosd2_init(void)
struct clk *aemif_clk; struct clk *aemif_clk;
struct davinci_soc_info *soc_info = &davinci_soc_info; struct davinci_soc_info *soc_info = &davinci_soc_info;
dm644x_register_clocks();
dm644x_init_devices(); dm644x_init_devices();
ret = dm644x_gpio_register(); ret = dm644x_gpio_register();
......
...@@ -15,7 +15,12 @@ ...@@ -15,7 +15,12 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/gpio/machine.h> #include <linux/gpio/machine.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/rawnand.h>
#include <linux/platform_data/gpio-davinci.h> #include <linux/platform_data/gpio-davinci.h>
#include <linux/platform_data/mtd-davinci.h>
#include <linux/platform_data/mtd-davinci-aemif.h>
#include <linux/platform_data/ti-aemif.h>
#include <linux/regulator/machine.h> #include <linux/regulator/machine.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
...@@ -166,6 +171,129 @@ static __init void omapl138_hawk_mmc_init(void) ...@@ -166,6 +171,129 @@ static __init void omapl138_hawk_mmc_init(void)
gpiod_remove_lookup_table(&mmc_gpios_table); gpiod_remove_lookup_table(&mmc_gpios_table);
} }
static struct mtd_partition omapl138_hawk_nandflash_partition[] = {
{
.name = "u-boot env",
.offset = 0,
.size = SZ_128K,
.mask_flags = MTD_WRITEABLE,
},
{
.name = "u-boot",
.offset = MTDPART_OFS_APPEND,
.size = SZ_512K,
.mask_flags = MTD_WRITEABLE,
},
{
.name = "free space",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
.mask_flags = 0,
},
};
static struct davinci_aemif_timing omapl138_hawk_nandflash_timing = {
.wsetup = 24,
.wstrobe = 21,
.whold = 14,
.rsetup = 19,
.rstrobe = 50,
.rhold = 0,
.ta = 20,
};
static struct davinci_nand_pdata omapl138_hawk_nandflash_data = {
.core_chipsel = 1,
.parts = omapl138_hawk_nandflash_partition,
.nr_parts = ARRAY_SIZE(omapl138_hawk_nandflash_partition),
.ecc_mode = NAND_ECC_HW,
.ecc_bits = 4,
.bbt_options = NAND_BBT_USE_FLASH,
.options = NAND_BUSWIDTH_16,
.timing = &omapl138_hawk_nandflash_timing,
.mask_chipsel = 0,
.mask_ale = 0,
.mask_cle = 0,
};
static struct resource omapl138_hawk_nandflash_resource[] = {
{
.start = DA8XX_AEMIF_CS3_BASE,
.end = DA8XX_AEMIF_CS3_BASE + SZ_32M,
.flags = IORESOURCE_MEM,
},
{
.start = DA8XX_AEMIF_CTL_BASE,
.end = DA8XX_AEMIF_CTL_BASE + SZ_32K,
.flags = IORESOURCE_MEM,
},
};
static struct resource omapl138_hawk_aemif_resource[] = {
{
.start = DA8XX_AEMIF_CTL_BASE,
.end = DA8XX_AEMIF_CTL_BASE + SZ_32K,
.flags = IORESOURCE_MEM,
}
};
static struct aemif_abus_data omapl138_hawk_aemif_abus_data[] = {
{
.cs = 3,
}
};
static struct platform_device omapl138_hawk_aemif_devices[] = {
{
.name = "davinci_nand",
.id = -1,
.dev = {
.platform_data = &omapl138_hawk_nandflash_data,
},
.resource = omapl138_hawk_nandflash_resource,
.num_resources = ARRAY_SIZE(omapl138_hawk_nandflash_resource),
}
};
static struct aemif_platform_data omapl138_hawk_aemif_pdata = {
.cs_offset = 2,
.abus_data = omapl138_hawk_aemif_abus_data,
.num_abus_data = ARRAY_SIZE(omapl138_hawk_aemif_abus_data),
.sub_devices = omapl138_hawk_aemif_devices,
.num_sub_devices = ARRAY_SIZE(omapl138_hawk_aemif_devices),
};
static struct platform_device omapl138_hawk_aemif_device = {
.name = "ti-aemif",
.id = -1,
.dev = {
.platform_data = &omapl138_hawk_aemif_pdata,
},
.resource = omapl138_hawk_aemif_resource,
.num_resources = ARRAY_SIZE(omapl138_hawk_aemif_resource),
};
static const short omapl138_hawk_nand_pins[] = {
DA850_EMA_WAIT_1, DA850_NEMA_OE, DA850_NEMA_WE, DA850_NEMA_CS_3,
DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11,
DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15,
DA850_EMA_A_1, DA850_EMA_A_2,
-1
};
static int omapl138_hawk_register_aemif(void)
{
int ret;
ret = davinci_cfg_reg_list(omapl138_hawk_nand_pins);
if (ret)
pr_warn("%s: NAND mux setup failed: %d\n", __func__, ret);
return platform_device_register(&omapl138_hawk_aemif_device);
}
static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id); static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id);
static da8xx_ocic_handler_t hawk_usb_ocic_handler; static da8xx_ocic_handler_t hawk_usb_ocic_handler;
...@@ -236,14 +364,9 @@ static __init void omapl138_hawk_usb_init(void) ...@@ -236,14 +364,9 @@ static __init void omapl138_hawk_usb_init(void)
return; return;
} }
ret = da8xx_register_usb20_phy_clk(false); ret = da8xx_register_usb_phy_clocks();
if (ret)
pr_warn("%s: USB 2.0 PHY CLK registration failed: %d\n",
__func__, ret);
ret = da8xx_register_usb11_phy_clk(false);
if (ret) if (ret)
pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n", pr_warn("%s: USB PHY CLK registration failed: %d\n",
__func__, ret); __func__, ret);
ret = da8xx_register_usb_phy(); ret = da8xx_register_usb_phy();
...@@ -285,6 +408,8 @@ static __init void omapl138_hawk_init(void) ...@@ -285,6 +408,8 @@ static __init void omapl138_hawk_init(void)
{ {
int ret; int ret;
da850_register_clocks();
ret = da850_register_gpio(); ret = da850_register_gpio();
if (ret) if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret); pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
...@@ -301,6 +426,10 @@ static __init void omapl138_hawk_init(void) ...@@ -301,6 +426,10 @@ static __init void omapl138_hawk_init(void)
omapl138_hawk_usb_init(); omapl138_hawk_usb_init();
ret = omapl138_hawk_register_aemif();
if (ret)
pr_warn("%s: aemif registration failed: %d\n", __func__, ret);
ret = da8xx_register_watchdog(); ret = da8xx_register_watchdog();
if (ret) if (ret)
pr_warn("%s: watchdog registration failed: %d\n", pr_warn("%s: watchdog registration failed: %d\n",
......
...@@ -134,6 +134,8 @@ static __init void davinci_sffsdr_init(void) ...@@ -134,6 +134,8 @@ static __init void davinci_sffsdr_init(void)
{ {
struct davinci_soc_info *soc_info = &davinci_soc_info; struct davinci_soc_info *soc_info = &davinci_soc_info;
dm644x_register_clocks();
dm644x_init_devices(); dm644x_init_devices();
platform_add_devices(davinci_sffsdr_devices, platform_add_devices(davinci_sffsdr_devices,
......
This diff is collapsed.
...@@ -12,10 +12,6 @@ ...@@ -12,10 +12,6 @@
#ifndef __ARCH_ARM_DAVINCI_CLOCK_H #ifndef __ARCH_ARM_DAVINCI_CLOCK_H
#define __ARCH_ARM_DAVINCI_CLOCK_H #define __ARCH_ARM_DAVINCI_CLOCK_H
#define DAVINCI_PLL1_BASE 0x01c40800
#define DAVINCI_PLL2_BASE 0x01c40c00
#define MAX_PLL 2
/* PLL/Reset register offsets */ /* PLL/Reset register offsets */
#define PLLCTL 0x100 #define PLLCTL 0x100
#define PLLCTL_PLLEN BIT(0) #define PLLCTL_PLLEN BIT(0)
...@@ -65,76 +61,4 @@ ...@@ -65,76 +61,4 @@
*/ */
#define PLL_LOCK_TIME 20 #define PLL_LOCK_TIME 20
#ifndef __ASSEMBLER__
#include <linux/list.h>
#include <linux/clkdev.h>
#define PLLSTAT_GOSTAT BIT(0)
#define PLLCMD_GOSET BIT(0)
struct pll_data {
u32 phys_base;
void __iomem *base;
u32 num;
u32 flags;
u32 input_rate;
u32 div_ratio_mask;
};
#define PLL_HAS_PREDIV 0x01
#define PLL_HAS_POSTDIV 0x02
struct clk {
struct list_head node;
struct module *owner;
const char *name;
unsigned long rate;
unsigned long maxrate; /* H/W supported max rate */
u8 usecount;
u8 lpsc;
u8 gpsc;
u8 domain;
u32 flags;
struct clk *parent;
struct list_head children; /* list of children */
struct list_head childnode; /* parent's child list node */
struct pll_data *pll_data;
u32 div_reg;
unsigned long (*recalc) (struct clk *);
int (*set_rate) (struct clk *clk, unsigned long rate);
int (*round_rate) (struct clk *clk, unsigned long rate);
int (*reset) (struct clk *clk, bool reset);
void (*clk_enable) (struct clk *clk);
void (*clk_disable) (struct clk *clk);
int (*set_parent) (struct clk *clk, struct clk *parent);
};
/* Clock flags: SoC-specific flags start at BIT(16) */
#define ALWAYS_ENABLED BIT(1)
#define CLK_PSC BIT(2)
#define CLK_PLL BIT(3) /* PLL-derived clock */
#define PRE_PLL BIT(4) /* source is before PLL mult/div */
#define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */
#define PSC_FORCE BIT(6) /* Force module state transtition */
#define PSC_LRST BIT(8) /* Use local reset on enable/disable */
#define CLK(dev, con, ck) \
{ \
.dev_id = dev, \
.con_id = con, \
.clk = ck, \
} \
int davinci_clk_init(struct clk_lookup *clocks);
int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
unsigned int mult, unsigned int postdiv);
int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
int davinci_set_refclk_rate(unsigned long rate);
int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
int davinci_clk_reset(struct clk *clk, bool reset);
void davinci_clk_enable(struct clk *clk);
void davinci_clk_disable(struct clk *clk);
#endif
#endif #endif
...@@ -20,8 +20,6 @@ ...@@ -20,8 +20,6 @@
#include <mach/common.h> #include <mach/common.h>
#include <mach/cputype.h> #include <mach/cputype.h>
#include "clock.h"
struct davinci_soc_info davinci_soc_info; struct davinci_soc_info davinci_soc_info;
EXPORT_SYMBOL(davinci_soc_info); EXPORT_SYMBOL(davinci_soc_info);
...@@ -118,5 +116,4 @@ void __init davinci_common_init(const struct davinci_soc_info *soc_info) ...@@ -118,5 +116,4 @@ void __init davinci_common_init(const struct davinci_soc_info *soc_info)
void __init davinci_init_late(void) void __init davinci_init_late(void)
{ {
davinci_cpufreq_init(); davinci_cpufreq_init();
davinci_clk_disable_unused();
} }
This diff is collapsed.
This diff is collapsed.
...@@ -7,81 +7,16 @@ ...@@ -7,81 +7,16 @@
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#include <linux/io.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/irqdomain.h>
#include <linux/platform_data/ti-aemif.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <mach/common.h> #include <mach/common.h>
#include "cp_intc.h"
#include <mach/da8xx.h> #include <mach/da8xx.h>
static struct of_dev_auxdata da850_aemif_auxdata_lookup[] = {
OF_DEV_AUXDATA("ti,davinci-nand", 0x62000000, "davinci-nand.0", NULL),
{}
};
static struct aemif_platform_data aemif_data = {
.dev_lookup = da850_aemif_auxdata_lookup,
};
static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL),
OF_DEV_AUXDATA("ti,davinci-i2c", 0x01e28000, "i2c_davinci.2", NULL),
OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "davinci-wdt", NULL),
OF_DEV_AUXDATA("ti,da830-mmc", 0x01c40000, "da830-mmc.0", NULL),
OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f00000, "ehrpwm.0", NULL),
OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f02000, "ehrpwm.1", NULL),
OF_DEV_AUXDATA("ti,da850-ecap", 0x01f06000, "ecap.0", NULL),
OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap.1", NULL),
OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap.2", NULL),
OF_DEV_AUXDATA("ti,da830-spi", 0x01c41000, "spi_davinci.0", NULL),
OF_DEV_AUXDATA("ti,da830-spi", 0x01f0e000, "spi_davinci.1", NULL),
OF_DEV_AUXDATA("ns16550a", 0x01c42000, "serial8250.0", NULL),
OF_DEV_AUXDATA("ns16550a", 0x01d0c000, "serial8250.1", NULL),
OF_DEV_AUXDATA("ns16550a", 0x01d0d000, "serial8250.2", NULL),
OF_DEV_AUXDATA("ti,davinci_mdio", 0x01e24000, "davinci_mdio.0", NULL),
OF_DEV_AUXDATA("ti,davinci-dm6467-emac", 0x01e20000, "davinci_emac.1",
NULL),
OF_DEV_AUXDATA("ti,da830-mcasp-audio", 0x01d00000, "davinci-mcasp.0", NULL),
OF_DEV_AUXDATA("ti,da850-aemif", 0x68000000, "ti-aemif", &aemif_data),
OF_DEV_AUXDATA("ti,da850-tilcdc", 0x01e13000, "da8xx_lcdc.0", NULL),
OF_DEV_AUXDATA("ti,da830-ohci", 0x01e25000, "ohci-da8xx", NULL),
OF_DEV_AUXDATA("ti,da830-musb", 0x01e00000, "musb-da8xx", NULL),
OF_DEV_AUXDATA("ti,da830-usb-phy", 0x01c1417c, "da8xx-usb-phy", NULL),
OF_DEV_AUXDATA("ti,da850-ahci", 0x01e18000, "ahci_da850", NULL),
OF_DEV_AUXDATA("ti,da850-vpif", 0x01e17000, "vpif", NULL),
OF_DEV_AUXDATA("ti,da850-dsp", 0x11800000, "davinci-rproc.0", NULL),
{}
};
#ifdef CONFIG_ARCH_DAVINCI_DA850 #ifdef CONFIG_ARCH_DAVINCI_DA850
static void __init da850_init_machine(void) static void __init da850_init_machine(void)
{ {
/* All existing boards use 100MHz SATA refclkpn */
static const unsigned long sata_refclkpn = 100 * 1000 * 1000;
int ret;
ret = da8xx_register_usb20_phy_clk(false);
if (ret)
pr_warn("%s: registering USB 2.0 PHY clock failed: %d",
__func__, ret);
ret = da8xx_register_usb11_phy_clk(false);
if (ret)
pr_warn("%s: registering USB 1.1 PHY clock failed: %d",
__func__, ret);
ret = da850_register_sata_refclk(sata_refclkpn);
if (ret)
pr_warn("%s: registering SATA REFCLK failed: %d",
__func__, ret);
of_platform_default_populate(NULL, da850_auxdata_lookup, NULL);
davinci_pm_init(); davinci_pm_init();
pdata_quirks_init(); pdata_quirks_init();
} }
...@@ -96,7 +31,6 @@ static const char *const da850_boards_compat[] __initconst = { ...@@ -96,7 +31,6 @@ static const char *const da850_boards_compat[] __initconst = {
DT_MACHINE_START(DA850_DT, "Generic DA850/OMAP-L138/AM18x") DT_MACHINE_START(DA850_DT, "Generic DA850/OMAP-L138/AM18x")
.map_io = da850_init, .map_io = da850_init,
.init_time = da850_init_time,
.init_machine = da850_init_machine, .init_machine = da850_init_machine,
.dt_compat = da850_boards_compat, .dt_compat = da850_boards_compat,
.init_late = davinci_init_late, .init_late = davinci_init_late,
......
...@@ -35,6 +35,10 @@ ...@@ -35,6 +35,10 @@
#include <media/davinci/vpbe.h> #include <media/davinci/vpbe.h>
#include <media/davinci/vpbe_osd.h> #include <media/davinci/vpbe_osd.h>
#define DAVINCI_PLL1_BASE 0x01c40800
#define DAVINCI_PLL2_BASE 0x01c40c00
#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01c41000
#define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000 #define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000
#define SYSMOD_VDAC_CONFIG 0x2c #define SYSMOD_VDAC_CONFIG 0x2c
#define SYSMOD_VIDCLKCTL 0x38 #define SYSMOD_VIDCLKCTL 0x38
...@@ -84,6 +88,7 @@ int davinci_init_wdt(void); ...@@ -84,6 +88,7 @@ int davinci_init_wdt(void);
/* DM355 function declarations */ /* DM355 function declarations */
void dm355_init(void); void dm355_init(void);
void dm355_init_time(void); void dm355_init_time(void);
void dm355_register_clocks(void);
void dm355_init_spi0(unsigned chipselect_mask, void dm355_init_spi0(unsigned chipselect_mask,
const struct spi_board_info *info, unsigned len); const struct spi_board_info *info, unsigned len);
void dm355_init_asp1(u32 evt_enable); void dm355_init_asp1(u32 evt_enable);
...@@ -93,6 +98,7 @@ int dm355_gpio_register(void); ...@@ -93,6 +98,7 @@ int dm355_gpio_register(void);
/* DM365 function declarations */ /* DM365 function declarations */
void dm365_init(void); void dm365_init(void);
void dm365_init_time(void); void dm365_init_time(void);
void dm365_register_clocks(void);
void dm365_init_asp(void); void dm365_init_asp(void);
void dm365_init_vc(void); void dm365_init_vc(void);
void dm365_init_ks(struct davinci_ks_platform_data *pdata); void dm365_init_ks(struct davinci_ks_platform_data *pdata);
...@@ -106,6 +112,7 @@ int dm365_gpio_register(void); ...@@ -106,6 +112,7 @@ int dm365_gpio_register(void);
void dm644x_init(void); void dm644x_init(void);
void dm644x_init_devices(void); void dm644x_init_devices(void);
void dm644x_init_time(void); void dm644x_init_time(void);
void dm644x_register_clocks(void);
void dm644x_init_asp(void); void dm644x_init_asp(void);
int dm644x_init_video(struct vpfe_config *, struct vpbe_config *); int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
int dm644x_gpio_register(void); int dm644x_gpio_register(void);
...@@ -113,6 +120,7 @@ int dm644x_gpio_register(void); ...@@ -113,6 +120,7 @@ int dm644x_gpio_register(void);
/* DM646x function declarations */ /* DM646x function declarations */
void dm646x_init(void); void dm646x_init(void);
void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate); void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate);
void dm646x_register_clocks(void);
void dm646x_init_mcasp0(struct snd_platform_data *pdata); void dm646x_init_mcasp0(struct snd_platform_data *pdata);
void dm646x_init_mcasp1(struct snd_platform_data *pdata); void dm646x_init_mcasp1(struct snd_platform_data *pdata);
int dm646x_init_edma(struct edma_rsv_info *rsv); int dm646x_init_edma(struct edma_rsv_info *rsv);
......
...@@ -10,25 +10,25 @@ ...@@ -10,25 +10,25 @@
* the Free Software Foundation; either version 2 of the License, or * the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version. * (at your option) any later version.
*/ */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-contiguous.h>
#include <linux/serial_8250.h>
#include <linux/ahci_platform.h> #include <linux/ahci_platform.h>
#include <linux/clk-provider.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/reboot.h> #include <linux/clkdev.h>
#include <linux/dma-contiguous.h>
#include <linux/dmaengine.h> #include <linux/dmaengine.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/serial_8250.h>
#include <mach/cputype.h>
#include <mach/common.h> #include <mach/common.h>
#include <mach/time.h> #include <mach/cputype.h>
#include <mach/da8xx.h> #include <mach/da8xx.h>
#include <mach/clock.h> #include <mach/time.h>
#include "cpuidle.h"
#include "sram.h"
#include "clock.h"
#include "asp.h" #include "asp.h"
#include "cpuidle.h"
#include "sram.h"
#define DA8XX_TPCC_BASE 0x01c00000 #define DA8XX_TPCC_BASE 0x01c00000
#define DA8XX_TPTC0_BASE 0x01c08000 #define DA8XX_TPTC0_BASE 0x01c08000
...@@ -1040,26 +1040,15 @@ int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect) ...@@ -1040,26 +1040,15 @@ int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
} }
#ifdef CONFIG_ARCH_DAVINCI_DA850 #ifdef CONFIG_ARCH_DAVINCI_DA850
static struct clk sata_refclk = {
.name = "sata_refclk",
.set_rate = davinci_simple_set_rate,
};
static struct clk_lookup sata_refclk_lookup =
CLK("ahci_da850", "refclk", &sata_refclk);
int __init da850_register_sata_refclk(int rate) int __init da850_register_sata_refclk(int rate)
{ {
int ret; struct clk *clk;
sata_refclk.rate = rate;
ret = clk_register(&sata_refclk);
if (ret)
return ret;
clkdev_add(&sata_refclk_lookup); clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate);
if (IS_ERR(clk))
return PTR_ERR(clk);
return 0; return clk_register_clkdev(clk, "refclk", "ahci_da850");
} }
static struct resource da850_sata_resources[] = { static struct resource da850_sata_resources[] = {
......
...@@ -26,7 +26,6 @@ ...@@ -26,7 +26,6 @@
#include "davinci.h" #include "davinci.h"
#include "clock.h"
#define DAVINCI_I2C_BASE 0x01C21000 #define DAVINCI_I2C_BASE 0x01C21000
#define DAVINCI_ATA_BASE 0x01C66000 #define DAVINCI_ATA_BASE 0x01C66000
......
This diff is collapsed.
This diff is collapsed.
...@@ -8,28 +8,29 @@ ...@@ -8,28 +8,29 @@
* is licensed "as is" without any warranty of any kind, whether express * is licensed "as is" without any warranty of any kind, whether express
* or implied. * or implied.
*/ */
#include <linux/init.h>
#include <linux/clk.h> #include <linux/clk-provider.h>
#include <linux/serial_8250.h> #include <linux/clk/davinci.h>
#include <linux/clkdev.h>
#include <linux/dmaengine.h> #include <linux/dmaengine.h>
#include <linux/platform_device.h> #include <linux/init.h>
#include <linux/platform_data/edma.h> #include <linux/platform_data/edma.h>
#include <linux/platform_data/gpio-davinci.h> #include <linux/platform_data/gpio-davinci.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/cputype.h> #include <mach/cputype.h>
#include <mach/irqs.h> #include <mach/irqs.h>
#include "psc.h"
#include <mach/mux.h> #include <mach/mux.h>
#include <mach/time.h>
#include <mach/serial.h> #include <mach/serial.h>
#include <mach/common.h> #include <mach/time.h>
#include "asp.h"
#include "davinci.h" #include "davinci.h"
#include "clock.h"
#include "mux.h" #include "mux.h"
#include "asp.h"
/* /*
* Device specific clocks * Device specific clocks
...@@ -43,290 +44,6 @@ ...@@ -43,290 +44,6 @@
#define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000 #define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
#define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000 #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
static struct pll_data pll1_data = {
.num = 1,
.phys_base = DAVINCI_PLL1_BASE,
};
static struct pll_data pll2_data = {
.num = 2,
.phys_base = DAVINCI_PLL2_BASE,
};
static struct clk ref_clk = {
.name = "ref_clk",
.rate = DM644X_REF_FREQ,
};
static struct clk pll1_clk = {
.name = "pll1",
.parent = &ref_clk,
.pll_data = &pll1_data,
.flags = CLK_PLL,
};
static struct clk pll1_sysclk1 = {
.name = "pll1_sysclk1",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV1,
};
static struct clk pll1_sysclk2 = {
.name = "pll1_sysclk2",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV2,
};
static struct clk pll1_sysclk3 = {
.name = "pll1_sysclk3",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV3,
};
static struct clk pll1_sysclk5 = {
.name = "pll1_sysclk5",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV5,
};
static struct clk pll1_aux_clk = {
.name = "pll1_aux_clk",
.parent = &pll1_clk,
.flags = CLK_PLL | PRE_PLL,
};
static struct clk pll1_sysclkbp = {
.name = "pll1_sysclkbp",
.parent = &pll1_clk,
.flags = CLK_PLL | PRE_PLL,
.div_reg = BPDIV
};
static struct clk pll2_clk = {
.name = "pll2",
.parent = &ref_clk,
.pll_data = &pll2_data,
.flags = CLK_PLL,
};
static struct clk pll2_sysclk1 = {
.name = "pll2_sysclk1",
.parent = &pll2_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV1,
};
static struct clk pll2_sysclk2 = {
.name = "pll2_sysclk2",
.parent = &pll2_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV2,
};
static struct clk pll2_sysclkbp = {
.name = "pll2_sysclkbp",
.parent = &pll2_clk,
.flags = CLK_PLL | PRE_PLL,
.div_reg = BPDIV
};
static struct clk dsp_clk = {
.name = "dsp",
.parent = &pll1_sysclk1,
.lpsc = DAVINCI_LPSC_GEM,
.domain = DAVINCI_GPSC_DSPDOMAIN,
.usecount = 1, /* REVISIT how to disable? */
};
static struct clk arm_clk = {
.name = "arm",
.parent = &pll1_sysclk2,
.lpsc = DAVINCI_LPSC_ARM,
.flags = ALWAYS_ENABLED,
};
static struct clk vicp_clk = {
.name = "vicp",
.parent = &pll1_sysclk2,
.lpsc = DAVINCI_LPSC_IMCOP,
.domain = DAVINCI_GPSC_DSPDOMAIN,
.usecount = 1, /* REVISIT how to disable? */
};
static struct clk vpss_master_clk = {
.name = "vpss_master",
.parent = &pll1_sysclk3,
.lpsc = DAVINCI_LPSC_VPSSMSTR,
.flags = CLK_PSC,
};
static struct clk vpss_slave_clk = {
.name = "vpss_slave",
.parent = &pll1_sysclk3,
.lpsc = DAVINCI_LPSC_VPSSSLV,
};
static struct clk uart0_clk = {
.name = "uart0",
.parent = &pll1_aux_clk,
.lpsc = DAVINCI_LPSC_UART0,
};
static struct clk uart1_clk = {
.name = "uart1",
.parent = &pll1_aux_clk,
.lpsc = DAVINCI_LPSC_UART1,
};
static struct clk uart2_clk = {
.name = "uart2",
.parent = &pll1_aux_clk,
.lpsc = DAVINCI_LPSC_UART2,
};
static struct clk emac_clk = {
.name = "emac",
.parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
};
static struct clk i2c_clk = {
.name = "i2c",
.parent = &pll1_aux_clk,
.lpsc = DAVINCI_LPSC_I2C,
};
static struct clk ide_clk = {
.name = "ide",
.parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_ATA,
};
static struct clk asp_clk = {
.name = "asp0",
.parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_McBSP,
};
static struct clk mmcsd_clk = {
.name = "mmcsd",
.parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_MMC_SD,
};
static struct clk spi_clk = {
.name = "spi",
.parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_SPI,
};
static struct clk gpio_clk = {
.name = "gpio",
.parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_GPIO,
};
static struct clk usb_clk = {
.name = "usb",
.parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_USB,
};
static struct clk vlynq_clk = {
.name = "vlynq",
.parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_VLYNQ,
};
static struct clk aemif_clk = {
.name = "aemif",
.parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_AEMIF,
};
static struct clk pwm0_clk = {
.name = "pwm0",
.parent = &pll1_aux_clk,
.lpsc = DAVINCI_LPSC_PWM0,
};
static struct clk pwm1_clk = {
.name = "pwm1",
.parent = &pll1_aux_clk,
.lpsc = DAVINCI_LPSC_PWM1,
};
static struct clk pwm2_clk = {
.name = "pwm2",
.parent = &pll1_aux_clk,
.lpsc = DAVINCI_LPSC_PWM2,
};
static struct clk timer0_clk = {
.name = "timer0",
.parent = &pll1_aux_clk,
.lpsc = DAVINCI_LPSC_TIMER0,
};
static struct clk timer1_clk = {
.name = "timer1",
.parent = &pll1_aux_clk,
.lpsc = DAVINCI_LPSC_TIMER1,
};
static struct clk timer2_clk = {
.name = "timer2",
.parent = &pll1_aux_clk,
.lpsc = DAVINCI_LPSC_TIMER2,
.usecount = 1, /* REVISIT: why can't this be disabled? */
};
static struct clk_lookup dm644x_clks[] = {
CLK(NULL, "ref", &ref_clk),
CLK(NULL, "pll1", &pll1_clk),
CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
CLK(NULL, "pll1_aux", &pll1_aux_clk),
CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
CLK(NULL, "pll2", &pll2_clk),
CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
CLK(NULL, "dsp", &dsp_clk),
CLK(NULL, "arm", &arm_clk),
CLK(NULL, "vicp", &vicp_clk),
CLK("vpss", "master", &vpss_master_clk),
CLK("vpss", "slave", &vpss_slave_clk),
CLK(NULL, "arm", &arm_clk),
CLK("serial8250.0", NULL, &uart0_clk),
CLK("serial8250.1", NULL, &uart1_clk),
CLK("serial8250.2", NULL, &uart2_clk),
CLK("davinci_emac.1", NULL, &emac_clk),
CLK("davinci_mdio.0", "fck", &emac_clk),
CLK("i2c_davinci.1", NULL, &i2c_clk),
CLK("palm_bk3710", NULL, &ide_clk),
CLK("davinci-mcbsp", NULL, &asp_clk),
CLK("dm6441-mmc.0", NULL, &mmcsd_clk),
CLK(NULL, "spi", &spi_clk),
CLK(NULL, "gpio", &gpio_clk),
CLK(NULL, "usb", &usb_clk),
CLK(NULL, "vlynq", &vlynq_clk),
CLK(NULL, "aemif", &aemif_clk),
CLK(NULL, "pwm0", &pwm0_clk),
CLK(NULL, "pwm1", &pwm1_clk),
CLK(NULL, "pwm2", &pwm2_clk),
CLK(NULL, "timer0", &timer0_clk),
CLK(NULL, "timer1", &timer1_clk),
CLK("davinci-wdt", NULL, &timer2_clk),
CLK(NULL, NULL, NULL),
};
static struct emac_platform_data dm644x_emac_pdata = { static struct emac_platform_data dm644x_emac_pdata = {
.ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET, .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
.ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET, .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
...@@ -819,8 +536,6 @@ static struct davinci_id dm644x_ids[] = { ...@@ -819,8 +536,6 @@ static struct davinci_id dm644x_ids[] = {
}, },
}; };
static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
/* /*
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
* T0_TOP: Timer 0, top : clocksource for generic timekeeping * T0_TOP: Timer 0, top : clocksource for generic timekeeping
...@@ -905,8 +620,6 @@ static const struct davinci_soc_info davinci_soc_info_dm644x = { ...@@ -905,8 +620,6 @@ static const struct davinci_soc_info davinci_soc_info_dm644x = {
.jtag_id_reg = 0x01c40028, .jtag_id_reg = 0x01c40028,
.ids = dm644x_ids, .ids = dm644x_ids,
.ids_num = ARRAY_SIZE(dm644x_ids), .ids_num = ARRAY_SIZE(dm644x_ids),
.psc_bases = dm644x_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm644x_pins, .pinmux_pins = dm644x_pins,
.pinmux_pins_num = ARRAY_SIZE(dm644x_pins), .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
...@@ -934,8 +647,41 @@ void __init dm644x_init(void) ...@@ -934,8 +647,41 @@ void __init dm644x_init(void)
void __init dm644x_init_time(void) void __init dm644x_init_time(void)
{ {
davinci_clk_init(dm644x_clks); void __iomem *pll1, *psc;
davinci_timer_init(); struct clk *clk;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
dm644x_pll1_init(NULL, pll1, NULL);
psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
dm644x_psc_init(NULL, psc);
clk = clk_get(NULL, "timer0");
davinci_timer_init(clk);
}
static struct resource dm644x_pll2_resources[] = {
{
.start = DAVINCI_PLL2_BASE,
.end = DAVINCI_PLL2_BASE + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device dm644x_pll2_device = {
.name = "dm644x-pll2",
.id = -1,
.resource = dm644x_pll2_resources,
.num_resources = ARRAY_SIZE(dm644x_pll2_resources),
};
void __init dm644x_register_clocks(void)
{
/* PLL1 and PSC are registered in dm644x_init_time() */
platform_device_register(&dm644x_pll2_device);
} }
int __init dm644x_init_video(struct vpfe_config *vpfe_cfg, int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
......
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...@@ -15,9 +15,6 @@ ...@@ -15,9 +15,6 @@
struct clk; struct clk;
extern int clk_register(struct clk *clk);
extern void clk_unregister(struct clk *clk);
int davinci_clk_reset_assert(struct clk *c); int davinci_clk_reset_assert(struct clk *c);
int davinci_clk_reset_deassert(struct clk *c); int davinci_clk_reset_deassert(struct clk *c);
......
...@@ -12,11 +12,12 @@ ...@@ -12,11 +12,12 @@
#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
#define __ARCH_ARM_MACH_DAVINCI_COMMON_H #define __ARCH_ARM_MACH_DAVINCI_COMMON_H
#include <linux/clk.h>
#include <linux/compiler.h> #include <linux/compiler.h>
#include <linux/types.h> #include <linux/types.h>
#include <linux/reboot.h> #include <linux/reboot.h>
extern void davinci_timer_init(void); void davinci_timer_init(struct clk *clk);
extern void davinci_irq_init(void); extern void davinci_irq_init(void);
extern void __iomem *davinci_intc_base; extern void __iomem *davinci_intc_base;
...@@ -53,8 +54,6 @@ struct davinci_soc_info { ...@@ -53,8 +54,6 @@ struct davinci_soc_info {
u32 jtag_id_reg; u32 jtag_id_reg;
struct davinci_id *ids; struct davinci_id *ids;
unsigned long ids_num; unsigned long ids_num;
u32 *psc_bases;
unsigned long psc_bases_num;
u32 pinmux_base; u32 pinmux_base;
const struct mux_config *pinmux_pins; const struct mux_config *pinmux_pins;
unsigned long pinmux_pins_num; unsigned long pinmux_pins_num;
...@@ -82,12 +81,6 @@ extern void davinci_common_init(const struct davinci_soc_info *soc_info); ...@@ -82,12 +81,6 @@ extern void davinci_common_init(const struct davinci_soc_info *soc_info);
extern void davinci_init_ide(void); extern void davinci_init_ide(void);
void davinci_init_late(void); void davinci_init_late(void);
#ifdef CONFIG_DAVINCI_RESET_CLOCKS
int davinci_clk_disable_unused(void);
#else
static inline int davinci_clk_disable_unused(void) { return 0; }
#endif
#ifdef CONFIG_CPU_FREQ #ifdef CONFIG_CPU_FREQ
int davinci_cpufreq_init(void); int davinci_cpufreq_init(void);
#else #else
......
...@@ -89,9 +89,11 @@ extern unsigned int da850_max_speed; ...@@ -89,9 +89,11 @@ extern unsigned int da850_max_speed;
void da830_init(void); void da830_init(void);
void da830_init_time(void); void da830_init_time(void);
void da830_register_clocks(void);
void da850_init(void); void da850_init(void);
void da850_init_time(void); void da850_init_time(void);
void da850_register_clocks(void);
int da830_register_edma(struct edma_rsv_info *rsv); int da830_register_edma(struct edma_rsv_info *rsv);
int da850_register_edma(struct edma_rsv_info *rsv[2]); int da850_register_edma(struct edma_rsv_info *rsv[2]);
...@@ -101,9 +103,7 @@ int da8xx_register_watchdog(void); ...@@ -101,9 +103,7 @@ int da8xx_register_watchdog(void);
int da8xx_register_usb_phy(void); int da8xx_register_usb_phy(void);
int da8xx_register_usb20(unsigned mA, unsigned potpgt); int da8xx_register_usb20(unsigned mA, unsigned potpgt);
int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata); int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
int da8xx_register_usb_refclkin(int rate); int da8xx_register_usb_phy_clocks(void);
int da8xx_register_usb20_phy_clk(bool use_usb_refclkin);
int da8xx_register_usb11_phy_clk(bool use_usb_refclkin);
int da850_register_sata_refclk(int rate); int da850_register_sata_refclk(int rate);
int da8xx_register_emac(void); int da8xx_register_emac(void);
int da8xx_register_uio_pruss(void); int da8xx_register_uio_pruss(void);
......
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
#include <linux/pm_clock.h> #include <linux/pm_clock.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/of.h>
static struct dev_pm_domain davinci_pm_domain = { static struct dev_pm_domain davinci_pm_domain = {
.ops = { .ops = {
...@@ -28,6 +29,10 @@ static struct pm_clk_notifier_block platform_bus_notifier = { ...@@ -28,6 +29,10 @@ static struct pm_clk_notifier_block platform_bus_notifier = {
static int __init davinci_pm_runtime_init(void) static int __init davinci_pm_runtime_init(void)
{ {
if (of_have_populated_dt())
return 0;
/* Use pm_clk as fallback if we're not using genpd. */
pm_clk_add_notifier(&platform_bus_type, &platform_bus_notifier); pm_clk_add_notifier(&platform_bus_type, &platform_bus_notifier);
return 0; return 0;
......
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...@@ -27,8 +27,6 @@ ...@@ -27,8 +27,6 @@
#ifndef __ASM_ARCH_PSC_H #ifndef __ASM_ARCH_PSC_H
#define __ASM_ARCH_PSC_H #define __ASM_ARCH_PSC_H
#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
/* Power and Sleep Controller (PSC) Domains */ /* Power and Sleep Controller (PSC) Domains */
#define DAVINCI_GPSC_ARMDOMAIN 0 #define DAVINCI_GPSC_ARMDOMAIN 0
#define DAVINCI_GPSC_DSPDOMAIN 1 #define DAVINCI_GPSC_DSPDOMAIN 1
...@@ -206,14 +204,4 @@ ...@@ -206,14 +204,4 @@
#define PDCTL_NEXT BIT(0) #define PDCTL_NEXT BIT(0)
#define PDCTL_EPCGOOD BIT(8) #define PDCTL_EPCGOOD BIT(8)
#ifndef __ASSEMBLER__
extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
extern void davinci_psc_reset(unsigned int ctlr, unsigned int id,
bool reset);
extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
unsigned int id, bool enable, u32 flags);
#endif
#endif /* __ASM_ARCH_PSC_H */ #endif /* __ASM_ARCH_PSC_H */
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...@@ -190,8 +190,6 @@ static void __init exynos_dt_fixup(void) ...@@ -190,8 +190,6 @@ static void __init exynos_dt_fixup(void)
} }
DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)") DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.l2c_aux_val = 0x3c400001, .l2c_aux_val = 0x3c400001,
.l2c_aux_mask = 0xc20fffff, .l2c_aux_mask = 0xc20fffff,
.smp = smp_ops(exynos_smp_ops), .smp = smp_ops(exynos_smp_ops),
......
...@@ -203,6 +203,7 @@ static int __init exynos_pmu_irq_init(struct device_node *node, ...@@ -203,6 +203,7 @@ static int __init exynos_pmu_irq_init(struct device_node *node,
NULL); NULL);
if (!domain) { if (!domain) {
iounmap(pmu_base_addr); iounmap(pmu_base_addr);
pmu_base_addr = NULL;
return -ENOMEM; return -ENOMEM;
} }
......
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...@@ -68,6 +68,7 @@ void __init imx_aips_allow_unprivileged_access( ...@@ -68,6 +68,7 @@ void __init imx_aips_allow_unprivileged_access(
for_each_compatible_node(np, NULL, compat) { for_each_compatible_node(np, NULL, compat) {
aips_base_addr = of_iomap(np, 0); aips_base_addr = of_iomap(np, 0);
WARN_ON(!aips_base_addr);
imx_set_aips(aips_base_addr); imx_set_aips(aips_base_addr);
} }
} }
......
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