Commit 9f817501 authored by Sagar Arun Kamble's avatar Sagar Arun Kamble Committed by Chris Wilson

drm/i915: Move rps.hw_lock to dev_priv and s/hw_lock/pcu_lock

In order to separate GT PM related functionality into new structure
we are updating rps structure. hw_lock in it is used for display
related PCU communication too hence move it to dev_priv.
Signed-off-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-8-git-send-email-sagar.a.kamble@intel.comAcked-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010213010.7415-7-chris@chris-wilson.co.uk
parent ad1443f0
...@@ -1097,7 +1097,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) ...@@ -1097,7 +1097,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
u32 rpmodectl, freq_sts; u32 rpmodectl, freq_sts;
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
rpmodectl = I915_READ(GEN6_RP_CONTROL); rpmodectl = I915_READ(GEN6_RP_CONTROL);
seq_printf(m, "Video Turbo Mode: %s\n", seq_printf(m, "Video Turbo Mode: %s\n",
...@@ -1130,7 +1130,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) ...@@ -1130,7 +1130,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_printf(m, seq_printf(m,
"efficient (RPe) frequency: %d MHz\n", "efficient (RPe) frequency: %d MHz\n",
intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
} else if (INTEL_GEN(dev_priv) >= 6) { } else if (INTEL_GEN(dev_priv) >= 6) {
u32 rp_state_limits; u32 rp_state_limits;
u32 gt_perf_status; u32 gt_perf_status;
...@@ -1565,9 +1565,9 @@ static int gen6_drpc_info(struct seq_file *m) ...@@ -1565,9 +1565,9 @@ static int gen6_drpc_info(struct seq_file *m)
gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
} }
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
seq_printf(m, "RC1e Enabled: %s\n", seq_printf(m, "RC1e Enabled: %s\n",
yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
...@@ -1842,7 +1842,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) ...@@ -1842,7 +1842,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
intel_runtime_pm_get(dev_priv); intel_runtime_pm_get(dev_priv);
ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
if (ret) if (ret)
goto out; goto out;
...@@ -1873,7 +1873,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) ...@@ -1873,7 +1873,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
((ia_freq >> 8) & 0xff) * 100); ((ia_freq >> 8) & 0xff) * 100);
} }
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
out: out:
intel_runtime_pm_put(dev_priv); intel_runtime_pm_put(dev_priv);
...@@ -4320,7 +4320,7 @@ i915_max_freq_set(void *data, u64 val) ...@@ -4320,7 +4320,7 @@ i915_max_freq_set(void *data, u64 val)
DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
if (ret) if (ret)
return ret; return ret;
...@@ -4333,7 +4333,7 @@ i915_max_freq_set(void *data, u64 val) ...@@ -4333,7 +4333,7 @@ i915_max_freq_set(void *data, u64 val)
hw_min = dev_priv->rps.min_freq; hw_min = dev_priv->rps.min_freq;
if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
return -EINVAL; return -EINVAL;
} }
...@@ -4342,7 +4342,7 @@ i915_max_freq_set(void *data, u64 val) ...@@ -4342,7 +4342,7 @@ i915_max_freq_set(void *data, u64 val)
if (intel_set_rps(dev_priv, val)) if (intel_set_rps(dev_priv, val))
DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
return 0; return 0;
} }
...@@ -4375,7 +4375,7 @@ i915_min_freq_set(void *data, u64 val) ...@@ -4375,7 +4375,7 @@ i915_min_freq_set(void *data, u64 val)
DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
if (ret) if (ret)
return ret; return ret;
...@@ -4389,7 +4389,7 @@ i915_min_freq_set(void *data, u64 val) ...@@ -4389,7 +4389,7 @@ i915_min_freq_set(void *data, u64 val)
if (val < hw_min || if (val < hw_min ||
val > hw_max || val > dev_priv->rps.max_freq_softlimit) { val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
return -EINVAL; return -EINVAL;
} }
...@@ -4398,7 +4398,7 @@ i915_min_freq_set(void *data, u64 val) ...@@ -4398,7 +4398,7 @@ i915_min_freq_set(void *data, u64 val)
if (intel_set_rps(dev_priv, val)) if (intel_set_rps(dev_priv, val))
DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
return 0; return 0;
} }
......
...@@ -1364,14 +1364,6 @@ struct intel_gen6_power_mgmt { ...@@ -1364,14 +1364,6 @@ struct intel_gen6_power_mgmt {
/* manual wa residency calculations */ /* manual wa residency calculations */
struct intel_rps_ei ei; struct intel_rps_ei ei;
/*
* Protects RPS/RC6 register access and PCU communication.
* Must be taken after struct_mutex if nested. Note that
* this lock may be held for long periods of time when
* talking to hw - so only take it when talking to hw!
*/
struct mutex hw_lock;
}; };
/* defined intel_pm.c */ /* defined intel_pm.c */
...@@ -2421,6 +2413,14 @@ struct drm_i915_private { ...@@ -2421,6 +2413,14 @@ struct drm_i915_private {
/* Cannot be determined by PCIID. You must always read a register. */ /* Cannot be determined by PCIID. You must always read a register. */
u32 edram_cap; u32 edram_cap;
/*
* Protects RPS/RC6 register access and PCU communication.
* Must be taken after struct_mutex if nested. Note that
* this lock may be held for long periods of time when
* talking to hw - so only take it when talking to hw!
*/
struct mutex pcu_lock;
/* gen6+ rps state */ /* gen6+ rps state */
struct intel_gen6_power_mgmt rps; struct intel_gen6_power_mgmt rps;
......
...@@ -1181,7 +1181,7 @@ static void gen6_pm_rps_work(struct work_struct *work) ...@@ -1181,7 +1181,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
goto out; goto out;
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
...@@ -1235,7 +1235,7 @@ static void gen6_pm_rps_work(struct work_struct *work) ...@@ -1235,7 +1235,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
dev_priv->rps.last_adj = 0; dev_priv->rps.last_adj = 0;
} }
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
out: out:
/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
......
...@@ -246,7 +246,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev, ...@@ -246,7 +246,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
intel_runtime_pm_get(dev_priv); intel_runtime_pm_get(dev_priv);
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
u32 freq; u32 freq;
freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
...@@ -261,7 +261,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev, ...@@ -261,7 +261,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
ret = intel_gpu_freq(dev_priv, ret); ret = intel_gpu_freq(dev_priv, ret);
} }
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
intel_runtime_pm_put(dev_priv); intel_runtime_pm_put(dev_priv);
...@@ -304,9 +304,9 @@ static ssize_t gt_boost_freq_mhz_store(struct device *kdev, ...@@ -304,9 +304,9 @@ static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
if (val < dev_priv->rps.min_freq || val > dev_priv->rps.max_freq) if (val < dev_priv->rps.min_freq || val > dev_priv->rps.max_freq)
return -EINVAL; return -EINVAL;
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
dev_priv->rps.boost_freq = val; dev_priv->rps.boost_freq = val;
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
return count; return count;
} }
...@@ -344,14 +344,14 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, ...@@ -344,14 +344,14 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
intel_runtime_pm_get(dev_priv); intel_runtime_pm_get(dev_priv);
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
val = intel_freq_opcode(dev_priv, val); val = intel_freq_opcode(dev_priv, val);
if (val < dev_priv->rps.min_freq || if (val < dev_priv->rps.min_freq ||
val > dev_priv->rps.max_freq || val > dev_priv->rps.max_freq ||
val < dev_priv->rps.min_freq_softlimit) { val < dev_priv->rps.min_freq_softlimit) {
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
intel_runtime_pm_put(dev_priv); intel_runtime_pm_put(dev_priv);
return -EINVAL; return -EINVAL;
} }
...@@ -371,7 +371,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, ...@@ -371,7 +371,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
* frequency request may be unchanged. */ * frequency request may be unchanged. */
ret = intel_set_rps(dev_priv, val); ret = intel_set_rps(dev_priv, val);
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
intel_runtime_pm_put(dev_priv); intel_runtime_pm_put(dev_priv);
...@@ -401,14 +401,14 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, ...@@ -401,14 +401,14 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
intel_runtime_pm_get(dev_priv); intel_runtime_pm_get(dev_priv);
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
val = intel_freq_opcode(dev_priv, val); val = intel_freq_opcode(dev_priv, val);
if (val < dev_priv->rps.min_freq || if (val < dev_priv->rps.min_freq ||
val > dev_priv->rps.max_freq || val > dev_priv->rps.max_freq ||
val > dev_priv->rps.max_freq_softlimit) { val > dev_priv->rps.max_freq_softlimit) {
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
intel_runtime_pm_put(dev_priv); intel_runtime_pm_put(dev_priv);
return -EINVAL; return -EINVAL;
} }
...@@ -424,7 +424,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, ...@@ -424,7 +424,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
* frequency request may be unchanged. */ * frequency request may be unchanged. */
ret = intel_set_rps(dev_priv, val); ret = intel_set_rps(dev_priv, val);
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
intel_runtime_pm_put(dev_priv); intel_runtime_pm_put(dev_priv);
......
...@@ -503,7 +503,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -503,7 +503,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
else else
cmd = 0; cmd = 0;
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
val &= ~DSPFREQGUAR_MASK; val &= ~DSPFREQGUAR_MASK;
val |= (cmd << DSPFREQGUAR_SHIFT); val |= (cmd << DSPFREQGUAR_SHIFT);
...@@ -513,7 +513,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -513,7 +513,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
50)) { 50)) {
DRM_ERROR("timed out waiting for CDclk change\n"); DRM_ERROR("timed out waiting for CDclk change\n");
} }
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
mutex_lock(&dev_priv->sb_lock); mutex_lock(&dev_priv->sb_lock);
...@@ -590,7 +590,7 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -590,7 +590,7 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
*/ */
cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
val &= ~DSPFREQGUAR_MASK_CHV; val &= ~DSPFREQGUAR_MASK_CHV;
val |= (cmd << DSPFREQGUAR_SHIFT_CHV); val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
...@@ -600,7 +600,7 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -600,7 +600,7 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
50)) { 50)) {
DRM_ERROR("timed out waiting for CDclk change\n"); DRM_ERROR("timed out waiting for CDclk change\n");
} }
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
intel_update_cdclk(dev_priv); intel_update_cdclk(dev_priv);
...@@ -656,10 +656,10 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -656,10 +656,10 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
"trying to change cdclk frequency with cdclk not enabled\n")) "trying to change cdclk frequency with cdclk not enabled\n"))
return; return;
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
ret = sandybridge_pcode_write(dev_priv, ret = sandybridge_pcode_write(dev_priv,
BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
if (ret) { if (ret) {
DRM_ERROR("failed to inform pcode about cdclk change\n"); DRM_ERROR("failed to inform pcode about cdclk change\n");
return; return;
...@@ -712,9 +712,9 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -712,9 +712,9 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
DRM_ERROR("Switching back to LCPLL failed\n"); DRM_ERROR("Switching back to LCPLL failed\n");
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
...@@ -928,12 +928,12 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -928,12 +928,12 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
WARN_ON((cdclk == 24000) != (vco == 0)); WARN_ON((cdclk == 24000) != (vco == 0));
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
SKL_CDCLK_PREPARE_FOR_CHANGE, SKL_CDCLK_PREPARE_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE, SKL_CDCLK_READY_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE, 3); SKL_CDCLK_READY_FOR_CHANGE, 3);
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
if (ret) { if (ret) {
DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
ret); ret);
...@@ -975,9 +975,9 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -975,9 +975,9 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
POSTING_READ(CDCLK_CTL); POSTING_READ(CDCLK_CTL);
/* inform PCU of the change */ /* inform PCU of the change */
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
intel_update_cdclk(dev_priv); intel_update_cdclk(dev_priv);
} }
...@@ -1268,10 +1268,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -1268,10 +1268,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
} }
/* Inform power controller of upcoming frequency change */ /* Inform power controller of upcoming frequency change */
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
0x80000000); 0x80000000);
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
if (ret) { if (ret) {
DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
...@@ -1300,10 +1300,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -1300,10 +1300,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
I915_WRITE(CDCLK_CTL, val); I915_WRITE(CDCLK_CTL, val);
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
DIV_ROUND_UP(cdclk, 25000)); DIV_ROUND_UP(cdclk, 25000));
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
if (ret) { if (ret) {
DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
...@@ -1518,12 +1518,12 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -1518,12 +1518,12 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
u32 val, divider, pcu_ack; u32 val, divider, pcu_ack;
int ret; int ret;
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
SKL_CDCLK_PREPARE_FOR_CHANGE, SKL_CDCLK_PREPARE_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE, SKL_CDCLK_READY_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE, 3); SKL_CDCLK_READY_FOR_CHANGE, 3);
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
if (ret) { if (ret) {
DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
ret); ret);
...@@ -1575,9 +1575,9 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -1575,9 +1575,9 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
I915_WRITE(CDCLK_CTL, val); I915_WRITE(CDCLK_CTL, val);
/* inform PCU of the change */ /* inform PCU of the change */
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
intel_update_cdclk(dev_priv); intel_update_cdclk(dev_priv);
} }
......
...@@ -4946,10 +4946,10 @@ void hsw_enable_ips(struct intel_crtc *crtc) ...@@ -4946,10 +4946,10 @@ void hsw_enable_ips(struct intel_crtc *crtc)
assert_plane_enabled(dev_priv, crtc->plane); assert_plane_enabled(dev_priv, crtc->plane);
if (IS_BROADWELL(dev_priv)) { if (IS_BROADWELL(dev_priv)) {
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
IPS_ENABLE | IPS_PCODE_CONTROL)); IPS_ENABLE | IPS_PCODE_CONTROL));
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
/* Quoting Art Runyan: "its not safe to expect any particular /* Quoting Art Runyan: "its not safe to expect any particular
* value in IPS_CTL bit 31 after enabling IPS through the * value in IPS_CTL bit 31 after enabling IPS through the
* mailbox." Moreover, the mailbox may return a bogus state, * mailbox." Moreover, the mailbox may return a bogus state,
...@@ -4979,9 +4979,9 @@ void hsw_disable_ips(struct intel_crtc *crtc) ...@@ -4979,9 +4979,9 @@ void hsw_disable_ips(struct intel_crtc *crtc)
assert_plane_enabled(dev_priv, crtc->plane); assert_plane_enabled(dev_priv, crtc->plane);
if (IS_BROADWELL(dev_priv)) { if (IS_BROADWELL(dev_priv)) {
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
/* wait for pcode to finish disabling IPS, which may take up to 42ms */ /* wait for pcode to finish disabling IPS, which may take up to 42ms */
if (intel_wait_for_register(dev_priv, if (intel_wait_for_register(dev_priv,
IPS_CTL, IPS_ENABLE, 0, IPS_CTL, IPS_ENABLE, 0,
...@@ -8839,11 +8839,11 @@ static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) ...@@ -8839,11 +8839,11 @@ static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
{ {
if (IS_HASWELL(dev_priv)) { if (IS_HASWELL(dev_priv)) {
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
val)) val))
DRM_DEBUG_KMS("Failed to write to D_COMP\n"); DRM_DEBUG_KMS("Failed to write to D_COMP\n");
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
} else { } else {
I915_WRITE(D_COMP_BDW, val); I915_WRITE(D_COMP_BDW, val);
POSTING_READ(D_COMP_BDW); POSTING_READ(D_COMP_BDW);
......
This diff is collapsed.
...@@ -785,7 +785,7 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv, ...@@ -785,7 +785,7 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv,
state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
PUNIT_PWRGT_PWR_GATE(power_well_id); PUNIT_PWRGT_PWR_GATE(power_well_id);
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
#define COND \ #define COND \
((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
...@@ -806,7 +806,7 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv, ...@@ -806,7 +806,7 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv,
#undef COND #undef COND
out: out:
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
} }
static void vlv_power_well_enable(struct drm_i915_private *dev_priv, static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
...@@ -833,7 +833,7 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, ...@@ -833,7 +833,7 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
mask = PUNIT_PWRGT_MASK(power_well_id); mask = PUNIT_PWRGT_MASK(power_well_id);
ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
/* /*
...@@ -852,7 +852,7 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, ...@@ -852,7 +852,7 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
WARN_ON(ctrl != state); WARN_ON(ctrl != state);
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
return enabled; return enabled;
} }
...@@ -1364,7 +1364,7 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, ...@@ -1364,7 +1364,7 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
bool enabled; bool enabled;
u32 state, ctrl; u32 state, ctrl;
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
/* /*
...@@ -1381,7 +1381,7 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, ...@@ -1381,7 +1381,7 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
WARN_ON(ctrl << 16 != state); WARN_ON(ctrl << 16 != state);
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
return enabled; return enabled;
} }
...@@ -1396,7 +1396,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, ...@@ -1396,7 +1396,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->pcu_lock);
#define COND \ #define COND \
((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
...@@ -1417,7 +1417,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, ...@@ -1417,7 +1417,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
#undef COND #undef COND
out: out:
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->pcu_lock);
} }
static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
......
...@@ -81,7 +81,7 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr) ...@@ -81,7 +81,7 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr)
{ {
u32 val = 0; u32 val = 0;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
mutex_lock(&dev_priv->sb_lock); mutex_lock(&dev_priv->sb_lock);
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT, vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
...@@ -95,7 +95,7 @@ int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val) ...@@ -95,7 +95,7 @@ int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val)
{ {
int err; int err;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
mutex_lock(&dev_priv->sb_lock); mutex_lock(&dev_priv->sb_lock);
err = vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT, err = vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
...@@ -125,7 +125,7 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) ...@@ -125,7 +125,7 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
{ {
u32 val = 0; u32 val = 0;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
mutex_lock(&dev_priv->sb_lock); mutex_lock(&dev_priv->sb_lock);
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC, vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC,
......
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