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Commit a12e6062 authored by Linus Torvalds's avatar Linus Torvalds
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Merge master.kernel.org:/home/rmk/linux-2.6-arm 

* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 4694/1: IXP4xx: Update clockevent support for shutdown and resume
  [ARM] 4710/1: Fix coprocessor 14 usage for debug messages via ICEDCC
  [ARM] 4690/1: PXA: fix CKEN corruption in PXA27x AC97 cold reset code
  [ARM] 4667/1: CM-X270 fixes
parents aa62a869 553876c8
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Showing with 30 additions and 27 deletions
arch/arm/Kconfig
View file @ a12e6062
...@@ -537,7 +537,7 @@ config ISA_DMA_API ...@@ -537,7 +537,7 @@ config ISA_DMA_API
bool bool
config PCI config PCI
bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
help help
Find out whether you have a PCI motherboard. PCI is the name of a Find out whether you have a PCI motherboard. PCI is the name of a
bus system, i.e. the way the CPU talks to the other stuff inside bus system, i.e. the way the CPU talks to the other stuff inside
...@@ -558,6 +558,12 @@ config PCI_HOST_VIA82C505 ...@@ -558,6 +558,12 @@ config PCI_HOST_VIA82C505
depends on PCI && ARCH_SHARK depends on PCI && ARCH_SHARK
default y default y
config PCI_HOST_ITE8152
bool
depends on PCI && MACH_ARMCORE
default y
select DMABOUNCE
source "drivers/pci/Kconfig" source "drivers/pci/Kconfig"
source "drivers/pcmcia/Kconfig" source "drivers/pcmcia/Kconfig"
......
arch/arm/boot/compressed/head.S
View file @ a12e6062
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
.macro loadsp, rb .macro loadsp, rb
.endm .endm
.macro writeb, ch, rb .macro writeb, ch, rb
mcr p14, 0, \ch, c0, c1, 0 mcr p14, 0, \ch, c1, c0, 0
.endm .endm
#endif #endif
......
arch/arm/common/it8152.c
View file @ a12e6062
...@@ -70,8 +70,6 @@ static inline void it8152_irq(int irq) ...@@ -70,8 +70,6 @@ static inline void it8152_irq(int irq)
{ {
struct irq_desc *desc; struct irq_desc *desc;
printk(KERN_DEBUG "===> %s: irq=%d\n", __FUNCTION__, irq);
desc = irq_desc + irq; desc = irq_desc + irq;
desc_handle_irq(irq, desc); desc_handle_irq(irq, desc);
} }
...@@ -106,8 +104,6 @@ void it8152_irq_demux(unsigned int irq, struct irq_desc *desc) ...@@ -106,8 +104,6 @@ void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
int bits_pd, bits_lp, bits_ld; int bits_pd, bits_lp, bits_ld;
int i; int i;
printk(KERN_DEBUG "=> %s: irq = %d\n", __FUNCTION__, irq);
while (1) { while (1) {
/* Read all */ /* Read all */
bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
...@@ -293,8 +289,7 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) ...@@ -293,8 +289,7 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
*/ */
int pci_set_dma_mask(struct pci_dev *dev, u64 mask) int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
{ {
printk(KERN_DEBUG "%s: %s %llx\n", dev_dbg(&dev->dev, "%s: %llx\n", __FUNCTION__, mask);
__FUNCTION__, dev->dev.bus_id, mask);
if (mask >= PHYS_OFFSET + SZ_64M - 1) if (mask >= PHYS_OFFSET + SZ_64M - 1)
return 0; return 0;
...@@ -304,8 +299,7 @@ int pci_set_dma_mask(struct pci_dev *dev, u64 mask) ...@@ -304,8 +299,7 @@ int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
int int
pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
{ {
printk(KERN_DEBUG "%s: %s %llx\n", dev_dbg(&dev->dev, "%s: %llx\n", __FUNCTION__, mask);
__FUNCTION__, dev->dev.bus_id, mask);
if (mask >= PHYS_OFFSET + SZ_64M - 1) if (mask >= PHYS_OFFSET + SZ_64M - 1)
return 0; return 0;
......
arch/arm/mach-ixp4xx/common.c
View file @ a12e6062
...@@ -442,7 +442,8 @@ static int ixp4xx_set_next_event(unsigned long evt, ...@@ -442,7 +442,8 @@ static int ixp4xx_set_next_event(unsigned long evt,
static void ixp4xx_set_mode(enum clock_event_mode mode, static void ixp4xx_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt) struct clock_event_device *evt)
{ {
unsigned long opts, osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK; unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
switch (mode) { switch (mode) {
case CLOCK_EVT_MODE_PERIODIC: case CLOCK_EVT_MODE_PERIODIC:
...@@ -455,12 +456,15 @@ static void ixp4xx_set_mode(enum clock_event_mode mode, ...@@ -455,12 +456,15 @@ static void ixp4xx_set_mode(enum clock_event_mode mode,
opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT; opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
break; break;
case CLOCK_EVT_MODE_SHUTDOWN: case CLOCK_EVT_MODE_SHUTDOWN:
opts &= ~IXP4XX_OST_ENABLE;
break;
case CLOCK_EVT_MODE_RESUME:
opts |= IXP4XX_OST_ENABLE;
break;
case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_UNUSED:
default: default:
osrt = opts = 0; osrt = opts = 0;
break; break;
case CLOCK_EVT_MODE_RESUME:
break;
} }
*IXP4XX_OSRT1 = osrt | opts; *IXP4XX_OSRT1 = osrt | opts;
......
arch/arm/mach-pxa/cm-x270-pci.c
View file @ a12e6062
...@@ -40,7 +40,7 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size, ...@@ -40,7 +40,7 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
{ {
unsigned int sz = SZ_64M >> PAGE_SHIFT; unsigned int sz = SZ_64M >> PAGE_SHIFT;
printk(KERN_INFO "Adjusting zones for CM-x270\n"); pr_info("Adjusting zones for CM-x270\n");
/* /*
* Only adjust if > 64M on current system * Only adjust if > 64M on current system
...@@ -104,8 +104,7 @@ static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) ...@@ -104,8 +104,7 @@ static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{ {
int irq; int irq;
printk(KERN_DEBUG "===> %s: %s slot=%x, pin=%x\n", __FUNCTION__, dev_dbg(&dev->dev, "%s: slot=%x, pin=%x\n", __FUNCTION__, slot, pin);
pci_name(dev), slot, pin);
irq = it8152_pci_map_irq(dev, slot, pin); irq = it8152_pci_map_irq(dev, slot, pin);
if (irq) if (irq)
...@@ -141,14 +140,13 @@ static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) ...@@ -141,14 +140,13 @@ static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
return(0); return(0);
} }
static struct pci_bus * __init static void cmx270_pci_preinit(void)
cmx270_pci_scan_bus(int nr, struct pci_sys_data *sys)
{ {
printk(KERN_INFO "Initializing CM-X270 PCI subsystem\n"); pr_info("Initializing CM-X270 PCI subsystem\n");
__raw_writel(0x800, IT8152_PCI_CFG_ADDR); __raw_writel(0x800, IT8152_PCI_CFG_ADDR);
if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) { if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
printk(KERN_INFO "PCI Bridge found.\n"); pr_info("PCI Bridge found.\n");
/* set PCI I/O base at 0 */ /* set PCI I/O base at 0 */
writel(0x848, IT8152_PCI_CFG_ADDR); writel(0x848, IT8152_PCI_CFG_ADDR);
...@@ -163,7 +161,7 @@ cmx270_pci_scan_bus(int nr, struct pci_sys_data *sys) ...@@ -163,7 +161,7 @@ cmx270_pci_scan_bus(int nr, struct pci_sys_data *sys)
/* CardBus Controller on ATXbase baseboard */ /* CardBus Controller on ATXbase baseboard */
writel(0x4000, IT8152_PCI_CFG_ADDR); writel(0x4000, IT8152_PCI_CFG_ADDR);
if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) { if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) {
printk(KERN_INFO "CardBus Bridge found.\n"); pr_info("CardBus Bridge found.\n");
/* Configure socket 0 */ /* Configure socket 0 */
writel(0x408C, IT8152_PCI_CFG_ADDR); writel(0x408C, IT8152_PCI_CFG_ADDR);
...@@ -196,7 +194,6 @@ cmx270_pci_scan_bus(int nr, struct pci_sys_data *sys) ...@@ -196,7 +194,6 @@ cmx270_pci_scan_bus(int nr, struct pci_sys_data *sys)
writel(0xb0000000, IT8152_PCI_CFG_DATA); writel(0xb0000000, IT8152_PCI_CFG_DATA);
} }
} }
return it8152_pci_scan_bus(nr, sys);
} }
static struct hw_pci cmx270_pci __initdata = { static struct hw_pci cmx270_pci __initdata = {
...@@ -204,7 +201,8 @@ static struct hw_pci cmx270_pci __initdata = { ...@@ -204,7 +201,8 @@ static struct hw_pci cmx270_pci __initdata = {
.map_irq = cmx270_pci_map_irq, .map_irq = cmx270_pci_map_irq,
.nr_controllers = 1, .nr_controllers = 1,
.setup = it8152_pci_setup, .setup = it8152_pci_setup,
.scan = cmx270_pci_scan_bus, .scan = it8152_pci_scan_bus,
.preinit = cmx270_pci_preinit,
}; };
static int __init cmx270_init_pci(void) static int __init cmx270_init_pci(void)
......
include/asm-arm/arch-pxa/pxa-regs.h
View file @ a12e6062
...@@ -1784,6 +1784,7 @@ ...@@ -1784,6 +1784,7 @@
#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */ #define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */ #define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
#define CKEN_MEMC (22) /* Memory Controller Clock Enable */ #define CKEN_MEMC (22) /* Memory Controller Clock Enable */
......
sound/arm/pxa2xx-ac97.c
View file @ a12e6062
...@@ -113,9 +113,9 @@ static void pxa2xx_ac97_reset(struct snd_ac97 *ac97) ...@@ -113,9 +113,9 @@ static void pxa2xx_ac97_reset(struct snd_ac97 *ac97)
gsr_bits = 0; gsr_bits = 0;
#ifdef CONFIG_PXA27x #ifdef CONFIG_PXA27x
/* PXA27x Developers Manual section 13.5.2.2.1 */ /* PXA27x Developers Manual section 13.5.2.2.1 */
pxa_set_cken(1 << 31, 1); pxa_set_cken(CKEN_AC97CONF, 1);
udelay(5); udelay(5);
pxa_set_cken(1 << 31, 0); pxa_set_cken(CKEN_AC97CONF, 0);
GCR = GCR_COLD_RST; GCR = GCR_COLD_RST;
udelay(50); udelay(50);
#else #else
......
sound/soc/pxa/pxa2xx-ac97.c
View file @ a12e6062
...@@ -160,9 +160,9 @@ static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97) ...@@ -160,9 +160,9 @@ static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97)
gsr_bits = 0; gsr_bits = 0;
#ifdef CONFIG_PXA27x #ifdef CONFIG_PXA27x
/* PXA27x Developers Manual section 13.5.2.2.1 */ /* PXA27x Developers Manual section 13.5.2.2.1 */
pxa_set_cken(31, 1); pxa_set_cken(CKEN_AC97CONF, 1);
udelay(5); udelay(5);
pxa_set_cken(31, 0); pxa_set_cken(CKEN_AC97CONF, 0);
GCR = GCR_COLD_RST; GCR = GCR_COLD_RST;
udelay(50); udelay(50);
#else #else
......
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