Commit a1472e73 authored by Sanjay R Mehta's avatar Sanjay R Mehta Committed by Jon Mason

ntb_hw_amd: Add memory window support for new AMD hardware

The AMD new hardware uses BAR23 and BAR45 as memory windows
as compared to previos where BAR1, BAR23 and BAR45 is used
for memory windows.

This patch add support for both AMD hardwares.
Signed-off-by: default avatarSanjay R Mehta <sanju.mehta@amd.com>
Signed-off-by: default avatarJon Mason <jdmason@kudzu.us>
parent 5f59f6b1
...@@ -78,7 +78,7 @@ static int ndev_mw_to_bar(struct amd_ntb_dev *ndev, int idx) ...@@ -78,7 +78,7 @@ static int ndev_mw_to_bar(struct amd_ntb_dev *ndev, int idx)
if (idx < 0 || idx > ndev->mw_count) if (idx < 0 || idx > ndev->mw_count)
return -EINVAL; return -EINVAL;
return 1 << idx; return ndev->dev_data->mw_idx << idx;
} }
static int amd_ntb_mw_count(struct ntb_dev *ntb, int pidx) static int amd_ntb_mw_count(struct ntb_dev *ntb, int pidx)
...@@ -909,7 +909,7 @@ static int amd_init_ntb(struct amd_ntb_dev *ndev) ...@@ -909,7 +909,7 @@ static int amd_init_ntb(struct amd_ntb_dev *ndev)
{ {
void __iomem *mmio = ndev->self_mmio; void __iomem *mmio = ndev->self_mmio;
ndev->mw_count = AMD_MW_CNT; ndev->mw_count = ndev->dev_data->mw_count;
ndev->spad_count = AMD_SPADS_CNT; ndev->spad_count = AMD_SPADS_CNT;
ndev->db_count = AMD_DB_CNT; ndev->db_count = AMD_DB_CNT;
...@@ -1069,6 +1069,8 @@ static int amd_ntb_pci_probe(struct pci_dev *pdev, ...@@ -1069,6 +1069,8 @@ static int amd_ntb_pci_probe(struct pci_dev *pdev,
goto err_ndev; goto err_ndev;
} }
ndev->dev_data = (struct ntb_dev_data *)id->driver_data;
ndev_init_struct(ndev, pdev); ndev_init_struct(ndev, pdev);
rc = amd_ntb_init_pci(ndev, pdev); rc = amd_ntb_init_pci(ndev, pdev);
...@@ -1123,10 +1125,21 @@ static const struct file_operations amd_ntb_debugfs_info = { ...@@ -1123,10 +1125,21 @@ static const struct file_operations amd_ntb_debugfs_info = {
.read = ndev_debugfs_read, .read = ndev_debugfs_read,
}; };
static const struct ntb_dev_data dev_data[] = {
{ /* for device 145b */
.mw_count = 3,
.mw_idx = 1,
},
{ /* for device 148b */
.mw_count = 2,
.mw_idx = 2,
},
};
static const struct pci_device_id amd_ntb_pci_tbl[] = { static const struct pci_device_id amd_ntb_pci_tbl[] = {
{PCI_VDEVICE(AMD, 0x145b)}, { PCI_VDEVICE(AMD, 0x145b), (kernel_ulong_t)&dev_data[0] },
{PCI_VDEVICE(AMD, 0x148b)}, { PCI_VDEVICE(AMD, 0x148b), (kernel_ulong_t)&dev_data[1] },
{0} { 0, }
}; };
MODULE_DEVICE_TABLE(pci, amd_ntb_pci_tbl); MODULE_DEVICE_TABLE(pci, amd_ntb_pci_tbl);
......
...@@ -92,7 +92,6 @@ static inline void _write64(u64 val, void __iomem *mmio) ...@@ -92,7 +92,6 @@ static inline void _write64(u64 val, void __iomem *mmio)
enum { enum {
/* AMD NTB Capability */ /* AMD NTB Capability */
AMD_MW_CNT = 3,
AMD_DB_CNT = 16, AMD_DB_CNT = 16,
AMD_MSIX_VECTOR_CNT = 24, AMD_MSIX_VECTOR_CNT = 24,
AMD_SPADS_CNT = 16, AMD_SPADS_CNT = 16,
...@@ -169,6 +168,11 @@ enum { ...@@ -169,6 +168,11 @@ enum {
AMD_PEER_OFFSET = 0x400, AMD_PEER_OFFSET = 0x400,
}; };
struct ntb_dev_data {
const unsigned char mw_count;
const unsigned int mw_idx;
};
struct amd_ntb_dev; struct amd_ntb_dev;
struct amd_ntb_vec { struct amd_ntb_vec {
...@@ -184,6 +188,7 @@ struct amd_ntb_dev { ...@@ -184,6 +188,7 @@ struct amd_ntb_dev {
u32 cntl_sta; u32 cntl_sta;
u32 peer_sta; u32 peer_sta;
struct ntb_dev_data *dev_data;
unsigned char mw_count; unsigned char mw_count;
unsigned char spad_count; unsigned char spad_count;
unsigned char db_count; unsigned char db_count;
......
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