drm/nouveau/disp/g94-: port OR DP training pattern control to nvkm_ior

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

@@ -122,7 +122,7 @@ nvkm_dp_train_pattern(struct lt_state *lt, u8 pattern)
 	u8 sink_tp;
 
 	OUTP_TRACE(&dp->outp, "training pattern %d", pattern);
-	dp->func->pattern(dp, pattern);
+	dp->outp.ior->func->dp.pattern(dp->outp.ior, pattern);
 
 	nvkm_rdaux(dp->aux, DPCD_LC02, &sink_tp, 1);
 	sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h

@@ -33,7 +33,6 @@ struct nvkm_dp {
 #define nvkm_output_dp nvkm_dp
 
 struct nvkm_output_dp_func {
-	int (*pattern)(struct nvkm_output_dp *, int);
 	int (*drv_ctl)(struct nvkm_output_dp *, int ln, int vs, int pe, int pc);
 	void (*vcpi)(struct nvkm_output_dp *, int head, u8 start_slot,
 		     u8 num_slots, u16 pbn, u16 aligned_pbn);
@@ -57,7 +56,6 @@ void gf119_sor_dp_vcpi(struct nvkm_dp *, int, u8, u8, u16, u16);
 
 int gm107_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
 		     struct nvkm_output **);
-int gm107_sor_dp_pattern(struct nvkm_dp *, int);
 
 int gm200_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
 		     struct nvkm_output **);

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h

@@ -55,6 +55,7 @@ struct nvkm_ior_func {
 		u8 lanes[4];
 		int (*links)(struct nvkm_ior *, struct nvkm_i2c_aux *);
 		void (*power)(struct nvkm_ior *, int nr);
+		void (*pattern)(struct nvkm_ior *, int pattern);
 	} dp;
 };
 
@@ -84,9 +85,13 @@ void nv50_sor_power(struct nvkm_ior *, bool, bool, bool, bool, bool);
 void g94_sor_state(struct nvkm_ior *, struct nvkm_ior_state *);
 int g94_sor_dp_links(struct nvkm_ior *, struct nvkm_i2c_aux *);
 void g94_sor_dp_power(struct nvkm_ior *, int);
+void g94_sor_dp_pattern(struct nvkm_ior *, int);
 
 void gf119_sor_state(struct nvkm_ior *, struct nvkm_ior_state *);
 int gf119_sor_dp_links(struct nvkm_ior *, struct nvkm_i2c_aux *);
+void gf119_sor_dp_pattern(struct nvkm_ior *, int);
+
+void gm107_sor_dp_pattern(struct nvkm_ior *, int);
 
 void g84_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8);
 void gt215_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8);

drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c

@@ -45,12 +45,6 @@ nv50_pior_output_new(struct nvkm_disp *disp, int index,
 /******************************************************************************
  * DisplayPort
  *****************************************************************************/
-static int
-nv50_pior_output_dp_pattern(struct nvkm_output_dp *outp, int pattern)
-{
-	return 0;
-}
-
 static int
 nv50_pior_dp_links(struct nvkm_ior *pior, struct nvkm_i2c_aux *aux)
 {
@@ -63,7 +57,6 @@ nv50_pior_dp_links(struct nvkm_ior *pior, struct nvkm_i2c_aux *aux)
 
 static const struct nvkm_output_dp_func
 nv50_pior_output_dp_func = {
-	.pattern = nv50_pior_output_dp_pattern,
 };
 
 int

drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c

@@ -81,13 +81,12 @@ g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
 	return 0;
 }
 
-static int
-g94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
+void
+g94_sor_dp_pattern(struct nvkm_ior *sor, int pattern)
 {
-	struct nvkm_device *device = outp->base.disp->engine.subdev.device;
-	const u32 loff = g94_sor_loff(outp);
+	struct nvkm_device *device = sor->disp->engine.subdev.device;
+	const u32 loff = nv50_sor_link(sor);
 	nvkm_mask(device, 0x61c10c + loff, 0x0f000000, pattern << 24);
-	return 0;
 }
 
 void
@@ -131,7 +130,6 @@ g94_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
 
 static const struct nvkm_output_dp_func
 g94_sor_dp_func = {
-	.pattern = g94_sor_dp_pattern,
 	.drv_ctl = g94_sor_dp_drv_ctl,
 };
 
@@ -299,6 +297,7 @@ g94_sor = {
 		.lanes = { 2, 1, 0, 3},
 		.links = g94_sor_dp_links,
 		.power = g94_sor_dp_power,
+		.pattern = g94_sor_dp_pattern,
 	},
 };
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c

@@ -84,13 +84,12 @@ gf119_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
 	return 0;
 }
 
-static int
-gf119_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
+void
+gf119_sor_dp_pattern(struct nvkm_ior *sor, int pattern)
 {
-	struct nvkm_device *device = outp->base.disp->engine.subdev.device;
-	const u32 soff = gf119_sor_soff(outp);
+	struct nvkm_device *device = sor->disp->engine.subdev.device;
+	const u32 soff = nv50_ior_base(sor);
 	nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, 0x01010101 * pattern);
-	return 0;
 }
 
 int
@@ -116,7 +115,6 @@ gf119_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
 
 static const struct nvkm_output_dp_func
 gf119_sor_dp_func = {
-	.pattern = gf119_sor_dp_pattern,
 	.drv_ctl = gf119_sor_dp_drv_ctl,
 	.vcpi = gf119_sor_dp_vcpi,
 };
@@ -162,6 +160,7 @@ gf119_sor = {
 		.lanes = { 2, 1, 0, 3 },
 		.links = gf119_sor_dp_links,
 		.power = g94_sor_dp_power,
+		.pattern = gf119_sor_dp_pattern,
 	},
 };
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgk104.c

@@ -32,6 +32,7 @@ gk104_sor = {
 		.lanes = { 2, 1, 0, 3 },
 		.links = gf119_sor_dp_links,
 		.power = g94_sor_dp_power,
+		.pattern = gf119_sor_dp_pattern,
 	},
 };
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c

@@ -24,22 +24,20 @@
 #include "ior.h"
 #include "nv50.h"
 
-int
-gm107_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
+void
+gm107_sor_dp_pattern(struct nvkm_ior *sor, int pattern)
 {
-	struct nvkm_device *device = outp->base.disp->engine.subdev.device;
-	const u32 soff = outp->base.or * 0x800;
+	struct nvkm_device *device = sor->disp->engine.subdev.device;
+	const u32 soff = nv50_ior_base(sor);
 	const u32 data = 0x01010101 * pattern;
-	if (outp->base.info.sorconf.link & 1)
+	if (sor->asy.link & 1)
 		nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, data);
 	else
 		nvkm_mask(device, 0x61c12c + soff, 0x0f0f0f0f, data);
-	return 0;
 }
 
 static const struct nvkm_output_dp_func
 gm107_sor_dp_func = {
-	.pattern = gm107_sor_dp_pattern,
 	.drv_ctl = gf119_sor_dp_drv_ctl,
 	.vcpi = gf119_sor_dp_vcpi,
 };
@@ -62,6 +60,7 @@ gm107_sor = {
 		.lanes = { 0, 1, 2, 3 },
 		.links = gf119_sor_dp_links,
 		.power = g94_sor_dp_power,
+		.pattern = gm107_sor_dp_pattern,
 	},
 };
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c

@@ -82,7 +82,6 @@ gm200_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
 
 static const struct nvkm_output_dp_func
 gm200_sor_dp_func = {
-	.pattern = gm107_sor_dp_pattern,
 	.drv_ctl = gm200_sor_dp_drv_ctl,
 	.vcpi = gf119_sor_dp_vcpi,
 };
@@ -117,6 +116,7 @@ gm200_sor = {
 		.lanes = { 0, 1, 2, 3 },
 		.links = gf119_sor_dp_links,
 		.power = g94_sor_dp_power,
+		.pattern = gm107_sor_dp_pattern,
 	},
 };
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c

@@ -32,6 +32,7 @@ gt215_sor = {
 		.lanes = { 2, 1, 0, 3 },
 		.links = g94_sor_dp_links,
 		.power = g94_sor_dp_power,
+		.pattern = g94_sor_dp_pattern,
 	},
 };
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp77.c

@@ -32,6 +32,7 @@ mcp77_sor = {
 		.lanes = { 2, 1, 0, 3},
 		.links = g94_sor_dp_links,
 		.power = g94_sor_dp_power,
+		.pattern = g94_sor_dp_pattern,
 	},
 };
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp89.c

@@ -32,6 +32,7 @@ mcp89_sor = {
 		.lanes = { 3, 2, 1, 0 },
 		.links = g94_sor_dp_links,
 		.power = g94_sor_dp_power,
+		.pattern = g94_sor_dp_pattern,
 	},
 };