Commit a2b5e056 authored by Nicholas Piggin's avatar Nicholas Piggin Committed by Michael Ellerman

powerpc/powernv: Fix SMT4 forcing idle code

The PSSCR value is not stored to PACA_REQ_PSSCR if the CPU does not
have the XER[SO] bug.

Fix this by storing up-front, outside the workaround code. The initial
test is not required because it is a slow path.

The workaround is made to depend on CONFIG_KVM_BOOK3S_HV_POSSIBLE, to
match pnv_power9_force_smt4_catch() where it is used. Drop the comment
on pnv_power9_force_smt4_catch() as it's no longer true.

Fixes: 7672691a ("powerpc/powernv: Provide a way to force a core into SMT4 mode")
Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent b6f534d1
...@@ -442,20 +442,20 @@ _GLOBAL(power9_offline_stop) ...@@ -442,20 +442,20 @@ _GLOBAL(power9_offline_stop)
* r3 contains desired PSSCR register value. * r3 contains desired PSSCR register value.
*/ */
_GLOBAL(power9_idle_stop) _GLOBAL(power9_idle_stop)
BEGIN_FTR_SECTION
lwz r5, PACA_DONT_STOP(r13)
cmpwi r5, 0
bne 1f
std r3, PACA_REQ_PSSCR(r13) std r3, PACA_REQ_PSSCR(r13)
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
BEGIN_FTR_SECTION
sync sync
lwz r5, PACA_DONT_STOP(r13) lwz r5, PACA_DONT_STOP(r13)
cmpwi r5, 0 cmpwi r5, 0
bne 1f bne 1f
END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG) END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
#endif
mtspr SPRN_PSSCR,r3 mtspr SPRN_PSSCR,r3
LOAD_REG_ADDR(r4,power_enter_stop) LOAD_REG_ADDR(r4,power_enter_stop)
b pnv_powersave_common b pnv_powersave_common
/* No return */ /* No return */
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
1: 1:
/* /*
* We get here when TM / thread reconfiguration bug workaround * We get here when TM / thread reconfiguration bug workaround
...@@ -465,6 +465,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG) ...@@ -465,6 +465,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
li r3, 0 li r3, 0
std r3, PACA_REQ_PSSCR(r13) std r3, PACA_REQ_PSSCR(r13)
blr /* return 0 for wakeup cause / SRR1 value */ blr /* return 0 for wakeup cause / SRR1 value */
#endif
/* /*
* On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1, * On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1,
......
...@@ -397,10 +397,6 @@ void power9_idle(void) ...@@ -397,10 +397,6 @@ void power9_idle(void)
* all other threads not to stop, and sending a message to any * all other threads not to stop, and sending a message to any
* that are in a stop state. * that are in a stop state.
* Must be called with preemption disabled. * Must be called with preemption disabled.
*
* DO NOT call this unless cpu_has_feature(CPU_FTR_P9_TM_XER_SO_BUG) is
* true; otherwise this function will hang the system, due to the
* optimization in power9_idle_stop.
*/ */
void pnv_power9_force_smt4_catch(void) void pnv_power9_force_smt4_catch(void)
{ {
......
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