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Commit a355c17b authored by Andrew Morton's avatar Andrew Morton Committed by Linus Torvalds
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[PATCH] PPC32: PPC40x ports for new OCP 

From: Matt Porter <mporter@kernel.crashing.org>

Merge all current PPC40x ports against new OCP.
parent d63538d4
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Showing with 480 additions and 133 deletions
arch/ppc/platforms/4xx/ash.h
View file @ a355c17b
...@@ -15,7 +15,6 @@ ...@@ -15,7 +15,6 @@
#ifdef __KERNEL__ #ifdef __KERNEL__
#ifndef __ASM_ASH_H__ #ifndef __ASM_ASH_H__
#define __ASM_ASH_H__ #define __ASM_ASH_H__
#include <asm/ibm_ocp.h>
#include <platforms/4xx/ibmnp405h.h> #include <platforms/4xx/ibmnp405h.h>
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
......
arch/ppc/platforms/4xx/cpci405.c
View file @ a355c17b
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
#include <asm/pci-bridge.h> #include <asm/pci-bridge.h>
#include <asm/machdep.h> #include <asm/machdep.h>
#include <asm/todc.h> #include <asm/todc.h>
#include <asm/ocp.h>
void *cpci405_nvram; void *cpci405_nvram;
...@@ -53,6 +54,9 @@ void __init ...@@ -53,6 +54,9 @@ void __init
cpci405_setup_arch(void) cpci405_setup_arch(void)
{ {
ppc4xx_setup_arch(); ppc4xx_setup_arch();
ibm_ocp_set_emac(0, 0);
TODC_INIT(TODC_TYPE_MK48T35, cpci405_nvram, cpci405_nvram, cpci405_nvram, 8); TODC_INIT(TODC_TYPE_MK48T35, cpci405_nvram, cpci405_nvram, cpci405_nvram, 8);
} }
......
arch/ppc/platforms/4xx/ep405.c
View file @ a355c17b
...@@ -18,6 +18,7 @@ ...@@ -18,6 +18,7 @@
#include <asm/pci-bridge.h> #include <asm/pci-bridge.h>
#include <asm/machdep.h> #include <asm/machdep.h>
#include <asm/todc.h> #include <asm/todc.h>
#include <asm/ocp.h>
#include <asm/ibm_ocp_pci.h> #include <asm/ibm_ocp_pci.h>
#undef DEBUG #undef DEBUG
...@@ -59,6 +60,8 @@ ep405_setup_arch(void) ...@@ -59,6 +60,8 @@ ep405_setup_arch(void)
{ {
ppc4xx_setup_arch(); ppc4xx_setup_arch();
ibm_ocp_set_emac(0, 0);
if (__res.bi_nvramsize == 512*1024) { if (__res.bi_nvramsize == 512*1024) {
/* FIXME: we should properly handle NVRTCs of different sizes */ /* FIXME: we should properly handle NVRTCs of different sizes */
TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8); TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8);
......
arch/ppc/platforms/4xx/ibm405gp.c
View file @ a355c17b
/* /*
* arch/ppc/platforms/4xx/ibm405gp.c
* *
* Author: Armin Kuster <akuster@mvista.com> * Copyright 2000-2001 MontaVista Software Inc.
* Original author: Armin Kuster akuster@mvista.com
*
* Module name: ibm405gp.c
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
* *
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/ */
#include <linux/config.h> #include <linux/config.h>
#include <linux/init.h> #include <linux/init.h>
#include <asm/ocp.h> #include <linux/smp.h>
#include <linux/threads.h>
#include <linux/param.h>
#include <linux/string.h>
#include <platforms/4xx/ibm405gp.h> #include <platforms/4xx/ibm405gp.h>
#include <asm/ibm4xx.h>
#include <asm/ocp.h>
struct ocp_def core_ocp[] __initdata = { static struct ocp_func_emac_data ibm405gp_emac0_def = {
{OCP_VENDOR_IBM, OCP_FUNC_OPB, OPB_BASE_START, OCP_IRQ_NA, OCP_CPM_NA}, .rgmii_idx = -1, /* No RGMII */
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART0_IO_BASE, UART0_INT,IBM_CPM_UART0}, .rgmii_mux = -1, /* No RGMII */
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1}, .zmii_idx = -1, /* ZMII device index */
{OCP_VENDOR_IBM, OCP_FUNC_IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0}, .zmii_mux = 0, /* ZMII input of this EMAC */
{OCP_VENDOR_IBM, OCP_FUNC_GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0}, .mal_idx = 0, /* MAL device index */
{OCP_VENDOR_IBM, OCP_FUNC_EMAC, EMAC0_BASE, BL_MAC_ETH0, IBM_CPM_EMAC0}, .mal_rx_chan = 0, /* MAL rx channel number */
{OCP_VENDOR_INVALID, OCP_FUNC_INVALID, 0x0, OCP_IRQ_NA, OCP_CPM_NA}, .mal_tx_chan = 0, /* MAL tx channel number */
.wol_irq = 9, /* WOL interrupt number */
.mdio_idx = -1, /* No shared MDIO */
.tah_idx = -1, /* No TAH */
};
OCP_SYSFS_EMAC_DATA()
static struct ocp_func_mal_data ibm405gp_mal0_def = {
.num_tx_chans = 1, /* Number of TX channels */
.num_rx_chans = 1, /* Number of RX channels */
.txeob_irq = 11, /* TX End Of Buffer IRQ */
.rxeob_irq = 12, /* RX End Of Buffer IRQ */
.txde_irq = 13, /* TX Descriptor Error IRQ */
.rxde_irq = 14, /* RX Descriptor Error IRQ */
.serr_irq = 10, /* MAL System Error IRQ */
};
OCP_SYSFS_MAL_DATA()
static struct ocp_func_iic_data ibm405gp_iic0_def = {
.fast_mode = 0, /* Use standad mode (100Khz) */
};
OCP_SYSFS_IIC_DATA()
struct ocp_def core_ocp[] = {
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_OPB,
.index = 0,
.paddr = 0xEF600000,
.irq = OCP_IRQ_NA,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_16550,
.index = 0,
.paddr = UART0_IO_BASE,
.irq = UART0_INT,
.pm = IBM_CPM_UART0
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_16550,
.index = 1,
.paddr = UART1_IO_BASE,
.irq = UART1_INT,
.pm = IBM_CPM_UART1
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_IIC,
.paddr = 0xEF600500,
.irq = 2,
.pm = IBM_CPM_IIC0,
.additions = &ibm405gp_iic0_def,
.show = &ocp_show_iic_data,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_GPIO,
.paddr = 0xEF600700,
.irq = OCP_IRQ_NA,
.pm = IBM_CPM_GPIO0
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_MAL,
.paddr = OCP_PADDR_NA,
.irq = OCP_IRQ_NA,
.pm = OCP_CPM_NA,
.additions = &ibm405gp_mal0_def,
.show = &ocp_show_mal_data,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_EMAC,
.index = 0,
.paddr = EMAC0_BASE,
.irq = 15,
.pm = IBM_CPM_EMAC0,
.additions = &ibm405gp_emac0_def,
.show = &ocp_show_emac_data,
},
{ .vendor = OCP_VENDOR_INVALID
}
}; };
arch/ppc/platforms/4xx/ibm405gp.h
View file @ a355c17b
...@@ -51,9 +51,6 @@ ...@@ -51,9 +51,6 @@
#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR #define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
#define PPC4xx_ONB_IO_SIZE ((uint)4*1024) #define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
#define OPB_BASE_START 0x40000000
#define EBIU_BASE_START 0xF0100000
/* serial port defines */ /* serial port defines */
#define RS_TABLE_SIZE 2 #define RS_TABLE_SIZE 2
...@@ -63,24 +60,8 @@ ...@@ -63,24 +60,8 @@
#define PCIL0_BASE 0xEF400000 #define PCIL0_BASE 0xEF400000
#define UART0_IO_BASE 0xEF600300 #define UART0_IO_BASE 0xEF600300
#define UART1_IO_BASE 0xEF600400 #define UART1_IO_BASE 0xEF600400
#define IIC0_BASE 0xEF600500
#define OPB0_BASE 0xEF600600
#define GPIO0_BASE 0xEF600700
#define EMAC0_BASE 0xEF600800 #define EMAC0_BASE 0xEF600800
#define BL_MAC_WOL 9 /* WOL */
#define BL_MAL_SERR 10 /* MAL SERR */
#define BL_MAL_TXDE 13 /* MAL TXDE */
#define BL_MAL_RXDE 14 /* MAL RXDE */
#define BL_MAL_TXEOB 11 /* MAL TX EOB */
#define BL_MAL_RXEOB 12 /* MAL RX EOB */
#define BL_MAC_ETH0 15 /* MAC */
#define EMAC_NUMS 1
#define IIC0_IRQ 2
#define IIC1_IRQ 0
#define IIC_OWN 0x55
#define IIC_CLOCK 50
#define BD_EMAC_ADDR(e,i) bi_enetaddr[i] #define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
#define STD_UART_OP(num) \ #define STD_UART_OP(num) \
......
arch/ppc/platforms/4xx/ibm405gpr.c
View file @ a355c17b
...@@ -11,17 +11,98 @@ ...@@ -11,17 +11,98 @@
#include <linux/config.h> #include <linux/config.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/smp.h>
#include <linux/threads.h>
#include <linux/param.h>
#include <linux/string.h>
#include <platforms/4xx/ibm405gpr.h>
#include <asm/ibm4xx.h>
#include <asm/ocp.h> #include <asm/ocp.h>
#include "ibm405gpr.h" static struct ocp_func_emac_data ibm405gpr_emac0_def = {
.rgmii_idx = -1, /* No RGMII */
.rgmii_mux = -1, /* No RGMII */
.zmii_idx = -1, /* ZMII device index */
.zmii_mux = 0, /* ZMII input of this EMAC */
.mal_idx = 0, /* MAL device index */
.mal_rx_chan = 0, /* MAL rx channel number */
.mal_tx_chan = 0, /* MAL tx channel number */
.wol_irq = 9, /* WOL interrupt number */
.mdio_idx = -1, /* No shared MDIO */
.tah_idx = -1, /* No TAH */
};
OCP_SYSFS_EMAC_DATA()
static struct ocp_func_mal_data ibm405gpr_mal0_def = {
.num_tx_chans = 1, /* Number of TX channels */
.num_rx_chans = 1, /* Number of RX channels */
.txeob_irq = 11, /* TX End Of Buffer IRQ */
.rxeob_irq = 12, /* RX End Of Buffer IRQ */
.txde_irq = 13, /* TX Descriptor Error IRQ */
.rxde_irq = 14, /* RX Descriptor Error IRQ */
.serr_irq = 10, /* MAL System Error IRQ */
};
OCP_SYSFS_MAL_DATA()
static struct ocp_func_iic_data ibm405gpr_iic0_def = {
.fast_mode = 0, /* Use standad mode (100Khz) */
};
struct ocp_def core_ocp[] __initdata = { OCP_SYSFS_IIC_DATA()
{OCP_VENDOR_IBM, OCP_FUNC_OPB, OPB_BASE_START, OCP_IRQ_NA, OCP_CPM_NA},
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART0_IO_BASE, UART0_INT,IBM_CPM_UART0},
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1},
{OCP_VENDOR_IBM, OCP_FUNC_IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
{OCP_VENDOR_IBM, OCP_FUNC_GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
{OCP_VENDOR_IBM, OCP_FUNC_EMAC, EMAC0_BASE, BL_MAC_ETH0, IBM_CPM_EMAC0},
{OCP_VENDOR_INVALID, OCP_FUNC_INVALID, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
struct ocp_def core_ocp[] = {
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_OPB,
.index = 0,
.paddr = 0xEF600000,
.irq = OCP_IRQ_NA,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_16550,
.index = 0,
.paddr = UART0_IO_BASE,
.irq = UART0_INT,
.pm = IBM_CPM_UART0
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_16550,
.index = 1,
.paddr = UART1_IO_BASE,
.irq = UART1_INT,
.pm = IBM_CPM_UART1
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_IIC,
.paddr = 0xEF600500,
.irq = 2,
.pm = IBM_CPM_IIC0,
.additions = &ibm405gpr_iic0_def,
.show = &ocp_show_iic_data,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_GPIO,
.paddr = 0xEF600700,
.irq = OCP_IRQ_NA,
.pm = IBM_CPM_GPIO0
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_MAL,
.paddr = OCP_PADDR_NA,
.irq = OCP_IRQ_NA,
.pm = OCP_CPM_NA,
.additions = &ibm405gpr_mal0_def,
.show = &ocp_show_mal_data,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_EMAC,
.index = 0,
.paddr = EMAC0_BASE,
.irq = 15,
.pm = IBM_CPM_EMAC0,
.additions = &ibm405gpr_emac0_def,
.show = &ocp_show_emac_data,
},
{ .vendor = OCP_VENDOR_INVALID
}
}; };
arch/ppc/platforms/4xx/ibm405gpr.h
View file @ a355c17b
...@@ -51,9 +51,6 @@ ...@@ -51,9 +51,6 @@
#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR #define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
#define PPC4xx_ONB_IO_SIZE ((uint)4*1024) #define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
#define OPB_BASE_START 0x40000000
#define EBIU_BASE_START 0xF0100000
/* serial port defines */ /* serial port defines */
#define RS_TABLE_SIZE 2 #define RS_TABLE_SIZE 2
...@@ -63,20 +60,8 @@ ...@@ -63,20 +60,8 @@
#define PCIL0_BASE 0xEF400000 #define PCIL0_BASE 0xEF400000
#define UART0_IO_BASE 0xEF600300 #define UART0_IO_BASE 0xEF600300
#define UART1_IO_BASE 0xEF600400 #define UART1_IO_BASE 0xEF600400
#define IIC0_BASE 0xEF600500
#define OPB0_BASE 0xEF600600
#define GPIO0_BASE 0xEF600700
#define EMAC0_BASE 0xEF600800 #define EMAC0_BASE 0xEF600800
#define BL_MAC_WOL 9 /* WOL */
#define BL_MAL_SERR 10 /* MAL SERR */
#define BL_MAL_TXDE 13 /* MAL TXDE */
#define BL_MAL_RXDE 14 /* MAL RXDE */
#define BL_MAL_TXEOB 11 /* MAL TX EOB */
#define BL_MAL_RXEOB 12 /* MAL RX EOB */
#define BL_MAC_ETH0 15 /* MAC */
#define IIC_OWN 0x55
#define IIC_CLOCK 50
#define BD_EMAC_ADDR(e,i) bi_enetaddr[i] #define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
#define STD_UART_OP(num) \ #define STD_UART_OP(num) \
......
arch/ppc/platforms/4xx/ibmnp405h.c
View file @ a355c17b
...@@ -14,21 +14,159 @@ ...@@ -14,21 +14,159 @@
#include <asm/ocp.h> #include <asm/ocp.h>
#include <platforms/4xx/ibmnp405h.h> #include <platforms/4xx/ibmnp405h.h>
static struct ocp_func_emac_data ibmnp405h_emac0_def = {
.rgmii_idx = -1, /* No RGMII */
.rgmii_mux = -1, /* No RGMII */
.zmii_idx = 0, /* ZMII device index */
.zmii_mux = 0, /* ZMII input of this EMAC */
.mal_idx = 0, /* MAL device index */
.mal_rx_chan = 0, /* MAL rx channel number */
.mal_tx_chan = 0, /* MAL tx channel number */
.wol_irq = 41, /* WOL interrupt number */
.mdio_idx = -1, /* No shared MDIO */
.tah_idx = -1, /* No TAH */
};
static struct ocp_func_emac_data ibmnp405h_emac1_def = {
.rgmii_idx = -1, /* No RGMII */
.rgmii_mux = -1, /* No RGMII */
.zmii_idx = 0, /* ZMII device index */
.zmii_mux = 1, /* ZMII input of this EMAC */
.mal_idx = 0, /* MAL device index */
.mal_rx_chan = 1, /* MAL rx channel number */
.mal_tx_chan = 1, /* MAL tx channel number */
.wol_irq = 41, /* WOL interrupt number */
.mdio_idx = -1, /* No shared MDIO */
.tah_idx = -1, /* No TAH */
};
static struct ocp_func_emac_data ibmnp405h_emac2_def = {
.rgmii_idx = -1, /* No RGMII */
.rgmii_mux = -1, /* No RGMII */
.zmii_idx = 0, /* ZMII device index */
.zmii_mux = 2, /* ZMII input of this EMAC */
.mal_idx = 0, /* MAL device index */
.mal_rx_chan = 2, /* MAL rx channel number */
.mal_tx_chan = 2, /* MAL tx channel number */
.wol_irq = 41, /* WOL interrupt number */
.mdio_idx = -1, /* No shared MDIO */
.tah_idx = -1, /* No TAH */
};
static struct ocp_func_emac_data ibmnp405h_emac3_def = {
.rgmii_idx = -1, /* No RGMII */
.rgmii_mux = -1, /* No RGMII */
.zmii_idx = 0, /* ZMII device index */
.zmii_mux = 3, /* ZMII input of this EMAC */
.mal_idx = 0, /* MAL device index */
.mal_rx_chan = 3, /* MAL rx channel number */
.mal_tx_chan = 3, /* MAL tx channel number */
.wol_irq = 41, /* WOL interrupt number */
.mdio_idx = -1, /* No shared MDIO */
.tah_idx = -1, /* No TAH */
};
OCP_SYSFS_EMAC_DATA()
static struct ocp_func_mal_data ibmnp405h_mal0_def = {
.num_tx_chans = 8, /* Number of TX channels */
.num_rx_chans = 4, /* Number of RX channels */
.txeob_irq = 17, /* TX End Of Buffer IRQ */
.rxeob_irq = 18, /* RX End Of Buffer IRQ */
.txde_irq = 46, /* TX Descriptor Error IRQ */
.rxde_irq = 47, /* RX Descriptor Error IRQ */
.serr_irq = 45, /* MAL System Error IRQ */
};
OCP_SYSFS_MAL_DATA()
static struct ocp_func_iic_data ibmnp405h_iic0_def = {
.fast_mode = 0, /* Use standad mode (100Khz) */
};
OCP_SYSFS_IIC_DATA()
struct ocp_def core_ocp[] = { struct ocp_def core_ocp[] = {
// {OCP_VENDOR_IBM, OCP_FUNC_PLB, 0x0, OCP_IRQ_NA, OCP_CPM_NA}, { .vendor = OCP_VENDOR_IBM,
{OCP_VENDOR_IBM, OCP_FUNC_OPB, OPB_BASE_START, OCP_IRQ_NA, OCP_CPM_NA}, .function = OCP_FUNC_OPB,
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART0_IO_BASE, UART0_INT,IBM_CPM_UART0}, .index = 0,
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1}, .paddr = 0xEF600000,
{OCP_VENDOR_IBM, OCP_FUNC_IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0}, .irq = OCP_IRQ_NA,
{OCP_VENDOR_IBM, OCP_FUNC_GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0}, .pm = OCP_CPM_NA,
{OCP_VENDOR_IBM, OCP_FUNC_EMAC, EMAC0_BASE, BL_MAC_ETH0, IBM_CPM_EMAC0}, },
{OCP_VENDOR_IBM, OCP_FUNC_EMAC, EMAC0_BASE, BL_MAC_ETH0, IBM_CPM_EMAC0}, { .vendor = OCP_VENDOR_IBM,
{OCP_VENDOR_IBM, OCP_FUNC_EMAC, EMAC1_BASE, BL_MAC_ETH1, IBM_CPM_EMAC1}, .function = OCP_FUNC_16550,
{OCP_VENDOR_IBM, OCP_FUNC_EMAC, EMAC2_BASE, BL_MAC_ETH2, IBM_CPM_EMAC2}, .index = 0,
{OCP_VENDOR_IBM, OCP_FUNC_EMAC, EMAC3_BASE, BL_MAC_ETH3, IBM_CPM_EMAC3}, .paddr = UART0_IO_BASE,
{OCP_VENDOR_IBM, OCP_FUNC_PHY, ZMII0_BASE, OCP_IRQ_NA, OCP_CPM_NA}, .irq = UART0_INT,
// {OCP_VENDOR_IBM, OCP_FUNC_EXT, EBIU_BASE_START, OCP_IRQ_NA,IBM_CPM_EBC}, .pm = IBM_CPM_UART0
// {OCP_VENDOR_IBM, OCP_FUNC_PCI, PCIL0_BASE, OCP_IRQ_NA, IBM_CPM_PCI}, },
{OCP_VENDOR_INVALID, OCP_FUNC_INVALID, 0x0, OCP_IRQ_NA, OCP_CPM_NA}, { .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_16550,
.index = 1,
.paddr = UART1_IO_BASE,
.irq = UART1_INT,
.pm = IBM_CPM_UART1
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_IIC,
.paddr = 0xEF600500,
.irq = 2,
.pm = IBM_CPM_IIC0,
.additions = &ibmnp405h_iic0_def,
.show = &ocp_show_iic_data
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_GPIO,
.paddr = 0xEF600700,
.irq = OCP_IRQ_NA,
.pm = IBM_CPM_GPIO0
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_MAL,
.paddr = OCP_PADDR_NA,
.irq = OCP_IRQ_NA,
.pm = OCP_CPM_NA,
.additions = &ibmnp405h_mal0_def,
.show = &ocp_show_mal_data,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_EMAC,
.index = 0,
.paddr = EMAC0_BASE,
.irq = 37,
.pm = IBM_CPM_EMAC0,
.additions = &ibmnp405h_emac0_def,
.show = &ocp_show_emac_data,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_EMAC,
.index = 1,
.paddr = 0xEF600900,
.irq = 38,
.pm = IBM_CPM_EMAC1,
.additions = &ibmnp405h_emac1_def,
.show = &ocp_show_emac_data,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_EMAC,
.index = 2,
.paddr = 0xEF600a00,
.irq = 39,
.pm = IBM_CPM_EMAC2,
.additions = &ibmnp405h_emac2_def,
.show = &ocp_show_emac_data,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_EMAC,
.index = 3,
.paddr = 0xEF600b00,
.irq = 40,
.pm = IBM_CPM_EMAC3,
.additions = &ibmnp405h_emac3_def,
.show = &ocp_show_emac_data,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_ZMII,
.paddr = 0xEF600C10,
.irq = OCP_IRQ_NA,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_INVALID
}
}; };
arch/ppc/platforms/4xx/ibmnp405h.h
View file @ a355c17b
...@@ -14,7 +14,6 @@ ...@@ -14,7 +14,6 @@
#define __ASM_IBMNP405H_H__ #define __ASM_IBMNP405H_H__
#include <linux/config.h> #include <linux/config.h>
#include <asm/ibm_ocp.h>
/* ibm405.h at bottom of this file */ /* ibm405.h at bottom of this file */
...@@ -42,9 +41,6 @@ ...@@ -42,9 +41,6 @@
#define PPC4xx_ONB_IO_ADDR ((uint)0xef600000) #define PPC4xx_ONB_IO_ADDR ((uint)0xef600000)
#define PPC4xx_ONB_IO_SIZE ((uint)4*1024) #define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
#define OPB_BASE_START 0x40000000
#define EBIU_BASE_START 0xF0100000
/* serial port defines */ /* serial port defines */
#define RS_TABLE_SIZE 4 #define RS_TABLE_SIZE 4
...@@ -53,27 +49,8 @@ ...@@ -53,27 +49,8 @@
#define PCIL0_BASE 0xEF400000 #define PCIL0_BASE 0xEF400000
#define UART0_IO_BASE 0xEF600300 #define UART0_IO_BASE 0xEF600300
#define UART1_IO_BASE 0xEF600400 #define UART1_IO_BASE 0xEF600400
#define IIC0_BASE 0xEF600500
#define OPB0_BASE 0xEF600600 #define OPB0_BASE 0xEF600600
#define GPIO0_BASE 0xEF600700
#define EMAC0_BASE 0xEF600800 #define EMAC0_BASE 0xEF600800
#define EMAC1_BASE 0xEF600900
#define EMAC2_BASE 0xEF600a00
#define EMAC3_BASE 0xEF600b00
#define ZMII0_BASE 0xEF600C10
#define BL_MAC_WOL 41 /* WOL */
#define BL_MAL_SERR 45 /* MAL SERR */
#define BL_MAL_TXDE 46 /* MAL TXDE */
#define BL_MAL_RXDE 47 /* MAL RXDE */
#define BL_MAL_TXEOB 17 /* MAL TX EOB */
#define BL_MAL_RXEOB 18 /* MAL RX EOB */
#define BL_MAC_ETH0 37 /* MAC */
#define BL_MAC_ETH1 38 /* MAC */
#define BL_MAC_ETH2 39 /* MAC */
#define BL_MAC_ETH3 40 /* MAC */
#define EMAC_NUMS 4
#define IIC0_IRQ 2
#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i] #define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
......
arch/ppc/platforms/4xx/ibmstb4.c
View file @ a355c17b
...@@ -9,19 +9,75 @@ ...@@ -9,19 +9,75 @@
* or implied. * or implied.
*/ */
#include <linux/config.h> #include <linux/init.h>
#include <linux/module.h>
#include "ibmstb4.h"
#include <asm/ocp.h> #include <asm/ocp.h>
#include <platforms/4xx/ibmstb4.h>
struct ocp_def core_ocp[] = { static struct ocp_func_iic_data ibmstb4_iic0_def = {
{UART, UART0_IO_BASE, UART0_INT,IBM_CPM_UART0}, .fast_mode = 0, /* Use standad mode (100Khz) */
{UART, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1}, };
{UART, UART2_IO_BASE, UART2_INT, IBM_CPM_UART2},
{IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0}, static struct ocp_func_iic_data ibmstb4_iic1_def = {
{IIC, IIC1_BASE, IIC1_IRQ, IBM_CPM_IIC1}, .fast_mode = 0, /* Use standad mode (100Khz) */
{GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0}, };
{IDE, IDE0_BASE, IDE0_IRQ, OCP_CPM_NA}, OCP_SYSFS_IIC_DATA()
{USB, USB0_BASE, USB0_IRQ, IBM_CPM_USB0},
{OCP_NULL_TYPE, 0x0, OCP_IRQ_NA, OCP_CPM_NA}, struct ocp_def core_ocp[] __initdata = {
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_16550,
.index = 0,
.paddr = UART0_IO_BASE,
.irq = UART0_INT,
.pm = IBM_CPM_UART0,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_16550,
.index = 1,
.paddr = UART1_IO_BASE,
.irq = UART1_INT,
.pm = IBM_CPM_UART1,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_16550,
.index = 2,
.paddr = UART2_IO_BASE,
.irq = UART2_INT,
.pm = IBM_CPM_UART2,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_IIC,
.paddr = IIC0_BASE,
.irq = IIC0_IRQ,
.pm = IBM_CPM_IIC0,
.additions = &ibmstb4_iic0_def,
.show = &ocp_show_iic_data
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_IIC,
.paddr = IIC1_BASE,
.irq = IIC1_IRQ,
.pm = IBM_CPM_IIC1,
.additions = &ibmstb4_iic1_def,
.show = &ocp_show_iic_data
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_GPIO,
.paddr = GPIO0_BASE,
.irq = OCP_IRQ_NA,
.pm = IBM_CPM_GPIO0,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_IDE,
.paddr = IDE0_BASE,
.irq = IDE0_IRQ,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_USB,
.paddr = USB0_BASE,
.irq = USB0_IRQ,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_INVALID,
}
}; };
arch/ppc/platforms/4xx/ibmstb4.h
View file @ a355c17b
...@@ -14,7 +14,6 @@ ...@@ -14,7 +14,6 @@
#define __ASM_IBMSTB4_H__ #define __ASM_IBMSTB4_H__
#include <linux/config.h> #include <linux/config.h>
#include <platforms/4xx/ibm_ocp.h>
/* serial port defines */ /* serial port defines */
#define STB04xxx_IO_BASE ((uint)0xe0000000) #define STB04xxx_IO_BASE ((uint)0xe0000000)
......
arch/ppc/platforms/4xx/ibmstbx25.c
View file @ a355c17b
...@@ -9,22 +9,51 @@ ...@@ -9,22 +9,51 @@
* or implied. * or implied.
*/ */
#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h> #include <linux/init.h>
#include <asm/ocp.h> #include <asm/ocp.h>
#include "ibmstbx25.h" #include <platforms/4xx/ibmstbx25.h>
struct ocp_def core_ocp[] __initdata = { static struct ocp_func_iic_data ibmstbx25_iic0_def = {
{OCP_VENDOR_IBM, OCP_FUNC_PLB, 0x0, OCP_IRQ_NA, OCP_CPM_NA}, .fast_mode = 0, /* Use standad mode (100Khz) */
{OCP_VENDOR_IBM, OCP_FUNC_OPB, OPB_BASE_START, OCP_IRQ_NA, OCP_CPM_NA}, };
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART0_IO_BASE, UART0_INT,IBM_CPM_UART0}, OCP_SYSFS_IIC_DATA()
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1},
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART2_IO_BASE,UART2_INT, IBM_CPM_UART2},
{OCP_VENDOR_IBM, OCP_FUNC_IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
{OCP_VENDOR_IBM, OCP_FUNC_GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
{OCP_VENDOR_IBM, OCP_FUNC_IDE, IDE0_BASE, IDE0_IRQ, OCP_CPM_NA},
{OCP_VENDOR_IBM, OCP_FUNC_EXT, EBIU_BASE_START, OCP_IRQ_NA,IBM_CPM_EBIU},
{OCP_VENDOR_INVALID, OCP_FUNC_INVALID, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
struct ocp_def core_ocp[] __initdata = {
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_16550,
.index = 0,
.paddr = UART0_IO_BASE,
.irq = UART0_INT,
.pm = IBM_CPM_UART0,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_16550,
.index = 1,
.paddr = UART1_IO_BASE,
.irq = UART1_INT,
.pm = IBM_CPM_UART1,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_16550,
.index = 2,
.paddr = UART2_IO_BASE,
.irq = UART2_INT,
.pm = IBM_CPM_UART2,
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_IIC,
.paddr = IIC0_BASE,
.irq = IIC0_IRQ,
.pm = IBM_CPM_IIC0,
.additions = &ibmstbx25_iic0_def,
.show = &ocp_show_iic_data
},
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_GPIO,
.paddr = GPIO0_BASE,
.irq = OCP_IRQ_NA,
.pm = IBM_CPM_GPIO0,
},
{ .vendor = OCP_VENDOR_INVALID
}
}; };
arch/ppc/platforms/4xx/redwood5.c
View file @ a355c17b
...@@ -20,8 +20,6 @@ ...@@ -20,8 +20,6 @@
void __init void __init
redwood5_setup_arch(void) redwood5_setup_arch(void)
{ {
bd_t *bip = &__res;
ppc4xx_setup_arch(); ppc4xx_setup_arch();
#ifdef CONFIG_DEBUG_BRINGUP #ifdef CONFIG_DEBUG_BRINGUP
......
arch/ppc/platforms/4xx/sycamore.c
View file @ a355c17b
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
#include <asm/page.h> #include <asm/page.h>
#include <asm/time.h> #include <asm/time.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/ibm_ocp_pci.h>
#include <asm/todc.h> #include <asm/todc.h>
#undef DEBUG #undef DEBUG
...@@ -119,6 +120,8 @@ sycamore_setup_arch(void) ...@@ -119,6 +120,8 @@ sycamore_setup_arch(void)
ppc4xx_setup_arch(); ppc4xx_setup_arch();
ibm_ocp_set_emac(0, 1);
kb_data = ioremap(SYCAMORE_PS2_BASE, 8); kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
if (!kb_data) { if (!kb_data) {
printk(KERN_CRIT printk(KERN_CRIT
...@@ -218,21 +221,25 @@ bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip) ...@@ -218,21 +221,25 @@ bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
(PPC405_PCI_UPPER_MEM - (PPC405_PCI_UPPER_MEM -
PPC405_PCI_MEM_BASE)) | 0x01)); PPC405_PCI_MEM_BASE)) | 0x01));
/* Disable region one */ /* Enable inbound region one - 1GB size */
out_le32((void *) &(pcip->ptm1ms), 0xc0000001);
/* Disable outbound region one */
out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
out_le32((void *) &(pcip->pmm[1].la), 0x00000000); out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000); out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000); out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
out_le32((void *) &(pcip->ptm1ms), 0x00000000);
/* Disable region two */ /* Disable inbound region two */
out_le32((void *) &(pcip->ptm2ms), 0x00000000);
/* Disable outbound region two */
out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
out_le32((void *) &(pcip->pmm[2].la), 0x00000000); out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000); out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000); out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
out_le32((void *) &(pcip->ptm2ms), 0x00000000);
/* Zero config bars */ /* Zero config bars */
for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
...@@ -283,9 +290,11 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, ...@@ -283,9 +290,11 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
ppc_md.setup_arch = sycamore_setup_arch; ppc_md.setup_arch = sycamore_setup_arch;
ppc_md.setup_io_mappings = sycamore_map_io; ppc_md.setup_io_mappings = sycamore_map_io;
#ifdef CONFIG_GEN_RTC
ppc_md.time_init = todc_time_init; ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time; ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time; ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.nvram_read_val = todc_direct_read_val; ppc_md.nvram_read_val = todc_direct_read_val;
ppc_md.nvram_write_val = todc_direct_write_val; ppc_md.nvram_write_val = todc_direct_write_val;
#endif
} }
arch/ppc/platforms/4xx/walnut.c
View file @ a355c17b
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
#include <asm/page.h> #include <asm/page.h>
#include <asm/time.h> #include <asm/time.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/ocp.h>
#include <asm/ibm_ocp_pci.h> #include <asm/ibm_ocp_pci.h>
#include <asm/todc.h> #include <asm/todc.h>
...@@ -78,6 +79,8 @@ walnut_setup_arch(void) ...@@ -78,6 +79,8 @@ walnut_setup_arch(void)
ppc4xx_setup_arch(); ppc4xx_setup_arch();
ibm_ocp_set_emac(0, 0);
kb_data = ioremap(WALNUT_PS2_BASE, 8); kb_data = ioremap(WALNUT_PS2_BASE, 8);
if (!kb_data) { if (!kb_data) {
printk(KERN_CRIT printk(KERN_CRIT
......
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