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Commit a406c139 authored by Nick Kossifidis's avatar Nick Kossifidis Committed by John W. Linville
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ath5k: Update initvals 

 * Update initvals to match legacy and Sam's HAL
Signed-off-by: default avatarNick Kossifidis <mickflemm@gmail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 8892e4ec
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Showing with 687 additions and 947 deletions
drivers/net/wireless/ath5k/initvals.c
View file @ a406c139
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
* Initial register settings functions * Initial register settings functions
* *
* Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
* Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
* Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
* *
* Permission to use, copy, modify, and distribute this software for any * Permission to use, copy, modify, and distribute this software for any
...@@ -340,7 +340,7 @@ static const struct ath5k_ini ar5211_ini[] = { ...@@ -340,7 +340,7 @@ static const struct ath5k_ini ar5211_ini[] = {
* common on all cards/modes. * common on all cards/modes.
* Note: Table is rewritten during * Note: Table is rewritten during
* txpower setup later using calibration * txpower setup later using calibration
* data etc. so next write is non-common * data etc. so next write is non-common */
{ AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff }, { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff },
{ AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff }, { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff },
{ AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff }, { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff },
...@@ -371,7 +371,7 @@ static const struct ath5k_ini ar5211_ini[] = { ...@@ -371,7 +371,7 @@ static const struct ath5k_ini ar5211_ini[] = {
{ AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff }, { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff },
{ AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff }, { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff },
{ AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff }, { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff },
{ AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff },*/ { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff },
{ AR5K_PHY_CCKTXCTL, 0x00000000 }, { AR5K_PHY_CCKTXCTL, 0x00000000 },
{ AR5K_PHY(642), 0x503e4646 }, { AR5K_PHY(642), 0x503e4646 },
{ AR5K_PHY_GAIN_2GHZ, 0x6480416c }, { AR5K_PHY_GAIN_2GHZ, 0x6480416c },
...@@ -386,85 +386,85 @@ static const struct ath5k_ini ar5211_ini[] = { ...@@ -386,85 +386,85 @@ static const struct ath5k_ini ar5211_ini[] = {
}; };
/* Initial mode-specific settings for AR5211 /* Initial mode-specific settings for AR5211
* XXX: how about g / gTurbo ? RF5111 supports it, how about AR5211 ? * 5211 supports OFDM-only g (draft g) but we
* Maybe 5211 supports OFDM-only g but we need to test it ! * need to test it !
*/ */
static const struct ath5k_ini_mode ar5211_ini_mode[] = { static const struct ath5k_ini_mode ar5211_ini_mode[] = {
{ AR5K_TXCFG, { AR5K_TXCFG,
/* a aTurbo b */ /* a aTurbo b g (OFDM) */
{ 0x00000015, 0x00000015, 0x0000001d } }, { 0x00000015, 0x00000015, 0x0000001d, 0x00000015 } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(0), { AR5K_QUEUE_DFS_LOCAL_IFS(0),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(1), { AR5K_QUEUE_DFS_LOCAL_IFS(1),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(2), { AR5K_QUEUE_DFS_LOCAL_IFS(2),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(3), { AR5K_QUEUE_DFS_LOCAL_IFS(3),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(4), { AR5K_QUEUE_DFS_LOCAL_IFS(4),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(5), { AR5K_QUEUE_DFS_LOCAL_IFS(5),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(6), { AR5K_QUEUE_DFS_LOCAL_IFS(6),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(7), { AR5K_QUEUE_DFS_LOCAL_IFS(7),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(8), { AR5K_QUEUE_DFS_LOCAL_IFS(8),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(9), { AR5K_QUEUE_DFS_LOCAL_IFS(9),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
{ AR5K_DCU_GBL_IFS_SLOT, { AR5K_DCU_GBL_IFS_SLOT,
{ 0x00000168, 0x000001e0, 0x000001b8 } }, { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } },
{ AR5K_DCU_GBL_IFS_SIFS, { AR5K_DCU_GBL_IFS_SIFS,
{ 0x00000230, 0x000001e0, 0x000000b0 } }, { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } },
{ AR5K_DCU_GBL_IFS_EIFS, { AR5K_DCU_GBL_IFS_EIFS,
{ 0x00000d98, 0x00001180, 0x00001f48 } }, { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } },
{ AR5K_DCU_GBL_IFS_MISC, { AR5K_DCU_GBL_IFS_MISC,
{ 0x0000a0e0, 0x00014068, 0x00005880 } }, { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } },
{ AR5K_TIME_OUT, { AR5K_TIME_OUT,
{ 0x04000400, 0x08000800, 0x20003000 } }, { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } },
{ AR5K_USEC_5211, { AR5K_USEC_5211,
{ 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95 } }, { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } },
{ AR5K_PHY_TURBO, { AR5K_PHY_TURBO,
{ 0x00000000, 0x00000003, 0x00000000 } }, { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } },
{ AR5K_PHY(8), { AR5K_PHY(8),
{ 0x02020200, 0x02020200, 0x02010200 } }, { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } },
{ AR5K_PHY(9), { AR5K_PHY(9),
{ 0x00000e0e, 0x00000e0e, 0x00000707 } }, { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } },
{ AR5K_PHY(10), { AR5K_PHY(10),
{ 0x0a020001, 0x0a020001, 0x05010000 } }, { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } },
{ AR5K_PHY(13), { AR5K_PHY(13),
{ 0x00000e0e, 0x00000e0e, 0x00000e0e } }, { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
{ AR5K_PHY(14), { AR5K_PHY(14),
{ 0x00000007, 0x00000007, 0x0000000b } }, { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } },
{ AR5K_PHY(17), { AR5K_PHY(17),
{ 0x1372169c, 0x137216a5, 0x137216a8 } }, { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } },
{ AR5K_PHY(18), { AR5K_PHY(18),
{ 0x0018ba67, 0x0018ba67, 0x0018ba69 } }, { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } },
{ AR5K_PHY(20), { AR5K_PHY(20),
{ 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } }, { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
{ AR5K_PHY_SIG, { AR5K_PHY_SIG,
{ 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e } }, { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },
{ AR5K_PHY_AGCCOARSE, { AR5K_PHY_AGCCOARSE,
{ 0x31375d5e, 0x31375d5e, 0x313a5d5e } }, { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } },
{ AR5K_PHY_AGCCTL, { AR5K_PHY_AGCCTL,
{ 0x0000bd10, 0x0000bd10, 0x0000bd38 } }, { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } },
{ AR5K_PHY_NF, { AR5K_PHY_NF,
{ 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
{ AR5K_PHY_RX_DELAY, { AR5K_PHY_RX_DELAY,
{ 0x00002710, 0x00002710, 0x0000157c } }, { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } },
{ AR5K_PHY(70), { AR5K_PHY(70),
{ 0x00000190, 0x00000190, 0x00000084 } }, { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } },
{ AR5K_PHY_FRAME_CTL_5211, { AR5K_PHY_FRAME_CTL_5211,
{ 0x6fe01020, 0x6fe01020, 0x6fe00920 } }, { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
{ AR5K_PHY_PCDAC_TXPOWER_BASE_5211, { AR5K_PHY_PCDAC_TXPOWER_BASE,
{ 0x05ff14ff, 0x05ff14ff, 0x05ff14ff } }, { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
{ AR5K_RF_BUFFER_CONTROL_4, { AR5K_RF_BUFFER_CONTROL_4,
{ 0x00000010, 0x00000014, 0x00000010 } }, { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } },
}; };
/* Initial register settings for AR5212 */ /* Initial register settings for AR5212 */
static const struct ath5k_ini ar5212_ini[] = { static const struct ath5k_ini ar5212_ini_common_start[] = {
{ AR5K_RXDP, 0x00000000 }, { AR5K_RXDP, 0x00000000 },
{ AR5K_RXCFG, 0x00000005 }, { AR5K_RXCFG, 0x00000005 },
{ AR5K_MIBC, 0x00000000 }, { AR5K_MIBC, 0x00000000 },
...@@ -485,91 +485,83 @@ static const struct ath5k_ini ar5212_ini[] = { ...@@ -485,91 +485,83 @@ static const struct ath5k_ini ar5212_ini[] = {
{ AR5K_QUEUE_TXDP(9), 0x00000000 }, { AR5K_QUEUE_TXDP(9), 0x00000000 },
{ AR5K_DCU_FP, 0x00000000 }, { AR5K_DCU_FP, 0x00000000 },
{ AR5K_DCU_TXP, 0x00000000 }, { AR5K_DCU_TXP, 0x00000000 },
{ AR5K_DCU_TX_FILTER_0_BASE, 0x00000000 }, /* Tx filter table 0 (32 entries) */
/* Unknown table */ { AR5K_DCU_TX_FILTER_0(0), 0x00000000 }, /* DCU 0 */
{ 0x1078, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(1), 0x00000000 },
{ 0x10b8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(2), 0x00000000 },
{ 0x10f8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(3), 0x00000000 },
{ 0x1138, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(4), 0x00000000 }, /* DCU 1 */
{ 0x1178, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(5), 0x00000000 },
{ 0x11b8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(6), 0x00000000 },
{ 0x11f8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(7), 0x00000000 },
{ 0x1238, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(8), 0x00000000 }, /* DCU 2 */
{ 0x1278, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(9), 0x00000000 },
{ 0x12b8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(10), 0x00000000 },
{ 0x12f8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(11), 0x00000000 },
{ 0x1338, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(12), 0x00000000 }, /* DCU 3 */
{ 0x1378, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(13), 0x00000000 },
{ 0x13b8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(14), 0x00000000 },
{ 0x13f8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(15), 0x00000000 },
{ 0x1438, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(16), 0x00000000 }, /* DCU 4 */
{ 0x1478, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(17), 0x00000000 },
{ 0x14b8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(18), 0x00000000 },
{ 0x14f8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(19), 0x00000000 },
{ 0x1538, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(20), 0x00000000 }, /* DCU 5 */
{ 0x1578, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(21), 0x00000000 },
{ 0x15b8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(22), 0x00000000 },
{ 0x15f8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(23), 0x00000000 },
{ 0x1638, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(24), 0x00000000 }, /* DCU 6 */
{ 0x1678, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(25), 0x00000000 },
{ 0x16b8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(26), 0x00000000 },
{ 0x16f8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(27), 0x00000000 },
{ 0x1738, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(28), 0x00000000 }, /* DCU 7 */
{ 0x1778, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(29), 0x00000000 },
{ 0x17b8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(30), 0x00000000 },
{ 0x17f8, 0x00000000 }, { AR5K_DCU_TX_FILTER_0(31), 0x00000000 },
{ 0x103c, 0x00000000 }, /* Tx filter table 1 (16 entries) */
{ 0x107c, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(0), 0x00000000 },
{ 0x10bc, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(1), 0x00000000 },
{ 0x10fc, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(2), 0x00000000 },
{ 0x113c, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(3), 0x00000000 },
{ 0x117c, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(4), 0x00000000 },
{ 0x11bc, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(5), 0x00000000 },
{ 0x11fc, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(6), 0x00000000 },
{ 0x123c, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(7), 0x00000000 },
{ 0x127c, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(8), 0x00000000 },
{ 0x12bc, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(9), 0x00000000 },
{ 0x12fc, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(10), 0x00000000 },
{ 0x133c, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(11), 0x00000000 },
{ 0x137c, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(12), 0x00000000 },
{ 0x13bc, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(13), 0x00000000 },
{ 0x13fc, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(14), 0x00000000 },
{ 0x143c, 0x00000000 }, { AR5K_DCU_TX_FILTER_1(15), 0x00000000 },
{ 0x147c, 0x00000000 }, { AR5K_DCU_TX_FILTER_CLR, 0x00000000 },
{ AR5K_DCU_TX_FILTER_SET, 0x00000000 },
{ AR5K_DCU_TX_FILTER_CLR, 0x00000000 }, { AR5K_DCU_TX_FILTER_CLR, 0x00000000 },
{ AR5K_DCU_TX_FILTER_SET, 0x00000000 }, { AR5K_DCU_TX_FILTER_SET, 0x00000000 },
{ AR5K_STA_ID1, 0x00000000 }, { AR5K_STA_ID1, 0x00000000 },
{ AR5K_BSS_ID0, 0x00000000 }, { AR5K_BSS_ID0, 0x00000000 },
{ AR5K_BSS_ID1, 0x00000000 }, { AR5K_BSS_ID1, 0x00000000 },
/*{ AR5K_RSSI_THR, 0x00000000 },*/ /* Found on SuperAG cards */ { AR5K_BEACON_5211, 0x00000000 },
{ AR5K_BEACON_5211, 0x00000000 }, /* Found on SuperAG cards */ { AR5K_CFP_PERIOD_5211, 0x00000000 },
{ AR5K_CFP_PERIOD_5211, 0x00000000 }, /* Found on SuperAG cards */ { AR5K_TIMER0_5211, 0x00000030 },
{ AR5K_TIMER0_5211, 0x00000030 }, /* Found on SuperAG cards */ { AR5K_TIMER1_5211, 0x0007ffff },
{ AR5K_TIMER1_5211, 0x0007ffff }, /* Found on SuperAG cards */ { AR5K_TIMER2_5211, 0x01ffffff },
{ AR5K_TIMER2_5211, 0x01ffffff }, /* Found on SuperAG cards */ { AR5K_TIMER3_5211, 0x00000031 },
{ AR5K_TIMER3_5211, 0x00000031 }, /* Found on SuperAG cards */ { AR5K_CFP_DUR_5211, 0x00000000 },
{ AR5K_CFP_DUR_5211, 0x00000000 }, /* Found on SuperAG cards */
{ AR5K_RX_FILTER_5211, 0x00000000 }, { AR5K_RX_FILTER_5211, 0x00000000 },
{ AR5K_DIAG_SW_5211, 0x00000000 }, { AR5K_DIAG_SW_5211, 0x00000000 },
{ AR5K_ADDAC_TEST, 0x00000000 }, { AR5K_ADDAC_TEST, 0x00000000 },
{ AR5K_DEFAULT_ANTENNA, 0x00000000 }, { AR5K_DEFAULT_ANTENNA, 0x00000000 },
{ 0x8080, 0x00000000 }, { AR5K_FRAME_CTL_QOSM, 0x000fc78f },
/*{ 0x805c, 0xffffc7ff },*/ /* Old value */
{ 0x805c, 0x000fc78f },
{ AR5K_NAV_5211, 0x00000000 }, /* Not found on recent */
{ AR5K_RTS_OK_5211, 0x00000000 }, /* dumps but it makes */
{ AR5K_RTS_FAIL_5211, 0x00000000 }, /* sense to reset counters */
{ AR5K_ACK_FAIL_5211, 0x00000000 }, /* since pcu registers */
{ AR5K_FCS_FAIL_5211, 0x00000000 }, /* are skiped during chan*/
{ AR5K_BEACON_CNT_5211, 0x00000000 }, /* change */
{ AR5K_XRMODE, 0x2a82301a }, { AR5K_XRMODE, 0x2a82301a },
{ AR5K_XRDELAY, 0x05dc01e0 }, { AR5K_XRDELAY, 0x05dc01e0 },
{ AR5K_XRTIMEOUT, 0x1f402710 }, { AR5K_XRTIMEOUT, 0x1f402710 },
{ AR5K_XRCHIRP, 0x01f40000 }, { AR5K_XRCHIRP, 0x01f40000 },
{ AR5K_XRSTOMP, 0x00001e1c }, { AR5K_XRSTOMP, 0x00001e1c },
{ AR5K_SLEEP0, 0x0002aaaa }, /* Found on SuperAG cards */ { AR5K_SLEEP0, 0x0002aaaa },
{ AR5K_SLEEP1, 0x02005555 }, /* Found on SuperAG cards */ { AR5K_SLEEP1, 0x02005555 },
{ AR5K_SLEEP2, 0x00000000 }, /* Found on SuperAG cards */ { AR5K_SLEEP2, 0x00000000 },
{ AR5K_BSS_IDM0, 0xffffffff }, { AR5K_BSS_IDM0, 0xffffffff },
{ AR5K_BSS_IDM1, 0x0000ffff }, { AR5K_BSS_IDM1, 0x0000ffff },
{ AR5K_TXPC, 0x00000000 }, { AR5K_TXPC, 0x00000000 },
...@@ -577,7 +569,8 @@ static const struct ath5k_ini ar5212_ini[] = { ...@@ -577,7 +569,8 @@ static const struct ath5k_ini ar5212_ini[] = {
{ AR5K_PROFCNT_RX, 0x00000000 }, { AR5K_PROFCNT_RX, 0x00000000 },
{ AR5K_PROFCNT_RXCLR, 0x00000000 }, { AR5K_PROFCNT_RXCLR, 0x00000000 },
{ AR5K_PROFCNT_CYCLE, 0x00000000 }, { AR5K_PROFCNT_CYCLE, 0x00000000 },
{ 0x80fc, 0x00000088 }, { AR5K_QUIET_CTL1, 0x00000088 },
/* Initial rate duration table (32 entries )*/
{ AR5K_RATE_DUR(0), 0x00000000 }, { AR5K_RATE_DUR(0), 0x00000000 },
{ AR5K_RATE_DUR(1), 0x0000008c }, { AR5K_RATE_DUR(1), 0x0000008c },
{ AR5K_RATE_DUR(2), 0x000000e4 }, { AR5K_RATE_DUR(2), 0x000000e4 },
...@@ -610,881 +603,625 @@ static const struct ath5k_ini ar5212_ini[] = { ...@@ -610,881 +603,625 @@ static const struct ath5k_ini ar5212_ini[] = {
{ AR5K_RATE_DUR(29), 0x0000007f }, { AR5K_RATE_DUR(29), 0x0000007f },
{ AR5K_RATE_DUR(30), 0x000000a2 }, { AR5K_RATE_DUR(30), 0x000000a2 },
{ AR5K_RATE_DUR(31), 0x00000000 }, { AR5K_RATE_DUR(31), 0x00000000 },
{ 0x8100, 0x00010002}, { AR5K_QUIET_CTL2, 0x00010002 },
{ AR5K_TSF_PARM, 0x00000001 }, { AR5K_TSF_PARM, 0x00000001 },
{ 0x8108, 0x000000c0 }, { AR5K_QOS_NOACK, 0x000000c0 },
{ AR5K_PHY_ERR_FIL, 0x00000000 }, { AR5K_PHY_ERR_FIL, 0x00000000 },
{ 0x8110, 0x00000168 }, { AR5K_XRLAT_TX, 0x00000168 },
{ 0x8114, 0x00000000 }, { AR5K_ACKSIFS, 0x00000000 },
/* Some kind of table /* Rate -> db table
* also notice ...03<-02<-01<-00) */ * notice ...03<-02<-01<-00 ! */
{ 0x87c0, 0x03020100 }, { AR5K_RATE2DB(0), 0x03020100 },
{ 0x87c4, 0x07060504 }, { AR5K_RATE2DB(1), 0x07060504 },
{ 0x87c8, 0x0b0a0908 }, { AR5K_RATE2DB(2), 0x0b0a0908 },
{ 0x87cc, 0x0f0e0d0c }, { AR5K_RATE2DB(3), 0x0f0e0d0c },
{ 0x87d0, 0x13121110 }, { AR5K_RATE2DB(4), 0x13121110 },
{ 0x87d4, 0x17161514 }, { AR5K_RATE2DB(5), 0x17161514 },
{ 0x87d8, 0x1b1a1918 }, { AR5K_RATE2DB(6), 0x1b1a1918 },
{ 0x87dc, 0x1f1e1d1c }, { AR5K_RATE2DB(7), 0x1f1e1d1c },
/* loop ? */ /* Db -> Rate table */
{ 0x87e0, 0x03020100 }, { AR5K_DB2RATE(0), 0x03020100 },
{ 0x87e4, 0x07060504 }, { AR5K_DB2RATE(1), 0x07060504 },
{ 0x87e8, 0x0b0a0908 }, { AR5K_DB2RATE(2), 0x0b0a0908 },
{ 0x87ec, 0x0f0e0d0c }, { AR5K_DB2RATE(3), 0x0f0e0d0c },
{ 0x87f0, 0x13121110 }, { AR5K_DB2RATE(4), 0x13121110 },
{ 0x87f4, 0x17161514 }, { AR5K_DB2RATE(5), 0x17161514 },
{ 0x87f8, 0x1b1a1918 }, { AR5K_DB2RATE(6), 0x1b1a1918 },
{ 0x87fc, 0x1f1e1d1c }, { AR5K_DB2RATE(7), 0x1f1e1d1c },
/* PHY registers */ /* PHY registers (Common settings
/*{ AR5K_PHY_AGC, 0x00000000 },*/ * for all chips/modes) */
{ AR5K_PHY(3), 0xad848e19 }, { AR5K_PHY(3), 0xad848e19 },
{ AR5K_PHY(4), 0x7d28e000 }, { AR5K_PHY(4), 0x7d28e000 },
{ AR5K_PHY_TIMING_3, 0x9c0a9f6b }, { AR5K_PHY_TIMING_3, 0x9c0a9f6b },
{ AR5K_PHY_ACT, 0x00000000 }, { AR5K_PHY_ACT, 0x00000000 },
/*{ AR5K_PHY(11), 0x00022ffe },*/ { AR5K_PHY(16), 0x206a017a },
/*{ AR5K_PHY(15), 0x00020100 },*/ { AR5K_PHY(21), 0x00000859 },
{ AR5K_PHY(16), 0x206a017a }, { AR5K_PHY_BIN_MASK_1, 0x00000000 },
/*{ AR5K_PHY(19), 0x1284613c },*/ { AR5K_PHY_BIN_MASK_2, 0x00000000 },
{ AR5K_PHY(21), 0x00000859 }, { AR5K_PHY_BIN_MASK_3, 0x00000000 },
{ AR5K_PHY(64), 0x00000000 }, { AR5K_PHY_BIN_MASK_CTL, 0x00800000 },
{ AR5K_PHY(65), 0x00000000 }, { AR5K_PHY_ANT_CTL, 0x00000001 },
{ AR5K_PHY(66), 0x00000000 },
{ AR5K_PHY(67), 0x00800000 },
{ AR5K_PHY(68), 0x00000001 },
/*{ AR5K_PHY(71), 0x0000092a },*/ /* Old value */ /*{ AR5K_PHY(71), 0x0000092a },*/ /* Old value */
{ AR5K_PHY(71), 0x00000c80 }, { AR5K_PHY_MAX_RX_LEN, 0x00000c80 },
{ AR5K_PHY_IQ, 0x05100000 }, { AR5K_PHY_IQ, 0x05100000 },
{ AR5K_PHY(74), 0x00000001 }, { AR5K_PHY_WARM_RESET, 0x00000001 },
{ AR5K_PHY(75), 0x00000004 }, { AR5K_PHY_CTL, 0x00000004 },
{ AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022 }, { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022 },
{ AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d }, { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d },
{ AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f }, { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f },
/*{ AR5K_PHY(80), 0x00000004 },*/ { AR5K_PHY(82), 0x9280b212 },
{ AR5K_PHY(82), 0x9280b212 }, { AR5K_PHY_RADAR, 0x5d50e188 },
{ AR5K_PHY_RADAR, 0x5d50e188 },
/*{ AR5K_PHY(86), 0x000000ff },*/ /*{ AR5K_PHY(86), 0x000000ff },*/
{ AR5K_PHY(87), 0x004b6a8e }, { AR5K_PHY(87), 0x004b6a8e },
{ AR5K_PHY(90), 0x000003ce }, { AR5K_PHY_NFTHRES, 0x000003ce },
{ AR5K_PHY(92), 0x192fb515 }, { AR5K_PHY_RESTART, 0x192fb515 },
/*{ AR5K_PHY(93), 0x00000000 },*/ { AR5K_PHY(94), 0x00000001 },
{ AR5K_PHY(94), 0x00000001 }, { AR5K_PHY_RFBUS_REQ, 0x00000000 },
{ AR5K_PHY(95), 0x00000000 },
/*{ AR5K_PHY(644), 0x0080a333 },*/ /* Old value */ /*{ AR5K_PHY(644), 0x0080a333 },*/ /* Old value */
/*{ AR5K_PHY(645), 0x00206c10 },*/ /* Old value */ /*{ AR5K_PHY(645), 0x00206c10 },*/ /* Old value */
{ AR5K_PHY(644), 0x00806333 }, { AR5K_PHY(644), 0x00806333 },
{ AR5K_PHY(645), 0x00106c10 }, { AR5K_PHY(645), 0x00106c10 },
{ AR5K_PHY(646), 0x009c4060 }, { AR5K_PHY(646), 0x009c4060 },
{ AR5K_PHY(647), 0x1483800a }, /* { AR5K_PHY(647), 0x1483800a }, */
/* { AR5K_PHY(648), 0x018830c6 },*/ /* 2413/2425 */ /* { AR5K_PHY(648), 0x01831061 }, */ /* Old value */
{ AR5K_PHY(648), 0x01831061 }, { AR5K_PHY(648), 0x018830c6 },
{ AR5K_PHY(649), 0x00000400 }, { AR5K_PHY(649), 0x00000400 },
/*{ AR5K_PHY(650), 0x000001b5 },*/ /*{ AR5K_PHY(650), 0x000001b5 },*/
{ AR5K_PHY(651), 0x00000000 }, { AR5K_PHY(651), 0x00000000 },
{ AR5K_PHY_TXPOWER_RATE3, 0x20202020 }, { AR5K_PHY_TXPOWER_RATE3, 0x20202020 },
{ AR5K_PHY_TXPOWER_RATE2, 0x20202020 }, { AR5K_PHY_TXPOWER_RATE2, 0x20202020 },
/*{ AR5K_PHY(655), 0x13c889af },*/ /*{ AR5K_PHY(655), 0x13c889af },*/
{ AR5K_PHY(656), 0x38490a20 }, { AR5K_PHY(656), 0x38490a20 },
{ AR5K_PHY(657), 0x00007bb6 }, { AR5K_PHY(657), 0x00007bb6 },
{ AR5K_PHY(658), 0x0fff3ffc }, { AR5K_PHY(658), 0x0fff3ffc },
/*{ AR5K_PHY_CCKTXCTL, 0x00000000 },*/
}; };
/* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */ /* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */
static const struct ath5k_ini_mode ar5212_ini_mode_start[] = { static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
{ AR5K_PHY(640),
/* a/XR aTurbo b g (DYN) gTurbo */
{ 0x00000008, 0x00000008, 0x0000000b, 0x0000000e, 0x0000000e } },
{ AR5K_PHY(0),
{ 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(0), { AR5K_QUEUE_DFS_LOCAL_IFS(0),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, /* a/XR aTurbo b g (DYN) gTurbo */
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(1), { AR5K_QUEUE_DFS_LOCAL_IFS(1),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(2), { AR5K_QUEUE_DFS_LOCAL_IFS(2),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(3), { AR5K_QUEUE_DFS_LOCAL_IFS(3),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(4), { AR5K_QUEUE_DFS_LOCAL_IFS(4),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(5), { AR5K_QUEUE_DFS_LOCAL_IFS(5),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(6), { AR5K_QUEUE_DFS_LOCAL_IFS(6),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(7), { AR5K_QUEUE_DFS_LOCAL_IFS(7),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(8), { AR5K_QUEUE_DFS_LOCAL_IFS(8),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
{ AR5K_QUEUE_DFS_LOCAL_IFS(9), { AR5K_QUEUE_DFS_LOCAL_IFS(9),
{ 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
{ AR5K_DCU_GBL_IFS_SIFS, { AR5K_DCU_GBL_IFS_SIFS,
{ 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } }, { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } },
{ AR5K_DCU_GBL_IFS_SLOT, { AR5K_DCU_GBL_IFS_SLOT,
{ 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } }, { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } },
{ AR5K_DCU_GBL_IFS_EIFS, { AR5K_DCU_GBL_IFS_EIFS,
{ 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } }, { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } },
{ AR5K_DCU_GBL_IFS_MISC, { AR5K_DCU_GBL_IFS_MISC,
{ 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } }, { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } },
{ AR5K_TIME_OUT, { AR5K_TIME_OUT,
{ 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } }, { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } },
{ AR5K_PHY_TURBO, { AR5K_PHY_TURBO,
{ 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } }, { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } },
{ AR5K_PHY(8), { AR5K_PHY(8),
{ 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } }, { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } },
{ AR5K_PHY(9), { AR5K_PHY_RF_CTL2,
{ 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } }, { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } },
{ AR5K_PHY(17), { AR5K_PHY_SETTLING,
{ 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } }, { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } },
{ AR5K_PHY_AGCCTL, { AR5K_PHY_AGCCTL,
{ 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d18 } }, { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d18 } },
{ AR5K_PHY_NF, { AR5K_PHY_NF,
{ 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
{ AR5K_PHY(26), { AR5K_PHY_WEAK_OFDM_HIGH_THR,
{ 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } }, { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } },
{ AR5K_PHY(70), { AR5K_PHY(70),
{ 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } }, { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } },
{ AR5K_PHY(73), { AR5K_PHY_OFDM_SELFCORR,
{ 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } }, { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } },
{ 0xa230, { 0xa230,
{ 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } }, { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } },
}; };
/* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */ /* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
/* New dump pending */ static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
static const struct ath5k_ini_mode ar5212_rf5111_ini_mode_end[] = {
{ AR5K_PHY(640), /* This one differs from ar5212_ini_mode_start ! */
/* a/XR aTurbo b g (DYN) gTurbo */
{ 0x00000000, 0x00000000, 0x00000003, 0x00000006, 0x00000006 } },
{ AR5K_TXCFG, { AR5K_TXCFG,
{ 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } }, /* a/XR aTurbo b g (DYN) gTurbo */
{ 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
{ AR5K_USEC_5211, { AR5K_USEC_5211,
{ 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } }, { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } },
{ AR5K_PHY(10), { AR5K_PHY_RF_CTL3,
{ 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } }, { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } },
{ AR5K_PHY(13), { AR5K_PHY_RF_CTL4,
{ 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
{ AR5K_PHY(14), { AR5K_PHY_PA_CTL,
{ 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } }, { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
{ AR5K_PHY(18), { AR5K_PHY_GAIN,
{ 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } }, { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } },
{ AR5K_PHY(20), { AR5K_PHY_DESIRED_SIZE,
{ 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } }, { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
{ AR5K_PHY_SIG, { AR5K_PHY_SIG,
{ 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } }, { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } },
{ AR5K_PHY_AGCCOARSE, { AR5K_PHY_AGCCOARSE,
{ 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } }, { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } },
{ AR5K_PHY(27), { AR5K_PHY_WEAK_OFDM_LOW_THR,
{ 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } }, { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } },
{ AR5K_PHY_RX_DELAY, { AR5K_PHY_RX_DELAY,
{ 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } }, { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } },
{ AR5K_PHY_FRAME_CTL_5211, { AR5K_PHY_FRAME_CTL_5211,
{ 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } }, { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } },
{ AR5K_PHY_GAIN_2GHZ, { AR5K_PHY_GAIN_2GHZ,
{ 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } }, { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } },
{ 0xa21c, { AR5K_PHY_CCK_RX_CTL_4,
{ 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } }, { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
{ AR5K_DCU_FP, };
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
{ AR5K_PHY_AGC, static const struct ath5k_ini rf5111_ini_common_end[] = {
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_DCU_FP, 0x00000000 },
{ AR5K_PHY(11), { AR5K_PHY_AGC, 0x00000000 },
{ 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe } }, { AR5K_PHY_ADC_CTL, 0x00022ffe },
{ AR5K_PHY(15), { 0x983c, 0x00020100 },
{ 0x00020100, 0x00020100, 0x00020100, 0x00020100, 0x00020100 } }, { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
{ AR5K_PHY(19), { AR5K_PHY_PAPD_PROBE, 0x00004883 },
{ 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c } }, { 0x9940, 0x00000004 },
{ AR5K_PHY_PAPD_PROBE, { 0x9958, 0x000000ff },
{ 0x00004883, 0x00004883, 0x00004883, 0x00004883, 0x00004883 } }, { 0x9974, 0x00000000 },
{ AR5K_PHY(80), { AR5K_PHY_SPENDING, 0x00000018 },
{ 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 } }, { AR5K_PHY_CCKTXCTL, 0x00000000 },
{ AR5K_PHY(86), { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788 },
{ 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff } }, { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
{ AR5K_PHY(93), { 0xa23c, 0x13c889af },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
{ AR5K_PHY_SPENDING,
{ 0x00000018, 0x00000018, 0x00000018, 0x00000018, 0x00000018 } },
{ AR5K_PHY_CCKTXCTL,
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
{ AR5K_PHY(642),
{ 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
{ 0xa228,
{ 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5 } },
{ 0xa23c,
{ 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af } },
}; };
/* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */ /* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
/* XXX: No dumps for turbog yet, but i found settings from old values so it should be ok */ static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
static const struct ath5k_ini_mode ar5212_rf5112_ini_mode_end[] = {
{ AR5K_TXCFG, { AR5K_TXCFG,
/* a/XR aTurbo b g (DYN) gTurbo */ /* a/XR aTurbo b g (DYN) gTurbo */
{ 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } }, { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
{ AR5K_USEC_5211, { AR5K_USEC_5211,
{ 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } }, { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
{ AR5K_PHY(10), { AR5K_PHY_RF_CTL3,
{ 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } }, { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
{ AR5K_PHY(13), { AR5K_PHY_RF_CTL4,
{ 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
{ AR5K_PHY(14), { AR5K_PHY_PA_CTL,
{ 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } }, { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
{ AR5K_PHY(18), { AR5K_PHY_GAIN,
{ 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } }, { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } },
{ AR5K_PHY(20), { AR5K_PHY_DESIRED_SIZE,
{ 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } }, { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
{ AR5K_PHY_SIG, { AR5K_PHY_SIG,
{ 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7ee80d2e } }, { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7ee80d2e } },
{ AR5K_PHY_AGCCOARSE, { AR5K_PHY_AGCCOARSE,
{ 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } }, { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } },
{ AR5K_PHY(27), { AR5K_PHY_WEAK_OFDM_LOW_THR,
{ 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } }, { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
{ AR5K_PHY_RX_DELAY, { AR5K_PHY_RX_DELAY,
{ 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } }, { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
{ AR5K_PHY_FRAME_CTL_5211, { AR5K_PHY_FRAME_CTL_5211,
{ 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } }, { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } },
{ AR5K_PHY_CCKTXCTL, { AR5K_PHY_CCKTXCTL,
{ 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } }, { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } },
{ AR5K_PHY(642), { AR5K_PHY_CCK_CROSSCORR,
{ 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
{ AR5K_PHY_GAIN_2GHZ, { AR5K_PHY_GAIN_2GHZ,
{ 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } }, { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } },
{ 0xa21c, { AR5K_PHY_CCK_RX_CTL_4,
{ 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } }, { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
{ AR5K_DCU_FP, };
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
{ AR5K_PHY_AGC, static const struct ath5k_ini rf5112_ini_common_end[] = {
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_DCU_FP, 0x00000000 },
{ AR5K_PHY(11), { AR5K_PHY_AGC, 0x00000000 },
{ 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe } }, { AR5K_PHY_ADC_CTL, 0x00022ffe },
{ AR5K_PHY(15), { 0x983c, 0x00020100 },
{ 0x00020100, 0x00020100, 0x00020100, 0x00020100, 0x00020100 } }, { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
{ AR5K_PHY(19), { AR5K_PHY_PAPD_PROBE, 0x00004882 },
{ 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c } }, { 0x9940, 0x00000004 },
{ AR5K_PHY_PAPD_PROBE, { 0x9958, 0x000000ff },
{ 0x00004882, 0x00004882, 0x00004882, 0x00004882, 0x00004882 } }, { 0x9974, 0x00000000 },
{ AR5K_PHY(80), { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
{ 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 } }, { 0xa23c, 0x13c889af },
{ AR5K_PHY(86),
{ 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff } },
{ AR5K_PHY(93),
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa228,
{ 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5 } },
{ 0xa23c,
{ 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af } },
}; };
/* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */ /* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
/* XXX: No dumps for turbog yet, so turbog is the same with g here with some
* minor tweaking based on dumps from other chips */
static const struct ath5k_ini_mode rf5413_ini_mode_end[] = { static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
{ AR5K_TXCFG, { AR5K_TXCFG,
/* a/XR aTurbo b g gTurbo */ /* a/XR aTurbo b g (DYN) gTurbo */
{ 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } }, { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
{ AR5K_USEC_5211, { AR5K_USEC_5211,
{ 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } }, { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
{ AR5K_PHY(10), { AR5K_PHY_RF_CTL3,
{ 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } }, { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
{ AR5K_PHY(13), { AR5K_PHY_RF_CTL4,
{ 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
{ AR5K_PHY(14), { AR5K_PHY_PA_CTL,
{ 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } }, { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
{ AR5K_PHY(18), { AR5K_PHY_GAIN,
{ 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } }, { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } },
{ AR5K_PHY(20), { AR5K_PHY_DESIRED_SIZE,
{ 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } }, { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
{ AR5K_PHY_SIG, { AR5K_PHY_SIG,
{ 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } }, { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
{ AR5K_PHY_AGCCOARSE, { AR5K_PHY_AGCCOARSE,
{ 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } }, { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
{ AR5K_PHY(27), { AR5K_PHY_WEAK_OFDM_LOW_THR,
{ 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } }, { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
{ AR5K_PHY_RX_DELAY, { AR5K_PHY_RX_DELAY,
{ 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } }, { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
{ AR5K_PHY_FRAME_CTL_5211, { AR5K_PHY_FRAME_CTL_5211,
{ 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } }, { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
{ AR5K_PHY_CCKTXCTL, { AR5K_PHY_CCKTXCTL,
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
{ AR5K_PHY(642), { AR5K_PHY_CCK_CROSSCORR,
{ 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
{ AR5K_PHY_GAIN_2GHZ, { AR5K_PHY_GAIN_2GHZ,
{ 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } }, { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } },
{ 0xa21c, { AR5K_PHY_CCK_RX_CTL_4,
{ 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } }, { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
{ 0xa300, { 0xa300,
{ 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } }, { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } },
{ 0xa304, { 0xa304,
{ 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } }, { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } },
{ 0xa308, { 0xa308,
{ 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } }, { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } },
{ 0xa30c, { 0xa30c,
{ 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } }, { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
{ 0xa310, { 0xa310,
{ 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } }, { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } },
{ 0xa314, { 0xa314,
{ 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } }, { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
{ 0xa318, { 0xa318,
{ 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } }, { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
{ 0xa31c, { 0xa31c,
{ 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } }, { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
{ 0xa320, { 0xa320,
{ 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } }, { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } },
{ 0xa324, { 0xa324,
{ 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } }, { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } },
{ 0xa328, { 0xa328,
{ 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } }, { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } },
{ 0xa32c, { 0xa32c,
{ 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } }, { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } },
{ 0xa330, { 0xa330,
{ 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } }, { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } },
{ 0xa334, { 0xa334,
{ 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } }, { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
{ AR5K_DCU_FP, };
{ 0x000003e0, 0x000003e0, 0x000003e0, 0x000003e0, 0x000003e0 } },
{ 0x4068, static const struct ath5k_ini rf5413_ini_common_end[] = {
{ 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } }, { AR5K_DCU_FP, 0x000003e0 },
{ 0x8060, { AR5K_5414_CBCFG, 0x00000010 },
{ 0x0000000f, 0x0000000f, 0x0000000f, 0x0000000f, 0x0000000f } }, { AR5K_SEQ_MASK, 0x0000000f },
{ 0x809c, { 0x809c, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { 0x80a0, 0x00000000 },
{ 0x80a0, { AR5K_MIC_QOS_CTL, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_MIC_QOS_SEL, 0x00000000 },
{ 0x8118, { AR5K_MISC_MODE, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_OFDM_FIL_CNT, 0x00000000 },
{ 0x811c, { AR5K_CCK_FIL_CNT, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHYERR_CNT1, 0x00000000 },
{ 0x8120, { AR5K_PHYERR_CNT1_MASK, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHYERR_CNT2, 0x00000000 },
{ 0x8124, { AR5K_PHYERR_CNT2_MASK, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_TSF_THRES, 0x00000000 },
{ 0x8128, { 0x8140, 0x800003f9 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { 0x8144, 0x00000000 },
{ 0x812c, { AR5K_PHY_AGC, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHY_ADC_CTL, 0x0000a000 },
{ 0x8130, { 0x983c, 0x00200400 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHY_GAIN_OFFSET, 0x1284233c },
{ 0x8134, { AR5K_PHY_SCR, 0x0000001f },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHY_SLMT, 0x00000080 },
{ 0x8138, { AR5K_PHY_SCAL, 0x0000000e },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { 0x9958, 0x00081fff },
{ 0x813c, { AR5K_PHY_TIMING_7, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHY_TIMING_8, 0x02800000 },
{ 0x8140, { AR5K_PHY_TIMING_11, 0x00000000 },
{ 0x800003f9, 0x800003f9, 0x800003f9, 0x800003f9, 0x800003f9 } }, { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },
{ 0x8144, { 0x99e4, 0xaaaaaaaa },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { 0x99e8, 0x3c466478 },
{ AR5K_PHY_AGC, { 0x99ec, 0x000000aa },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHY_SCLOCK, 0x0000000c },
{ AR5K_PHY(11), { AR5K_PHY_SDELAY, 0x000000ff },
{ 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000 } }, { AR5K_PHY_SPENDING, 0x00000014 },
{ AR5K_PHY(15), { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },
{ 0x00200400, 0x00200400, 0x00200400, 0x00200400, 0x00200400 } }, { 0xa23c, 0x93c889af },
{ AR5K_PHY(19), { AR5K_PHY_FAST_ADC, 0x00000001 },
{ 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c } }, { 0xa250, 0x0000a000 },
{ AR5K_PHY_SCR, { AR5K_PHY_BLUETOOTH, 0x00000000 },
{ 0x0000001f, 0x0000001f, 0x0000001f, 0x0000001f, 0x0000001f } }, { AR5K_PHY_TPC_RG1, 0x0cc75380 },
{ AR5K_PHY_SLMT, { 0xa25c, 0x0f0f0f01 },
{ 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, { 0xa260, 0x5f690f01 },
{ AR5K_PHY_SCAL, { 0xa264, 0x00418a11 },
{ 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } }, { 0xa268, 0x00000000 },
{ AR5K_PHY(86), { AR5K_PHY_TPC_RG5, 0x0c30c16a },
{ 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff } }, { 0xa270, 0x00820820 },
{ AR5K_PHY(96), { 0xa274, 0x081b7caa },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { 0xa278, 0x1ce739ce },
{ AR5K_PHY(97), { 0xa27c, 0x051701ce },
{ 0x02800000, 0x02800000, 0x02800000, 0x02800000, 0x02800000 } }, { 0xa338, 0x00000000 },
{ AR5K_PHY(104), { 0xa33c, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { 0xa340, 0x00000000 },
{ AR5K_PHY(120), { 0xa344, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, { 0xa348, 0x3fffffff },
{ AR5K_PHY(121), { 0xa34c, 0x3fffffff },
{ 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa } }, { 0xa350, 0x3fffffff },
{ AR5K_PHY(122), { 0xa354, 0x0003ffff },
{ 0x3c466478, 0x3c466478, 0x3c466478, 0x3c466478, 0x3c466478 } }, { 0xa358, 0x79a8aa1f },
{ AR5K_PHY(123), { 0xa35c, 0x066c420f },
{ 0x000000aa, 0x000000aa, 0x000000aa, 0x000000aa, 0x000000aa } }, { 0xa360, 0x0f282207 },
{ AR5K_PHY_SCLOCK, { 0xa364, 0x17601685 },
{ 0x0000000c, 0x0000000c, 0x0000000c, 0x0000000c, 0x0000000c } }, { 0xa368, 0x1f801104 },
{ AR5K_PHY_SDELAY, { 0xa36c, 0x37a00c03 },
{ 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff } }, { 0xa370, 0x3fc40883 },
{ AR5K_PHY_SPENDING, { 0xa374, 0x57c00803 },
{ 0x00000014, 0x00000014, 0x00000014, 0x00000014, 0x00000014 } }, { 0xa378, 0x5fd80682 },
{ 0xa228, { 0xa37c, 0x7fe00482 },
{ 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5 } }, { 0xa380, 0x7f3c7bba },
{ 0xa23c, { 0xa384, 0xf3307ff0 },
{ 0x93c889af, 0x93c889af, 0x93c889af, 0x93c889af, 0x93c889af } },
{ 0xa24c,
{ 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
{ 0xa250,
{ 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000 } },
{ 0xa254,
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa258,
{ 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380 } },
{ 0xa25c,
{ 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01 } },
{ 0xa260,
{ 0x5f690f01, 0x5f690f01, 0x5f690f01, 0x5f690f01, 0x5f690f01 } },
{ 0xa264,
{ 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11 } },
{ 0xa268,
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa26c,
{ 0x0c30c16a, 0x0c30c16a, 0x0c30c16a, 0x0c30c16a, 0x0c30c16a } },
{ 0xa270,
{ 0x00820820, 0x00820820, 0x00820820, 0x00820820, 0x00820820 } },
{ 0xa274,
{ 0x081b7caa, 0x081b7caa, 0x081b7caa, 0x081b7caa, 0x081b7caa } },
{ 0xa278,
{ 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce } },
{ 0xa27c,
{ 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce } },
{ 0xa338,
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa33c,
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa340,
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa344,
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa348,
{ 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff } },
{ 0xa34c,
{ 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff } },
{ 0xa350,
{ 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff } },
{ 0xa354,
{ 0x0003ffff, 0x0003ffff, 0x0003ffff, 0x0003ffff, 0x0003ffff } },
{ 0xa358,
{ 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f } },
{ 0xa35c,
{ 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f } },
{ 0xa360,
{ 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207 } },
{ 0xa364,
{ 0x17601685, 0x17601685, 0x17601685, 0x17601685, 0x17601685 } },
{ 0xa368,
{ 0x1f801104, 0x1f801104, 0x1f801104, 0x1f801104, 0x1f801104 } },
{ 0xa36c,
{ 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03 } },
{ 0xa370,
{ 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883 } },
{ 0xa374,
{ 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803 } },
{ 0xa378,
{ 0x5fd80682, 0x5fd80682, 0x5fd80682, 0x5fd80682, 0x5fd80682 } },
{ 0xa37c,
{ 0x7fe00482, 0x7fe00482, 0x7fe00482, 0x7fe00482, 0x7fe00482 } },
{ 0xa380,
{ 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba } },
{ 0xa384,
{ 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0 } },
}; };
/* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */ /* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */
/* XXX: No dumps for turbog yet, so turbog is the same with g here with some /* XXX: a mode ? */
* minor tweaking based on dumps from other chips */
static const struct ath5k_ini_mode rf2413_ini_mode_end[] = { static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
{ AR5K_TXCFG, { AR5K_TXCFG,
/* b g gTurbo */ /* a/XR aTurbo b g (DYN) gTurbo */
{ 0x00000015, 0x00000015, 0x00000015 } }, { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
{ AR5K_USEC_5211, { AR5K_USEC_5211,
{ 0x04e01395, 0x12e013ab, 0x098813cf } }, { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
{ AR5K_PHY(10), { AR5K_PHY_RF_CTL3,
{ 0x05020000, 0x0a020001, 0x0a020001 } }, { 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 } },
{ AR5K_PHY(13), { AR5K_PHY_RF_CTL4,
{ 0x00000e00, 0x00000e00, 0x00000e00 } }, { 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 } },
{ AR5K_PHY(14), { AR5K_PHY_PA_CTL,
{ 0x0000000a, 0x0000000a, 0x0000000a } }, { 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a } },
{ AR5K_PHY(18), { AR5K_PHY_GAIN,
{ 0x001a6a64, 0x001a6a64, 0x001a6a64 } }, { 0x0018da6d, 0x0018da6d, 0x001a6a64, 0x001a6a64, 0x001a6a64 } },
{ AR5K_PHY(20), { AR5K_PHY_DESIRED_SIZE,
{ 0x0de8b0da, 0x0c98b0da, 0x0c98b0da } }, { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da } },
{ AR5K_PHY_SIG, { AR5K_PHY_SIG,
{ 0x7ee80d2e, 0x7ec80d2e, 0x7ec80d2e } }, { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e } },
{ AR5K_PHY_AGCCOARSE, { AR5K_PHY_AGCCOARSE,
{ 0x3137665e, 0x3139605e, 0x3139605e } }, { 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e } },
{ AR5K_PHY(27), { AR5K_PHY_WEAK_OFDM_LOW_THR,
{ 0x050cb081, 0x050cb081, 0x050cb081 } }, { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
{ AR5K_PHY_RX_DELAY, { AR5K_PHY_RX_DELAY,
{ 0x0000044c, 0x00000898, 0x000007d0 } }, { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
{ AR5K_PHY_FRAME_CTL_5211, { AR5K_PHY_FRAME_CTL_5211,
{ 0xf7b80d00, 0xf7b81000, 0xf7b81000 } }, { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
{ AR5K_PHY_CCKTXCTL, { AR5K_PHY_CCKTXCTL,
{ 0x00000000, 0x00000000, 0x00000000 } }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
{ AR5K_PHY(642), { AR5K_PHY_CCK_CROSSCORR,
{ 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
{ AR5K_PHY_GAIN_2GHZ, { AR5K_PHY_GAIN_2GHZ,
{ 0x0042c140, 0x0042c140, 0x0042c140 } }, { 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 } },
{ 0xa21c, { AR5K_PHY_CCK_RX_CTL_4,
{ 0x1863800a, 0x1883800a, 0x1883800a } }, { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
{ AR5K_DCU_FP, };
{ 0x000003e0, 0x000003e0, 0x000003e0 } },
{ 0x8060, static const struct ath5k_ini rf2413_ini_common_end[] = {
{ 0x0000000f, 0x0000000f, 0x0000000f } }, { AR5K_DCU_FP, 0x000003e0 },
{ 0x8118, { AR5K_SEQ_MASK, 0x0000000f },
{ 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_MIC_QOS_CTL, 0x00000000 },
{ 0x811c, { AR5K_MIC_QOS_SEL, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_MISC_MODE, 0x00000000 },
{ 0x8120, { AR5K_OFDM_FIL_CNT, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_CCK_FIL_CNT, 0x00000000 },
{ 0x8124, { AR5K_PHYERR_CNT1, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHYERR_CNT1_MASK, 0x00000000 },
{ 0x8128, { AR5K_PHYERR_CNT2, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHYERR_CNT2_MASK, 0x00000000 },
{ 0x812c, { AR5K_TSF_THRES, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000 } }, { 0x8140, 0x800000a8 },
{ 0x8130, { 0x8144, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHY_AGC, 0x00000000 },
{ 0x8134, { AR5K_PHY_ADC_CTL, 0x0000a000 },
{ 0x00000000, 0x00000000, 0x00000000 } }, { 0x983c, 0x00200400 },
{ 0x8138, { AR5K_PHY_GAIN_OFFSET, 0x1284233c },
{ 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHY_SCR, 0x0000001f },
{ 0x813c, { AR5K_PHY_SLMT, 0x00000080 },
{ 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHY_SCAL, 0x0000000e },
{ 0x8140, { 0x9958, 0x000000ff },
{ 0x800000a8, 0x800000a8, 0x800000a8 } }, { AR5K_PHY_TIMING_7, 0x00000000 },
{ 0x8144, { AR5K_PHY_TIMING_8, 0x02800000 },
{ 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHY_TIMING_11, 0x00000000 },
{ AR5K_PHY_AGC, { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000 } }, { 0x99e4, 0xaaaaaaaa },
{ AR5K_PHY(11), { 0x99e8, 0x3c466478 },
{ 0x0000a000, 0x0000a000, 0x0000a000 } }, { 0x99ec, 0x000000aa },
{ AR5K_PHY(15), { AR5K_PHY_SCLOCK, 0x0000000c },
{ 0x00200400, 0x00200400, 0x00200400 } }, { AR5K_PHY_SDELAY, 0x000000ff },
{ AR5K_PHY(19), { AR5K_PHY_SPENDING, 0x00000014 },
{ 0x1284233c, 0x1284233c, 0x1284233c } }, { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },
{ AR5K_PHY_SCR, { 0xa23c, 0x93c889af },
{ 0x0000001f, 0x0000001f, 0x0000001f } }, { AR5K_PHY_FAST_ADC, 0x00000001 },
{ AR5K_PHY_SLMT, { 0xa250, 0x0000a000 },
{ 0x00000080, 0x00000080, 0x00000080 } }, { AR5K_PHY_BLUETOOTH, 0x00000000 },
{ AR5K_PHY_SCAL, { AR5K_PHY_TPC_RG1, 0x0cc75380 },
{ 0x0000000e, 0x0000000e, 0x0000000e } }, { 0xa25c, 0x0f0f0f01 },
{ AR5K_PHY(86), { 0xa260, 0x5f690f01 },
{ 0x000000ff, 0x000000ff, 0x000000ff } }, { 0xa264, 0x00418a11 },
{ AR5K_PHY(96), { 0xa268, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000 } }, { AR5K_PHY_TPC_RG5, 0x0c30c16a },
{ AR5K_PHY(97), { 0xa270, 0x00820820 },
{ 0x02800000, 0x02800000, 0x02800000 } }, { 0xa274, 0x001b7caa },
{ AR5K_PHY(104), { 0xa278, 0x1ce739ce },
{ 0x00000000, 0x00000000, 0x00000000 } }, { 0xa27c, 0x051701ce },
{ AR5K_PHY(120), { 0xa300, 0x18010000 },
{ 0x00000000, 0x00000000, 0x00000000 } }, { 0xa304, 0x30032602 },
{ AR5K_PHY(121), { 0xa308, 0x48073e06 },
{ 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa } }, { 0xa30c, 0x560b4c0a },
{ AR5K_PHY(122), { 0xa310, 0x641a600f },
{ 0x3c466478, 0x3c466478, 0x3c466478 } }, { 0xa314, 0x784f6e1b },
{ AR5K_PHY(123), { 0xa318, 0x868f7c5a },
{ 0x000000aa, 0x000000aa, 0x000000aa } }, { 0xa31c, 0x8ecf865b },
{ AR5K_PHY_SCLOCK, { 0xa320, 0x9d4f970f },
{ 0x0000000c, 0x0000000c, 0x0000000c } }, { 0xa324, 0xa5cfa18f },
{ AR5K_PHY_SDELAY, { 0xa328, 0xb55faf1f },
{ 0x000000ff, 0x000000ff, 0x000000ff } }, { 0xa32c, 0xbddfb99f },
{ AR5K_PHY_SPENDING, { 0xa330, 0xcd7fc73f },
{ 0x00000014, 0x00000014, 0x00000014 } }, { 0xa334, 0xd5ffd1bf },
{ 0xa228, { 0xa338, 0x00000000 },
{ 0x000009b5, 0x000009b5, 0x000009b5 } }, { 0xa33c, 0x00000000 },
{ 0xa23c, { 0xa340, 0x00000000 },
{ 0x93c889af, 0x93c889af, 0x93c889af } }, { 0xa344, 0x00000000 },
{ 0xa24c, { 0xa348, 0x3fffffff },
{ 0x00000001, 0x00000001, 0x00000001 } }, { 0xa34c, 0x3fffffff },
{ 0xa250, { 0xa350, 0x3fffffff },
{ 0x0000a000, 0x0000a000, 0x0000a000 } }, { 0xa354, 0x0003ffff },
{ 0xa254, { 0xa358, 0x79a8aa1f },
{ 0x00000000, 0x00000000, 0x00000000 } }, { 0xa35c, 0x066c420f },
{ 0xa258, { 0xa360, 0x0f282207 },
{ 0x0cc75380, 0x0cc75380, 0x0cc75380 } }, { 0xa364, 0x17601685 },
{ 0xa25c, { 0xa368, 0x1f801104 },
{ 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01 } }, { 0xa36c, 0x37a00c03 },
{ 0xa260, { 0xa370, 0x3fc40883 },
{ 0x5f690f01, 0x5f690f01, 0x5f690f01 } }, { 0xa374, 0x57c00803 },
{ 0xa264, { 0xa378, 0x5fd80682 },
{ 0x00418a11, 0x00418a11, 0x00418a11 } }, { 0xa37c, 0x7fe00482 },
{ 0xa268, { 0xa380, 0x7f3c7bba },
{ 0x00000000, 0x00000000, 0x00000000 } }, { 0xa384, 0xf3307ff0 },
{ 0xa26c,
{ 0x0c30c16a, 0x0c30c16a, 0x0c30c16a } },
{ 0xa270,
{ 0x00820820, 0x00820820, 0x00820820 } },
{ 0xa274,
{ 0x001b7caa, 0x001b7caa, 0x001b7caa } },
{ 0xa278,
{ 0x1ce739ce, 0x1ce739ce, 0x1ce739ce } },
{ 0xa27c,
{ 0x051701ce, 0x051701ce, 0x051701ce } },
{ 0xa300,
{ 0x18010000, 0x18010000, 0x18010000 } },
{ 0xa304,
{ 0x30032602, 0x30032602, 0x30032602 } },
{ 0xa308,
{ 0x48073e06, 0x48073e06, 0x48073e06 } },
{ 0xa30c,
{ 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
{ 0xa310,
{ 0x641a600f, 0x641a600f, 0x641a600f } },
{ 0xa314,
{ 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
{ 0xa318,
{ 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
{ 0xa31c,
{ 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
{ 0xa320,
{ 0x9d4f970f, 0x9d4f970f, 0x9d4f970f } },
{ 0xa324,
{ 0xa5cfa18f, 0xa5cfa18f, 0xa5cfa18f } },
{ 0xa328,
{ 0xb55faf1f, 0xb55faf1f, 0xb55faf1f } },
{ 0xa32c,
{ 0xbddfb99f, 0xbddfb99f, 0xbddfb99f } },
{ 0xa330,
{ 0xcd7fc73f, 0xcd7fc73f, 0xcd7fc73f } },
{ 0xa334,
{ 0xd5ffd1bf, 0xd5ffd1bf, 0xd5ffd1bf } },
{ 0xa338,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa33c,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa340,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa344,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa348,
{ 0x3fffffff, 0x3fffffff, 0x3fffffff } },
{ 0xa34c,
{ 0x3fffffff, 0x3fffffff, 0x3fffffff } },
{ 0xa350,
{ 0x3fffffff, 0x3fffffff, 0x3fffffff } },
{ 0xa354,
{ 0x0003ffff, 0x0003ffff, 0x0003ffff } },
{ 0xa358,
{ 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f } },
{ 0xa35c,
{ 0x066c420f, 0x066c420f, 0x066c420f } },
{ 0xa360,
{ 0x0f282207, 0x0f282207, 0x0f282207 } },
{ 0xa364,
{ 0x17601685, 0x17601685, 0x17601685 } },
{ 0xa368,
{ 0x1f801104, 0x1f801104, 0x1f801104 } },
{ 0xa36c,
{ 0x37a00c03, 0x37a00c03, 0x37a00c03 } },
{ 0xa370,
{ 0x3fc40883, 0x3fc40883, 0x3fc40883 } },
{ 0xa374,
{ 0x57c00803, 0x57c00803, 0x57c00803 } },
{ 0xa378,
{ 0x5fd80682, 0x5fd80682, 0x5fd80682 } },
{ 0xa37c,
{ 0x7fe00482, 0x7fe00482, 0x7fe00482 } },
{ 0xa380,
{ 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba } },
{ 0xa384,
{ 0xf3307ff0, 0xf3307ff0, 0xf3307ff0 } },
}; };
/* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */ /* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */
/* XXX: No dumps for turbog yet, so turbog is the same with g here with some /* XXX: a mode ? */
* minor tweaking based on dumps from other chips */
static const struct ath5k_ini_mode rf2425_ini_mode_end[] = { static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
{ AR5K_TXCFG, { AR5K_TXCFG,
/* g gTurbo */ /* a/XR aTurbo b g (DYN) gTurbo */
{ 0x00000015, 0x00000015 } }, { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
{ AR5K_USEC_5211, { AR5K_USEC_5211,
{ 0x12e013ab, 0x098813cf } }, { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
{ AR5K_PHY_TURBO, { AR5K_PHY_TURBO,
{ 0x00000000, 0x00000003 } }, { 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001 } },
{ AR5K_PHY(10), { AR5K_PHY_RF_CTL3,
{ 0x0a020001, 0x0a020001 } }, { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
{ AR5K_PHY(13), { AR5K_PHY_RF_CTL4,
{ 0x00000e0e, 0x00000e0e } }, { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
{ AR5K_PHY(14), { AR5K_PHY_PA_CTL,
{ 0x0000000b, 0x0000000b } }, { 0x00000003, 0x00000003, 0x0000000b, 0x0000000b, 0x0000000b } },
{ AR5K_PHY(17), { AR5K_PHY_SETTLING,
{ 0x13721422, 0x13721422 } }, { 0x1372161c, 0x13721c25, 0x13721722, 0x13721422, 0x13721c25 } },
{ AR5K_PHY(18), { AR5K_PHY_GAIN,
{ 0x00199a65, 0x00199a65 } }, { 0x0018fa61, 0x0018fa61, 0x00199a65, 0x00199a65, 0x00199a65 } },
{ AR5K_PHY(20), { AR5K_PHY_DESIRED_SIZE,
{ 0x0c98b0da, 0x0c98b0da } }, { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
{ AR5K_PHY_SIG, { AR5K_PHY_SIG,
{ 0x7ec80d2e, 0x7ec80d2e } }, { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
{ AR5K_PHY_AGCCOARSE, { AR5K_PHY_AGCCOARSE,
{ 0x3139605e, 0x3139605e } }, { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
{ AR5K_PHY(27), { AR5K_PHY_WEAK_OFDM_LOW_THR,
{ 0x050cb081, 0x050cb081 } }, { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
{ AR5K_PHY_RX_DELAY, { AR5K_PHY_RX_DELAY,
{ 0x00000898, 0x000007d0 } }, { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
{ AR5K_PHY_FRAME_CTL_5211, { AR5K_PHY_FRAME_CTL_5211,
{ 0xf7b81000, 0xf7b81000 } }, { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
{ AR5K_PHY_CCKTXCTL, { AR5K_PHY_CCKTXCTL,
{ 0x00000000, 0x00000000 } }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
{ AR5K_PHY(642), { AR5K_PHY_CCK_CROSSCORR,
{ 0xd03e6788, 0xd03e6788 } }, { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
{ AR5K_PHY_GAIN_2GHZ, { AR5K_PHY_GAIN_2GHZ,
{ 0x0052c140, 0x0052c140 } }, { 0x00000140, 0x00000140, 0x0052c140, 0x0052c140, 0x0052c140 } },
{ 0xa21c, { AR5K_PHY_CCK_RX_CTL_4,
{ 0x1883800a, 0x1883800a } }, { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
{ 0xa324, { 0xa324,
{ 0xa7cfa7cf, 0xa7cfa7cf } }, { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
{ 0xa328, { 0xa328,
{ 0xa7cfa7cf, 0xa7cfa7cf } }, { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
{ 0xa32c, { 0xa32c,
{ 0xa7cfa7cf, 0xa7cfa7cf } }, { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
{ 0xa330, { 0xa330,
{ 0xa7cfa7cf, 0xa7cfa7cf } }, { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
{ 0xa334, { 0xa334,
{ 0xa7cfa7cf, 0xa7cfa7cf } }, { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
{ AR5K_DCU_FP, };
{ 0x000003e0, 0x000003e0 } },
{ 0x8060, static const struct ath5k_ini rf2425_ini_common_end[] = {
{ 0x0000000f, 0x0000000f } }, { AR5K_DCU_FP, 0x000003e0 },
{ 0x809c, { AR5K_SEQ_MASK, 0x0000000f },
{ 0x00000000, 0x00000000 } }, { 0x809c, 0x00000000 },
{ 0x80a0, { 0x80a0, 0x00000000 },
{ 0x00000000, 0x00000000 } }, { AR5K_MIC_QOS_CTL, 0x00000000 },
{ 0x8118, { AR5K_MIC_QOS_SEL, 0x00000000 },
{ 0x00000000, 0x00000000 } }, { AR5K_MISC_MODE, 0x00000000 },
{ 0x811c, { AR5K_OFDM_FIL_CNT, 0x00000000 },
{ 0x00000000, 0x00000000 } }, { AR5K_CCK_FIL_CNT, 0x00000000 },
{ 0x8120, { AR5K_PHYERR_CNT1, 0x00000000 },
{ 0x00000000, 0x00000000 } }, { AR5K_PHYERR_CNT1_MASK, 0x00000000 },
{ 0x8124, { AR5K_PHYERR_CNT2, 0x00000000 },
{ 0x00000000, 0x00000000 } }, { AR5K_PHYERR_CNT2_MASK, 0x00000000 },
{ 0x8128, { AR5K_TSF_THRES, 0x00000000 },
{ 0x00000000, 0x00000000 } }, { 0x8140, 0x800003f9 },
{ 0x812c, { 0x8144, 0x00000000 },
{ 0x00000000, 0x00000000 } }, { AR5K_PHY_AGC, 0x00000000 },
{ 0x8130, { AR5K_PHY_ADC_CTL, 0x0000a000 },
{ 0x00000000, 0x00000000 } }, { 0x983c, 0x00200400 },
{ 0x8134, { AR5K_PHY_GAIN_OFFSET, 0x1284233c },
{ 0x00000000, 0x00000000 } }, { AR5K_PHY_SCR, 0x0000001f },
{ 0x8138, { AR5K_PHY_SLMT, 0x00000080 },
{ 0x00000000, 0x00000000 } }, { AR5K_PHY_SCAL, 0x0000000e },
{ 0x813c, { 0x9958, 0x00081fff },
{ 0x00000000, 0x00000000 } }, { AR5K_PHY_TIMING_7, 0x00000000 },
{ 0x8140, { AR5K_PHY_TIMING_8, 0x02800000 },
{ 0x800003f9, 0x800003f9 } }, { AR5K_PHY_TIMING_11, 0x00000000 },
{ 0x8144, { 0x99dc, 0xfebadbe8 },
{ 0x00000000, 0x00000000 } }, { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },
{ AR5K_PHY_AGC, { 0x99e4, 0xaaaaaaaa },
{ 0x00000000, 0x00000000 } }, { 0x99e8, 0x3c466478 },
{ AR5K_PHY(11), { 0x99ec, 0x000000aa },
{ 0x0000a000, 0x0000a000 } }, { AR5K_PHY_SCLOCK, 0x0000000c },
{ AR5K_PHY(15), { AR5K_PHY_SDELAY, 0x000000ff },
{ 0x00200400, 0x00200400 } }, { AR5K_PHY_SPENDING, 0x00000014 },
{ AR5K_PHY(19), { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },
{ 0x1284233c, 0x1284233c } }, { AR5K_PHY_TXPOWER_RATE3, 0x20202020 },
{ AR5K_PHY_SCR, { AR5K_PHY_TXPOWER_RATE4, 0x20202020 },
{ 0x0000001f, 0x0000001f } }, { 0xa23c, 0x93c889af },
{ AR5K_PHY_SLMT, { AR5K_PHY_FAST_ADC, 0x00000001 },
{ 0x00000080, 0x00000080 } }, { 0xa250, 0x0000a000 },
{ AR5K_PHY_SCAL, { AR5K_PHY_BLUETOOTH, 0x00000000 },
{ 0x0000000e, 0x0000000e } }, { AR5K_PHY_TPC_RG1, 0x0cc75380 },
{ AR5K_PHY(86), { 0xa25c, 0x0f0f0f01 },
{ 0x00081fff, 0x00081fff } }, { 0xa260, 0x5f690f01 },
{ AR5K_PHY(96), { 0xa264, 0x00418a11 },
{ 0x00000000, 0x00000000 } }, { 0xa268, 0x00000000 },
{ AR5K_PHY(97), { AR5K_PHY_TPC_RG5, 0x0c30c166 },
{ 0x02800000, 0x02800000 } }, { 0xa270, 0x00820820 },
{ AR5K_PHY(104), { 0xa274, 0x081a3caa },
{ 0x00000000, 0x00000000 } }, { 0xa278, 0x1ce739ce },
{ AR5K_PHY(119), { 0xa27c, 0x051701ce },
{ 0xfebadbe8, 0xfebadbe8 } }, { 0xa300, 0x16010000 },
{ AR5K_PHY(120), { 0xa304, 0x2c032402 },
{ 0x00000000, 0x00000000 } }, { 0xa308, 0x48433e42 },
{ AR5K_PHY(121), { 0xa30c, 0x5a0f500b },
{ 0xaaaaaaaa, 0xaaaaaaaa } }, { 0xa310, 0x6c4b624a },
{ AR5K_PHY(122), { 0xa314, 0x7e8b748a },
{ 0x3c466478, 0x3c466478 } }, { 0xa318, 0x96cf8ccb },
{ AR5K_PHY(123), { 0xa31c, 0xa34f9d0f },
{ 0x000000aa, 0x000000aa } }, { 0xa320, 0xa7cfa58f },
{ AR5K_PHY_SCLOCK, { 0xa348, 0x3fffffff },
{ 0x0000000c, 0x0000000c } }, { 0xa34c, 0x3fffffff },
{ AR5K_PHY_SDELAY, { 0xa350, 0x3fffffff },
{ 0x000000ff, 0x000000ff } }, { 0xa354, 0x0003ffff },
{ AR5K_PHY_SPENDING, { 0xa358, 0x79a8aa1f },
{ 0x00000014, 0x00000014 } }, { 0xa35c, 0x066c420f },
{ 0xa228, { 0xa360, 0x0f282207 },
{ 0x000009b5, 0x000009b5 } }, { 0xa364, 0x17601685 },
{ AR5K_PHY_TXPOWER_RATE3, { 0xa368, 0x1f801104 },
{ 0x20202020, 0x20202020 } }, { 0xa36c, 0x37a00c03 },
{ AR5K_PHY_TXPOWER_RATE4, { 0xa370, 0x3fc40883 },
{ 0x20202020, 0x20202020 } }, { 0xa374, 0x57c00803 },
{ 0xa23c, { 0xa378, 0x5fd80682 },
{ 0x93c889af, 0x93c889af } }, { 0xa37c, 0x7fe00482 },
{ 0xa24c, { 0xa380, 0x7f3c7bba },
{ 0x00000001, 0x00000001 } }, { 0xa384, 0xf3307ff0 },
{ 0xa250,
{ 0x0000a000, 0x0000a000 } },
{ 0xa254,
{ 0x00000000, 0x00000000 } },
{ 0xa258,
{ 0x0cc75380, 0x0cc75380 } },
{ 0xa25c,
{ 0x0f0f0f01, 0x0f0f0f01 } },
{ 0xa260,
{ 0x5f690f01, 0x5f690f01 } },
{ 0xa264,
{ 0x00418a11, 0x00418a11 } },
{ 0xa268,
{ 0x00000000, 0x00000000 } },
{ 0xa26c,
{ 0x0c30c166, 0x0c30c166 } },
{ 0xa270,
{ 0x00820820, 0x00820820 } },
{ 0xa274,
{ 0x081a3caa, 0x081a3caa } },
{ 0xa278,
{ 0x1ce739ce, 0x1ce739ce } },
{ 0xa27c,
{ 0x051701ce, 0x051701ce } },
{ 0xa300,
{ 0x16010000, 0x16010000 } },
{ 0xa304,
{ 0x2c032402, 0x2c032402 } },
{ 0xa308,
{ 0x48433e42, 0x48433e42 } },
{ 0xa30c,
{ 0x5a0f500b, 0x5a0f500b } },
{ 0xa310,
{ 0x6c4b624a, 0x6c4b624a } },
{ 0xa314,
{ 0x7e8b748a, 0x7e8b748a } },
{ 0xa318,
{ 0x96cf8ccb, 0x96cf8ccb } },
{ 0xa31c,
{ 0xa34f9d0f, 0xa34f9d0f } },
{ 0xa320,
{ 0xa7cfa58f, 0xa7cfa58f } },
{ 0xa348,
{ 0x3fffffff, 0x3fffffff } },
{ 0xa34c,
{ 0x3fffffff, 0x3fffffff } },
{ 0xa350,
{ 0x3fffffff, 0x3fffffff } },
{ 0xa354,
{ 0x0003ffff, 0x0003ffff } },
{ 0xa358,
{ 0x79a8aa1f, 0x79a8aa1f } },
{ 0xa35c,
{ 0x066c420f, 0x066c420f } },
{ 0xa360,
{ 0x0f282207, 0x0f282207 } },
{ 0xa364,
{ 0x17601685, 0x17601685 } },
{ 0xa368,
{ 0x1f801104, 0x1f801104 } },
{ 0xa36c,
{ 0x37a00c03, 0x37a00c03 } },
{ 0xa370,
{ 0x3fc40883, 0x3fc40883 } },
{ 0xa374,
{ 0x57c00803, 0x57c00803 } },
{ 0xa378,
{ 0x5fd80682, 0x5fd80682 } },
{ 0xa37c,
{ 0x7fe00482, 0x7fe00482 } },
{ 0xa380,
{ 0x7f3c7bba, 0x7f3c7bba } },
{ 0xa384,
{ 0xf3307ff0, 0xf3307ff0 } },
}; };
/* /*
...@@ -1560,7 +1297,7 @@ static const struct ath5k_ini rf5111_ini_bbgain[] = { ...@@ -1560,7 +1297,7 @@ static const struct ath5k_ini rf5111_ini_bbgain[] = {
{ AR5K_BB_GAIN(63), 0x00000016 }, { AR5K_BB_GAIN(63), 0x00000016 },
}; };
/* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414) */ /* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414+) */
static const struct ath5k_ini rf5112_ini_bbgain[] = { static const struct ath5k_ini rf5112_ini_bbgain[] = {
{ AR5K_BB_GAIN(0), 0x00000000 }, { AR5K_BB_GAIN(0), 0x00000000 },
{ AR5K_BB_GAIN(1), 0x00000001 }, { AR5K_BB_GAIN(1), 0x00000001 },
...@@ -1691,87 +1428,97 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel) ...@@ -1691,87 +1428,97 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
/* /*
* Write initial settings common for all modes * Write initial settings common for all modes
*/ */
ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini), ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start),
ar5212_ini, change_channel); ar5212_ini_common_start, change_channel);
/* Second set of mode-specific settings */ /* Second set of mode-specific settings */
if (ah->ah_radio == AR5K_RF5111) { switch (ah->ah_radio) {
case AR5K_RF5111:
ath5k_hw_ini_mode_registers(ah, ath5k_hw_ini_mode_registers(ah,
ARRAY_SIZE(ar5212_rf5111_ini_mode_end), ARRAY_SIZE(rf5111_ini_mode_end),
ar5212_rf5111_ini_mode_end, mode); rf5111_ini_mode_end, mode);
ath5k_hw_ini_registers(ah,
ARRAY_SIZE(rf5111_ini_common_end),
rf5111_ini_common_end, change_channel);
/* Baseband gain table */ /* Baseband gain table */
ath5k_hw_ini_registers(ah, ath5k_hw_ini_registers(ah,
ARRAY_SIZE(rf5111_ini_bbgain), ARRAY_SIZE(rf5111_ini_bbgain),
rf5111_ini_bbgain, change_channel); rf5111_ini_bbgain, change_channel);
} else if (ah->ah_radio == AR5K_RF5112) { break;
case AR5K_RF5112:
ath5k_hw_ini_mode_registers(ah, ath5k_hw_ini_mode_registers(ah,
ARRAY_SIZE(ar5212_rf5112_ini_mode_end), ARRAY_SIZE(rf5112_ini_mode_end),
ar5212_rf5112_ini_mode_end, mode); rf5112_ini_mode_end, mode);
ath5k_hw_ini_registers(ah,
ARRAY_SIZE(rf5112_ini_common_end),
rf5112_ini_common_end, change_channel);
ath5k_hw_ini_registers(ah, ath5k_hw_ini_registers(ah,
ARRAY_SIZE(rf5112_ini_bbgain), ARRAY_SIZE(rf5112_ini_bbgain),
rf5112_ini_bbgain, change_channel); rf5112_ini_bbgain, change_channel);
} else if (ah->ah_radio == AR5K_RF5413) { break;
case AR5K_RF5413:
ath5k_hw_ini_mode_registers(ah, ath5k_hw_ini_mode_registers(ah,
ARRAY_SIZE(rf5413_ini_mode_end), ARRAY_SIZE(rf5413_ini_mode_end),
rf5413_ini_mode_end, mode); rf5413_ini_mode_end, mode);
ath5k_hw_ini_registers(ah,
ARRAY_SIZE(rf5413_ini_common_end),
rf5413_ini_common_end, change_channel);
ath5k_hw_ini_registers(ah, ath5k_hw_ini_registers(ah,
ARRAY_SIZE(rf5112_ini_bbgain), ARRAY_SIZE(rf5112_ini_bbgain),
rf5112_ini_bbgain, change_channel); rf5112_ini_bbgain, change_channel);
} else if (ah->ah_radio == AR5K_RF2413) { break;
case AR5K_RF2316:
if (mode < 2) { case AR5K_RF2413:
ATH5K_ERR(ah->ah_sc,
"unsupported channel mode: %d\n", mode);
return -EINVAL;
}
mode = mode - 2;
/* Override a setting from ar5212_ini */
ath5k_hw_reg_write(ah, 0x018830c6, AR5K_PHY(648));
ath5k_hw_ini_mode_registers(ah, ath5k_hw_ini_mode_registers(ah,
ARRAY_SIZE(rf2413_ini_mode_end), ARRAY_SIZE(rf2413_ini_mode_end),
rf2413_ini_mode_end, mode); rf2413_ini_mode_end, mode);
/* Baseband gain table */
ath5k_hw_ini_registers(ah, ath5k_hw_ini_registers(ah,
ARRAY_SIZE(rf5112_ini_bbgain), ARRAY_SIZE(rf2413_ini_common_end),
rf5112_ini_bbgain, change_channel); rf2413_ini_common_end, change_channel);
} else if (ah->ah_radio == AR5K_RF2425) {
if (mode < 2) { /* Override settings from rf2413_ini_common_end */
ATH5K_ERR(ah->ah_sc, if (ah->ah_radio == AR5K_RF2316) {
"unsupported channel mode: %d\n", mode); ath5k_hw_reg_write(ah, 0x00004000,
return -EINVAL; AR5K_PHY_AGC);
ath5k_hw_reg_write(ah, 0x081b7caa,
0xa274);
} }
/* Map b to g */ ath5k_hw_ini_registers(ah,
if (mode == 2) ARRAY_SIZE(rf5112_ini_bbgain),
mode = 0; rf5112_ini_bbgain, change_channel);
else break;
mode = mode - 3; case AR5K_RF2317:
case AR5K_RF2425:
/* Override a setting from ar5212_ini */
ath5k_hw_reg_write(ah, 0x018830c6, AR5K_PHY(648));
ath5k_hw_ini_mode_registers(ah, ath5k_hw_ini_mode_registers(ah,
ARRAY_SIZE(rf2425_ini_mode_end), ARRAY_SIZE(rf2425_ini_mode_end),
rf2425_ini_mode_end, mode); rf2425_ini_mode_end, mode);
/* Baseband gain table */ ath5k_hw_ini_registers(ah,
ARRAY_SIZE(rf2413_ini_common_end),
rf2413_ini_common_end, change_channel);
ath5k_hw_ini_registers(ah, ath5k_hw_ini_registers(ah,
ARRAY_SIZE(rf5112_ini_bbgain), ARRAY_SIZE(rf5112_ini_bbgain),
rf5112_ini_bbgain, change_channel); rf5112_ini_bbgain, change_channel);
break;
default:
return -EINVAL;
} }
......
drivers/net/wireless/ath5k/reg.h
View file @ a406c139
...@@ -811,6 +811,8 @@ ...@@ -811,6 +811,8 @@
/* /*
* DCU transmit filter table 0 (32 entries) * DCU transmit filter table 0 (32 entries)
* each entry contains a 32bit slice of the
* 128bit tx filter for each DCU (4 slices per DCU)
*/ */
#define AR5K_DCU_TX_FILTER_0_BASE 0x1038 #define AR5K_DCU_TX_FILTER_0_BASE 0x1038
#define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64)) #define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))
...@@ -819,7 +821,7 @@ ...@@ -819,7 +821,7 @@
* DCU transmit filter table 1 (16 entries) * DCU transmit filter table 1 (16 entries)
*/ */
#define AR5K_DCU_TX_FILTER_1_BASE 0x103c #define AR5K_DCU_TX_FILTER_1_BASE 0x103c
#define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + ((_n - 32) * 64)) #define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))
/* /*
* DCU clear transmit filter register * DCU clear transmit filter register
...@@ -1447,7 +1449,7 @@ ...@@ -1447,7 +1449,7 @@
AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211) AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211)
/* /*
* Last beacon timestamp register * Last beacon timestamp register (Read Only)
*/ */
#define AR5K_LAST_TSTP 0x8080 #define AR5K_LAST_TSTP 0x8080
...@@ -2219,9 +2221,7 @@ ...@@ -2219,9 +2221,7 @@
#define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 /* Enable low freq sleep */ #define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 /* Enable low freq sleep */
/* /*
* PHY PAPD probe register [5111+ (?)] * PHY PAPD probe register [5111+]
* Is this only present in 5212 ?
* Because it's always 0 in 5211 initialization code
*/ */
#define AR5K_PHY_PAPD_PROBE 0x9930 #define AR5K_PHY_PAPD_PROBE 0x9930
#define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001 #define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001
...@@ -2363,21 +2363,21 @@ ...@@ -2363,21 +2363,21 @@
#define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff #define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff
#define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0 #define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0
#define AR_PHY_TIMING_9 0x9998 #define AR5K_PHY_TIMING_9 0x9998
#define AR_PHY_TIMING_10 0x999c #define AR5K_PHY_TIMING_10 0x999c
#define AR_PHY_TIMING_10_PILOT_MASK_2 0x000fffff #define AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff
#define AR_PHY_TIMING_10_PILOT_MASK_2_S 0 #define AR5K_PHY_TIMING_10_PILOT_MASK_2_S 0
/* /*
* Spur mitigation control * Spur mitigation control
*/ */
#define AR_PHY_TIMING_11 0x99a0 /* Register address */ #define AR5K_PHY_TIMING_11 0x99a0 /* Register address */
#define AR_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */ #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */
#define AR_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0 #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0
#define AR_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */ #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */
#define AR_PHY_TIMING_11_SPUR_FREQ_SD_S 20 #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S 20
#define AR_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */ #define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */
#define AR_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */ #define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */
/* /*
* Gain tables * Gain tables
...@@ -2481,11 +2481,7 @@ ...@@ -2481,11 +2481,7 @@
/* /*
* PHY PCDAC TX power table * PHY PCDAC TX power table
*/ */
#define AR5K_PHY_PCDAC_TXPOWER_BASE_5211 0xa180 #define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180
#define AR5K_PHY_PCDAC_TXPOWER_BASE_2413 0xa280
#define AR5K_PHY_PCDAC_TXPOWER_BASE (ah->ah_radio >= AR5K_RF2413 ? \
AR5K_PHY_PCDAC_TXPOWER_BASE_2413 :\
AR5K_PHY_PCDAC_TXPOWER_BASE_5211)
#define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) #define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2))
/* /*
...@@ -2566,3 +2562,9 @@ ...@@ -2566,3 +2562,9 @@
#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16
#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000
#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22
/*
* PHY PDADC Tx power table
*/
#define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280
#define AR5K_PHY_PDADC_TXPOWER(_n) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))
drivers/net/wireless/ath5k/reset.c
View file @ a406c139
...@@ -457,15 +457,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, ...@@ -457,15 +457,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
* 5210 only comes with RF5110 * 5210 only comes with RF5110
*/ */
if (ah->ah_version != AR5K_AR5210) { if (ah->ah_version != AR5K_AR5210) {
if (ah->ah_radio != AR5K_RF5111 &&
ah->ah_radio != AR5K_RF5112 &&
ah->ah_radio != AR5K_RF5413 &&
ah->ah_radio != AR5K_RF2413 &&
ah->ah_radio != AR5K_RF2425) {
ATH5K_ERR(ah->ah_sc,
"invalid phy radio: %u\n", ah->ah_radio);
return -EINVAL;
}
switch (channel->hw_value & CHANNEL_MODES) { switch (channel->hw_value & CHANNEL_MODES) {
case CHANNEL_A: case CHANNEL_A:
...@@ -510,11 +501,11 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, ...@@ -510,11 +501,11 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
return -EINVAL; return -EINVAL;
} }
/* PHY access enable */
ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
} }
/* PHY access enable */
ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
ret = ath5k_hw_write_initvals(ah, mode, change_channel); ret = ath5k_hw_write_initvals(ah, mode, change_channel);
if (ret) if (ret)
return ret; return ret;
......
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