Commit a7174f97 authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Herbert Xu

crypto: hisilicon - allow compile-testing on x86

To avoid missing arm64 specific warnings that get introduced
in this driver, allow compile-testing on all 64-bit architectures.

The only actual arm64 specific code in this driver is an open-
coded 128 bit MMIO write. On non-arm64 the same can be done
using memcpy_toio. What I also noticed is that the mmio store
(either one) is not endian-safe, this will only work on little-
endian configurations, so I also add a Kconfig dependency on
that, regardless of the architecture.
Finally, a depenndecy on CONFIG_64BIT is needed because of the
writeq().
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 5fd39c4d
...@@ -16,14 +16,15 @@ config CRYPTO_DEV_HISI_SEC ...@@ -16,14 +16,15 @@ config CRYPTO_DEV_HISI_SEC
config CRYPTO_DEV_HISI_QM config CRYPTO_DEV_HISI_QM
tristate tristate
depends on ARM64 && PCI && PCI_MSI depends on ARM64 || COMPILE_TEST
depends on PCI && PCI_MSI
help help
HiSilicon accelerator engines use a common queue management HiSilicon accelerator engines use a common queue management
interface. Specific engine driver may use this module. interface. Specific engine driver may use this module.
config CRYPTO_HISI_SGL config CRYPTO_HISI_SGL
tristate tristate
depends on ARM64 depends on ARM64 || COMPILE_TEST
help help
HiSilicon accelerator engines use a common hardware scatterlist HiSilicon accelerator engines use a common hardware scatterlist
interface for data format. Specific engine driver may use this interface for data format. Specific engine driver may use this
...@@ -31,7 +32,9 @@ config CRYPTO_HISI_SGL ...@@ -31,7 +32,9 @@ config CRYPTO_HISI_SGL
config CRYPTO_DEV_HISI_ZIP config CRYPTO_DEV_HISI_ZIP
tristate "Support for HiSilicon ZIP accelerator" tristate "Support for HiSilicon ZIP accelerator"
depends on ARM64 && PCI && PCI_MSI depends on PCI && PCI_MSI
depends on ARM64 || (COMPILE_TEST && 64BIT)
depends on !CPU_BIG_ENDIAN || COMPILE_TEST
select CRYPTO_DEV_HISI_QM select CRYPTO_DEV_HISI_QM
select CRYPTO_HISI_SGL select CRYPTO_HISI_SGL
select SG_SPLIT select SG_SPLIT
......
...@@ -331,6 +331,12 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src) ...@@ -331,6 +331,12 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src)
void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE; void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
unsigned long tmp0 = 0, tmp1 = 0; unsigned long tmp0 = 0, tmp1 = 0;
if (!IS_ENABLED(CONFIG_ARM64)) {
memcpy_toio(fun_base, src, 16);
wmb();
return;
}
asm volatile("ldp %0, %1, %3\n" asm volatile("ldp %0, %1, %3\n"
"stp %0, %1, %2\n" "stp %0, %1, %2\n"
"dsb sy\n" "dsb sy\n"
......
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