[PATCH] ppc32: add Support for IBM 750FX and 750GX Eval Boards

I've added support for the IBM 750FX and 750GX Eval Boards
(Chestnut/Buckeye).
Signed-off-by: Randy Vinson <rvinson@mvista.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

arch/ppc/Kconfig

@@ -520,6 +520,12 @@ config PCORE
 config POWERPMC250
 	bool "Force-PowerPMC250"
 
+config CHESTNUT
+	bool "IBM 750FX Eval board or 750GX Eval board"
+	help
+	  Select CHESTNUT if configuring an IBM 750FX Eval Board or a
+	  IBM 750GX Eval board.
+
 config SPRUCE
 	bool "IBM-Spruce"
 
@@ -694,7 +700,7 @@ config PPC_GEN550
 	bool
 	depends on SANDPOINT || MCPN765 || SPRUCE || PPLUS || PCORE || \
 		PRPMC750 || K2 || PRPMC800 || LOPEC || \
-		(EV64260 && !SERIAL_MPSC)
+		(EV64260 && !SERIAL_MPSC) || CHESTNUT
 	default y
 
 config FORCE
@@ -712,6 +718,11 @@ config MV64360
 	depends on KATANA
 	default y
 
+config MV64360
+	bool
+	depends on CHESTNUT
+  	default y
+
 config MV64X60
 	bool
 	depends on (GT64260 || MV64360)

arch/ppc/boot/simple/Makefile

@@ -76,6 +76,9 @@ zimageinitrd-$(CONFIG_OCOTEA)		:= zImage.initrd-TREE
          end-$(CONFIG_EV64260)		:= ev64260
    cacheflag-$(CONFIG_EV64260)		:= -include $(clear_L2_L3)
 
+     extra.o-$(CONFIG_CHESTNUT)		:= misc-chestnut.o
+         end-$(CONFIG_CHESTNUT)		:= chestnut
+
       zimage-$(CONFIG_GEMINI)		:= zImage-STRIPELF
 zimageinitrd-$(CONFIG_GEMINI)		:= zImage.initrd-STRIPELF
          end-$(CONFIG_GEMINI)		:= gemini

arch/ppc/boot/simple/misc-chestnut.S

+/*
+ * arch/ppc/boot/simple/misc-chestnut.S
+ *
+ * Setup for the IBM Chestnut (ibm-750fxgx_eval)
+ *
+ * Author: <source@mvista.com>
+ *
+ * <2004> (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+
+#include <asm/ppc_asm.h>
+#include <asm/mv64x60_defs.h>
+#include <platforms/chestnut.h>
+
+	.globl	mv64x60_board_init
+mv64x60_board_init:
+	/*
+	 * move UART to 0xffc00000
+	 */
+
+	li      r23,16
+
+	addis	r25,0,CONFIG_MV64X60_BASE@h
+	ori     r25,r25,MV64x60_CPU2DEV_2_BASE
+	addis   r26,0,CHESTNUT_UART_BASE@h
+	srw     r26,r26,r23
+	stwbrx  r26,0,(r25)
+	sync
+
+	addis	r25,0,CONFIG_MV64X60_BASE@h
+	ori     r25,r25,MV64x60_CPU2DEV_2_SIZE
+	addis   r26,0,0x00100000@h
+	srw     r26,r26,r23
+	stwbrx  r26,0,(r25)
+	sync
+
+	blr

arch/ppc/configs/chestnut_defconfig

+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.10-rc2
+# Tue Dec  7 16:02:09 2004
+#
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_HAVE_DEC_LOCK=y
+CONFIG_PPC=y
+CONFIG_PPC32=y
+CONFIG_GENERIC_NVRAM=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Processor
+#
+CONFIG_6xx=y
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_POWER3 is not set
+# CONFIG_POWER4 is not set
+# CONFIG_8xx is not set
+# CONFIG_E500 is not set
+CONFIG_ALTIVEC=y
+# CONFIG_TAU is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_PPC_GEN550=y
+CONFIG_PPC_STD_MMU=y
+CONFIG_NOT_COHERENT_CACHE=y
+
+#
+# Platform options
+#
+# CONFIG_PPC_MULTIPLATFORM is not set
+# CONFIG_APUS is not set
+# CONFIG_WILLOW is not set
+# CONFIG_PCORE is not set
+# CONFIG_POWERPMC250 is not set
+CONFIG_CHESTNUT=y
+# CONFIG_SPRUCE is not set
+# CONFIG_EV64260 is not set
+# CONFIG_LOPEC is not set
+# CONFIG_MCPN765 is not set
+# CONFIG_MVME5100 is not set
+# CONFIG_PPLUS is not set
+# CONFIG_PRPMC750 is not set
+# CONFIG_PRPMC800 is not set
+# CONFIG_SANDPOINT is not set
+# CONFIG_ADIR is not set
+# CONFIG_K2 is not set
+# CONFIG_PAL4 is not set
+# CONFIG_GEMINI is not set
+# CONFIG_EST8260 is not set
+# CONFIG_SBC82xx is not set
+# CONFIG_SBS8260 is not set
+# CONFIG_RPX8260 is not set
+# CONFIG_TQM8260 is not set
+# CONFIG_ADS8272 is not set
+# CONFIG_LITE5200 is not set
+CONFIG_MV64360=y
+CONFIG_MV64X60=y
+
+#
+# Set bridge options
+#
+CONFIG_MV64X60_BASE=0xf1000000
+CONFIG_MV64X60_NEW_BASE=0xf1000000
+# CONFIG_SMP is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS0,115200 ip=on"
+
+#
+# Bus options
+#
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_PCI_NAMES=y
+
+#
+# Advanced setup
+#
+CONFIG_ADVANCED_OPTIONS=y
+CONFIG_HIGHMEM_START=0xfe000000
+# CONFIG_LOWMEM_SIZE_BOOL is not set
+CONFIG_LOWMEM_SIZE=0x30000000
+# CONFIG_KERNEL_START_BOOL is not set
+CONFIG_KERNEL_START=0xc0000000
+# CONFIG_TASK_SIZE_BOOL is not set
+CONFIG_TASK_SIZE=0x80000000
+# CONFIG_CONSISTENT_START_BOOL is not set
+CONFIG_CONSISTENT_START=0xff100000
+# CONFIG_CONSISTENT_SIZE_BOOL is not set
+CONFIG_CONSISTENT_SIZE=0x00200000
+# CONFIG_BOOT_LOAD_BOOL is not set
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_CHESTNUT=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_LBD is not set
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+CONFIG_NET_TULIP=y
+# CONFIG_DE2104X is not set
+CONFIG_TULIP=y
+# CONFIG_TULIP_MWI is not set
+CONFIG_TULIP_MMIO=y
+# CONFIG_TULIP_NAPI is not set
+# CONFIG_DE4X5 is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_DM9102 is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+# CONFIG_EEPRO100 is not set
+CONFIG_E100=y
+# CONFIG_E100_NAPI is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_SERIO is not set
+# CONFIG_SERIO_I8042 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+# CONFIG_DEVFS_DEBUG is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SERIAL_TEXT_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set

arch/ppc/platforms/Makefile

@@ -25,6 +25,7 @@ obj-$(CONFIG_PQ2ADS)		+= pq2ads.o
 obj-$(CONFIG_TQM8260)		+= tqm8260_setup.o
 obj-$(CONFIG_CPCI690)		+= cpci690.o
 obj-$(CONFIG_EV64260)		+= ev64260.o
+obj-$(CONFIG_CHESTNUT)		+= chestnut.o
 obj-$(CONFIG_GEMINI)		+= gemini_pci.o gemini_setup.o gemini_prom.o
 obj-$(CONFIG_K2)		+= k2.o
 obj-$(CONFIG_LOPEC)		+= lopec.o

arch/ppc/platforms/chestnut.c

+/*
+ * arch/ppc/platforms/chestnut.c
+ *
+ * Board setup routines for IBM Chestnut
+ *
+ * Author: <source@mvista.com>
+ *
+ * <2004> (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/blkdev.h>
+#include <linux/console.h>
+#include <linux/root_dev.h>
+#include <linux/initrd.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/ide.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/time.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <linux/irq.h>
+#include <asm/hw_irq.h>
+#include <asm/machdep.h>
+#include <asm/kgdb.h>
+#include <asm/bootinfo.h>
+#include <asm/mv64x60.h>
+#include <platforms/chestnut.h>
+
+static u32 boot_base; /* Virtual addr of 8bit boot */
+static u32 cpld_base; /* Virtual addr of CPLD Regs */
+
+static mv64x60_handle_t	bh;
+
+extern void gen550_progress(char *, unsigned short);
+extern void gen550_init(int, struct uart_port *);
+extern void mv64360_pcibios_fixup(mv64x60_handle_t *bh);
+
+#define BIT(x) (1<<x)
+#define CHESTNUT_PRESERVE_MASK (BIT(MV64x60_CPU2DEV_0_WIN) | \
+				BIT(MV64x60_CPU2DEV_1_WIN) | \
+				BIT(MV64x60_CPU2DEV_2_WIN) | \
+				BIT(MV64x60_CPU2DEV_3_WIN) | \
+				BIT(MV64x60_CPU2BOOT_WIN))
+/**************************************************************************
+ * FUNCTION: chestnut_calibrate_decr
+ *
+ * DESCRIPTION: initialize decrementer interrupt frequency (used as system
+ *              timer)
+ *
+ ****/
+static void __init
+chestnut_calibrate_decr(void){
+	ulong freq;
+
+	freq = CHESTNUT_BUS_SPEED / 4;
+
+	printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
+		freq/1000000, freq%1000000);
+
+	tb_ticks_per_jiffy = freq / HZ;
+	tb_to_us = mulhwu_scale_factor(freq, 1000000);
+
+	return;
+}
+
+static int
+chestnut_show_cpuinfo(struct seq_file *m)
+{
+	seq_printf(m, "vendor\t\t: IBM\n");
+	seq_printf(m, "machine\t\t: 750FX/GX Eval Board (Chestnut/Buckeye)\n");
+
+	return 0;
+}
+
+/**************************************************************************
+ * FUNCTION: chestnut_find_end_of_memory
+ *
+ * DESCRIPTION: ppc_md memory size callback
+ *
+ ****/
+unsigned long __init
+chestnut_find_end_of_memory(void)
+{
+   	static int  mem_size = 0;
+
+   	if (mem_size == 0) {
+      		mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
+				MV64x60_TYPE_MV64460);
+   	}
+   	return(mem_size);
+}
+
+#if defined(CONFIG_SERIAL_8250)
+static void __init
+chestnut_early_serial_map(void)
+{
+	struct uart_port port;
+
+	/* Setup serial port access */
+	memset(&port, 0, sizeof(port));
+	port.uartclk = BASE_BAUD * 16;
+	port.irq = UART0_INT;
+	port.flags = STD_COM_FLAGS | UPF_IOREMAP;
+	port.iotype = SERIAL_IO_MEM;
+	port.mapbase = CHESTNUT_UART0_IO_BASE;
+	port.regshift = 0;
+
+	if (early_serial_setup(&port) != 0)
+		printk("Early serial init of port 0 failed\n");
+
+	/* Assume early_serial_setup() doesn't modify serial_req */
+	port.line = 1;
+	port.irq = UART1_INT;
+	port.mapbase = CHESTNUT_UART1_IO_BASE;
+
+	if (early_serial_setup(&port) != 0)
+		printk("Early serial init of port 1 failed\n");
+}
+#endif
+
+/**************************************************************************
+ * FUNCTION: chestnut_map_irq
+ *
+ * DESCRIPTION: 0 return since PCI IRQs not needed
+ *
+ ****/
+static int __init
+chestnut_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+	static char pci_irq_table[][4] = {
+		{CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ,
+		 CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ},
+		{CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ,
+		 CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ},
+		{CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ,
+		 CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ},
+		{CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ,
+		 CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ},
+	};
+	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
+
+	return (PCI_IRQ_TABLE_LOOKUP);
+}
+
+
+/**************************************************************************
+ * FUNCTION: chestnut_setup_bridge
+ *
+ * DESCRIPTION: initalize board-specific settings on the MV64360
+ *
+ ****/
+static void __init
+chestnut_setup_bridge(void)
+{
+	struct mv64x60_setup_info	si;
+	int i;
+
+   	if ( ppc_md.progress )
+		ppc_md.progress("chestnut_setup_bridge: enter", 0);
+
+	memset(&si, 0, sizeof(si));
+
+	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
+
+	/* setup only PCI bus 0 (bus 1 not used) */
+	si.pci_0.enable_bus = 1;
+	si.pci_0.pci_io.cpu_base = CHESTNUT_PCI0_IO_PROC_ADDR;
+	si.pci_0.pci_io.pci_base_hi = 0;
+	si.pci_0.pci_io.pci_base_lo = CHESTNUT_PCI0_IO_PCI_ADDR;
+	si.pci_0.pci_io.size = CHESTNUT_PCI0_IO_SIZE;
+	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
+	si.pci_0.pci_mem[0].cpu_base = CHESTNUT_PCI0_MEM_PROC_ADDR;
+	si.pci_0.pci_mem[0].pci_base_hi = CHESTNUT_PCI0_MEM_PCI_HI_ADDR;
+	si.pci_0.pci_mem[0].pci_base_lo = CHESTNUT_PCI0_MEM_PCI_LO_ADDR;
+	si.pci_0.pci_mem[0].size = CHESTNUT_PCI0_MEM_SIZE;
+	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
+	si.pci_0.pci_cmd_bits = 0;
+	si.pci_0.latency_timer = 0x80;
+
+	si.window_preserve_mask_32_lo = CHESTNUT_PRESERVE_MASK;
+
+	for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
+		si.cpu_prot_options[i] = 0;
+#ifdef CONFIG_NOT_CACHE_COHERENT
+		si.cpu_snoop_options[i] = MV64360_CPU_SNOOP_NONE;
+#else
+		si.cpu_snoop_options[i] = MV64360_CPU_SNOOP_WB; /* risky */
+#endif
+		si.pci_0.acc_cntl_options[i] =
+#ifdef CONFIG_NOT_CACHE_COHERENT
+			MV64360_PCI_ACC_CNTL_SNOOP_NONE |
+#else
+			MV64360_PCI_ACC_CNTL_SNOOP_WB | /* risky */
+#endif
+			MV64360_PCI_ACC_CNTL_SWAP_NONE |
+			MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
+			MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
+	}
+
+   	/* Lookup host bridge - on CPU 0 - no SMP support */
+   	if (mv64x60_init(&bh, &si)) {
+        	printk("\n\nPCI Bridge initialization failed!\n");
+   	}
+
+	pci_dram_offset = 0;
+	ppc_md.pci_swizzle = common_swizzle;
+	ppc_md.pci_map_irq = chestnut_map_irq;
+	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
+
+	mv64x60_set_bus(&bh, 0, 0);
+	bh.hose_a->first_busno = 0;
+	bh.hose_a->last_busno = 0xff;
+	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
+
+}
+
+void __init
+chestnut_setup_peripherals(void)
+{
+
+   	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
+			CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0);
+
+	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
+			CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0);
+	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
+			CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0);
+
+	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
+			CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0);
+	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
+			CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0);
+   	/* Set up window for internal sram (256KByte insize) */
+   	mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
+			CHESTNUT_INTERNAL_SRAM_BASE,
+			CHESTNUT_INTERNAL_SRAM_SIZE, 0);
+
+	boot_base = (u32)ioremap(CHESTNUT_BOOT_8BIT_BASE,
+				CHESTNUT_BOOT_8BIT_SIZE);
+	cpld_base = (u32)ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
+
+   	/*
+    	 * Configure internal SRAM -
+    	 * Cache coherent write back, incase
+	 *      CONFIG_MV64360_SRAM_CACHE_COHERENT set
+    	 * Parity enabled.
+    	 * Parity error propagation
+    	 * Arbitration not parked for CPU only
+    	 * Other bits are reserved.
+    	 */
+#ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
+   	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
+#else
+   	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
+#endif
+
+   	/*
+    	 * Setting the SRAM to 0. Note that this generates parity errors on
+	 * internal data path in SRAM since it's first time accessing it
+	 * while after reset it's not configured
+    	*/
+   	memset((void *)CHESTNUT_INTERNAL_SRAM_BASE, 0, CHESTNUT_INTERNAL_SRAM_SIZE);
+	/*
+	 * Configure MPP pins for PCI DMA
+	 *
+	 * PCI Slot	GNT pin		REQ pin
+	 *	0	MPP16		MPP17
+	 *	1	MPP18		MPP19
+	 *	2	MPP20		MPP21
+	 *	3	MPP22		MPP23
+	 */
+	mv64x60_write(&bh, MV64x60_MPP_CNTL_2,
+			(0x1 << 0)  |	/* MPPSel16 PCI0_GNT[0] */
+			(0x1 << 4)  |	/* MPPSel17 PCI0_REQ[0] */
+			(0x1 << 8)  |	/* MPPSel18 PCI0_GNT[1] */
+			(0x1 << 12) |	/* MPPSel19 PCI0_REQ[1] */
+			(0x1 << 16) |	/* MPPSel20 PCI0_GNT[2] */
+			(0x1 << 20) |	/* MPPSel21 PCI0_REQ[2] */
+			(0x1 << 24) |	/* MPPSel22 PCI0_GNT[3] */
+			(0x1 << 28));	/* MPPSel23 PCI0_REQ[3] */
+	/*
+	 * Set unused MPP pins for output, as per schematic note
+	 *
+	 * Unused Pins: MPP01, MPP02, MPP04, MPP05, MPP06
+	 *		MPP09, MPP10, MPP13, MPP14, MPP15
+	 */
+	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_0,
+			(0xf << 4)  |	/* MPPSel01 GPIO[1] */
+			(0xf << 8)  |	/* MPPSel02 GPIO[2] */
+			(0xf << 16) |	/* MPPSel04 GPIO[4] */
+			(0xf << 20) |	/* MPPSel05 GPIO[5] */
+			(0xf << 24));	/* MPPSel06 GPIO[6] */
+	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1,
+			(0xf << 4)  |	/* MPPSel09 GPIO[9] */
+			(0xf << 8)  |	/* MPPSel10 GPIO[10] */
+			(0xf << 20) |	/* MPPSel13 GPIO[13] */
+			(0xf << 24) |	/* MPPSel14 GPIO[14] */
+			(0xf << 28));	/* MPPSel15 GPIO[15] */
+	mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL,
+			BIT(1)  | BIT(2)  | BIT(4)  | BIT(5)  | BIT(6)  |
+			BIT(9)  | BIT(10) | BIT(13) | BIT(14) | BIT(15)); /* Output */
+
+   	/*
+    	 * Configure the following MPP pins to indicate a level
+    	 * triggered interrupt
+    	 *
+       	 * MPP24 - Board Reset (just map the MPP & GPP for chestnut_reset)
+       	 * MPP25 - UART A  (high)
+       	 * MPP26 - UART B  (high)
+	 * MPP28 - PCI Slot 3 (low)
+	 * MPP29 - PCI Slot 2 (low)
+	 * MPP30 - PCI Slot 1 (low)
+	 * MPP31 - PCI Slot 0 (low)
+    	 */
+        mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3,
+                        BIT(3) | BIT(2) | BIT(1) | BIT(0)	 | /* MPP 24 */
+                        BIT(7) | BIT(6) | BIT(5) | BIT(4)	 | /* MPP 25 */
+                        BIT(11) | BIT(10) | BIT(9) | BIT(8)	 | /* MPP 26 */
+			BIT(19) | BIT(18) | BIT(17) | BIT(16)	 | /* MPP 28 */
+			BIT(23) | BIT(22) | BIT(21) | BIT(20)	 | /* MPP 29 */
+			BIT(27) | BIT(26) | BIT(25) | BIT(24)	 | /* MPP 30 */
+			BIT(31) | BIT(30) | BIT(29) | BIT(28));    /* MPP 31 */
+
+   	/*
+	 * Define GPP 25 (high), 26 (high), 28 (low), 29 (low), 30 (low),
+	 * 31 (low) interrupt polarity input signal and level triggered
+    	 */
+   	mv64x60_clr_bits(&bh, MV64x60_GPP_LEVEL_CNTL, BIT(25) | BIT(26));
+   	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL,
+			BIT(28) | BIT(29) | BIT(30) | BIT(31));
+   	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL,
+			BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
+			BIT(31));
+
+   	/* Config GPP interrupt controller to respond to level trigger */
+   	mv64x60_set_bits(&bh, MV64360_COMM_ARBITER_CNTL, BIT(10));
+
+   	/*
+    	 * Dismiss and then enable interrupt on GPP interrupt cause for CPU #0
+    	 */
+   	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE,
+			~(BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
+			  BIT(31)));
+   	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK,
+			BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
+			BIT(31));
+
+   	/*
+    	 * Dismiss and then enable interrupt on CPU #0 high cause register
+    	 * BIT27 summarizes GPP interrupts 24-31
+    	*/
+   	mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27));
+
+   	if (ppc_md.progress)
+		ppc_md.progress("chestnut_setup_bridge: exit", 0);
+}
+
+/**************************************************************************
+ * FUNCTION: chestnut_setup_arch
+ *
+ * DESCRIPTION: ppc_md machine configuration callback
+ *
+ ****/
+static void __init
+chestnut_setup_arch(void)
+{
+	if (ppc_md.progress)
+      		ppc_md.progress("chestnut_setup_arch: enter", 0);
+
+	/* init to some ~sane value until calibrate_delay() runs */
+	loops_per_jiffy = 50000000 / HZ;
+
+   	/* if the time base value is greater than bus freq/4 (the TB and
+    	* decrementer tick rate) + signed integer rollover value, we
+    	* can spend a fair amount of time waiting for the rollover to
+    	* happen.  To get around this, initialize the time base register
+    	* to a "safe" value.
+    	*/
+   	set_tb(0, 0);
+
+#ifdef CONFIG_BLK_DEV_INITRD
+	if (initrd_start)
+		ROOT_DEV = Root_RAM0;
+	else
+#endif
+#ifdef CONFIG_ROOT_NFS
+		ROOT_DEV = Root_NFS;
+#else
+		ROOT_DEV = Root_SDA2;
+#endif
+
+   	/*
+    	* Set up the L2CR register.
+    	*/
+ 	_set_L2CR(_get_L2CR() | L2CR_L2E);
+
+	chestnut_setup_bridge();
+	chestnut_setup_peripherals();
+
+#ifdef CONFIG_DUMMY_CONSOLE
+	conswitchp = &dummy_con;
+#endif
+
+#if defined(CONFIG_SERIAL_8250)
+	chestnut_early_serial_map();
+#endif
+
+	/* Identify the system */
+	printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n");
+	printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc. (source@mvista.com)\n");
+
+	if (ppc_md.progress)
+      		ppc_md.progress("chestnut_setup_arch: exit", 0);
+
+	return;
+}
+
+/**************************************************************************
+ * FUNCTION: chestnut_restart
+ *
+ * DESCRIPTION: ppc_md machine reset callback
+ *              reset the board via the CPLD command register
+ *
+ ****/
+static void
+chestnut_restart(char *cmd)
+{
+	volatile ulong i = 10000000;
+
+	local_irq_disable();
+
+        /*
+         * Set CPLD Reg 3 bit 0 to 1 to allow MPP signals on reset to work
+         *
+         * MPP24 - board reset
+         */
+   	writeb(0x1, (void __iomem *)(cpld_base+3));
+
+	/* GPP pin tied to MPP earlier */
+        mv64x60_set_bits(&bh, MV64x60_GPP_VALUE_SET, BIT(24));
+
+   	while (i-- > 0);
+   	panic("restart failed\n");
+}
+
+static void
+chestnut_halt(void)
+{
+	local_irq_disable();
+	for (;;);
+	/* NOTREACHED */
+}
+
+static void
+chestnut_power_off(void)
+{
+	chestnut_halt();
+	/* NOTREACHED */
+}
+
+#define SET_PCI_COMMAND_INVALIDATE
+#ifdef SET_PCI_COMMAND_INVALIDATE
+/*
+ * Dave Wilhardt found that PCI_COMMAND_INVALIDATE must
+ * be set for each device if you are using cache coherency.
+ */
+static void __init
+set_pci_command_invalidate(void)
+{
+	struct pci_dev *dev = NULL;
+	u16 val;
+
+	while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
+		pci_read_config_word(dev, PCI_COMMAND, &val);
+		val |= PCI_COMMAND_INVALIDATE;
+		pci_write_config_word(dev, PCI_COMMAND, val);
+
+		pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
+				      L1_CACHE_LINE_SIZE >> 2);
+	}
+}
+#endif
+
+static void __init
+chestnut_pci_fixups(void)
+{
+#ifdef SET_PCI_COMMAND_INVALIDATE
+	set_pci_command_invalidate();
+#endif
+}
+
+/**************************************************************************
+ * FUNCTION: chestnut_map_io
+ *
+ * DESCRIPTION: configure fixed memory-mapped IO
+ *
+ ****/
+static void __init
+chestnut_map_io(void)
+{
+#ifdef CONFIG_MV64360_SRAM_CACHEABLE
+   	io_block_mapping(CHESTNUT_INTERNAL_SRAM_BASE,
+       			CHESTNUT_INTERNAL_SRAM_BASE,
+       			CHESTNUT_INTERNAL_SRAM_SIZE,
+       			_PAGE_KERNEL | _PAGE_GUARDED);
+#else
+#ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
+   	io_block_mapping(CHESTNUT_INTERNAL_SRAM_BASE,
+       			CHESTNUT_INTERNAL_SRAM_BASE,
+       			CHESTNUT_INTERNAL_SRAM_SIZE,
+       			_PAGE_KERNEL | _PAGE_GUARDED | _PAGE_COHERENT);
+#else
+   	io_block_mapping(CHESTNUT_INTERNAL_SRAM_BASE,
+       			CHESTNUT_INTERNAL_SRAM_BASE,
+       			CHESTNUT_INTERNAL_SRAM_SIZE,
+       			_PAGE_IO);
+#endif /* !CONFIG_MV64360_SRAM_CACHE_COHERENT */
+#endif /* !CONFIG_MV64360_SRAM_CACHEABLE */
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+	io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000, _PAGE_IO);
+#endif
+}
+
+/**************************************************************************
+ * FUNCTION: chestnut_set_bat
+ *
+ * DESCRIPTION: configures a (temporary) bat mapping for early access to
+ *              device I/O
+ *
+ ****/
+static __inline__ void
+chestnut_set_bat(void)
+{
+        mb();
+        mtspr(DBAT3U, 0xf0001ffe);
+        mtspr(DBAT3L, 0xf000002a);
+        mb();
+
+	return;
+}
+
+/**************************************************************************
+ * FUNCTION: platform_init
+ *
+ * DESCRIPTION: main entry point for configuring board-specific machine
+ *              callbacks
+ *
+ ****/
+void __init
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+	      unsigned long r6, unsigned long r7)
+{
+	parse_bootinfo(find_bootinfo());
+
+        /* Copy the kernel command line arguments to a safe place. */
+
+        if (r6) {
+                *(char *) (r7 + KERNELBASE) = 0;
+                strcpy(cmd_line, (char *) (r6 + KERNELBASE));
+        }
+
+	isa_mem_base = 0;
+
+	ppc_md.setup_arch = chestnut_setup_arch;
+	ppc_md.show_cpuinfo = chestnut_show_cpuinfo;
+	ppc_md.irq_canonicalize = NULL;
+	ppc_md.init_IRQ = mv64360_init_irq;
+	ppc_md.get_irq = mv64360_get_irq;
+	ppc_md.init = NULL;
+
+	ppc_md.find_end_of_memory = chestnut_find_end_of_memory;
+	ppc_md.setup_io_mappings  = chestnut_map_io;
+	ppc_md.pcibios_fixup = chestnut_pci_fixups;
+
+	ppc_md.restart = chestnut_restart;
+   	ppc_md.power_off = chestnut_power_off;
+   	ppc_md.halt = chestnut_halt;
+
+	ppc_md.time_init = NULL;
+	ppc_md.set_rtc_time = NULL;
+	ppc_md.get_rtc_time = NULL;
+	ppc_md.calibrate_decr = chestnut_calibrate_decr;
+
+	ppc_md.nvram_read_val = NULL;
+	ppc_md.nvram_write_val = NULL;
+
+	ppc_md.heartbeat = NULL;
+
+	ppc_md.pcibios_fixup = chestnut_pci_fixups;
+
+	bh.p_base = CONFIG_MV64X60_NEW_BASE;
+
+	chestnut_set_bat();
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG)
+	ppc_md.progress = gen550_progress;
+#endif
+#if defined(CONFIG_KGDB)
+	ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
+#endif
+
+	if (ppc_md.progress)
+                ppc_md.progress("chestnut_init(): exit", 0);
+
+        return;
+}

arch/ppc/platforms/chestnut.h

+/*
+ * arch/ppc/platforms/chestnut.h
+ *
+ * Definitions for IBM 750FXGX Eval (Chestnut)
+ *
+ * Author: <source@mvista.com>
+ *
+ * Based on Artesyn Katana code done by Tim Montgomery <timm@artesyncp.com>
+ * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
+ * Based on code done by Mark A. Greer <mgreer@mvista.com>
+ *
+ * <2004> (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+/*
+ * This is the CPU physical memory map (windows must be at least 1MB and start
+ * on a boundary that is a multiple of the window size):
+ *
+ * Seems on the IBM 750FXGX Eval board, the MV64460 Registers can be in
+ * only 2 places per switch U17 0x14000000 or 0xf1000000 easily - chose to
+ * implement at 0xf1000000 only at this time
+ *
+ *    0xfff00000-0xffffffff      - 8 Flash
+ *    0xffd00000-0xffd00004      - CPLD
+ *    0xffc00000-0xffc0000f      - UART
+ *    0xffb00000-0xffb07fff      - FRAM
+ *    0xffa00000-0xffafffff      - *** HOLE ***
+ *    0xff900000-0xff9fffff      - MV64460 Integrated SRAM
+ *    0xfe000000-0xff8fffff      - *** HOLE ***
+ *    0xfc000000-0xfdffffff      - 32bit Flash
+ *    0xf1010000-0xfbffffff      - *** HOLE ***
+ *    0xf1000000-0xf100ffff      - MV64460 Registers
+ */
+
+#ifndef __PPC_PLATFORMS_CHESTNUT_H__
+#define __PPC_PLATFORMS_CHESTNUT_H__
+
+#define CHESTNUT_BOOT_8BIT_BASE			0xfff00000
+#define CHESTNUT_BOOT_8BIT_SIZE_ACTUAL		(1024*1024)
+#define CHESTNUT_BOOT_SRAM_BASE			0xffe00000
+#define CHESTNUT_BOOT_SRAM_SIZE_ACTUAL		(1024*1024)
+#define CHESTNUT_CPLD_BASE			0xffd00000
+#define CHESTNUT_CPLD_SIZE_ACTUAL		5
+#define CHESTNUT_CPLD_REG3			(CHESTNUT_CPLD_BASE+3)
+#define CHESTNUT_UART_BASE			0xffc00000
+#define CHESTNUT_UART_SIZE_ACTUAL		16
+#define CHESTNUT_FRAM_BASE			0xffb00000
+#define CHESTNUT_FRAM_SIZE_ACTUAL		(32*1024)
+#define CHESTNUT_BRIDGE_REG_BASE		0xf1000000
+#define CHESTNUT_INTERNAL_SRAM_BASE		0xff900000
+#define CHESTNUT_INTERNAL_SRAM_SIZE_ACTUAL	(256*1024)
+#define CHESTNUT_32BIT_BASE			0xfc000000
+#define CHESTNUT_32BIT_SIZE			(32*1024*1024)
+
+#define CHESTNUT_BOOT_8BIT_SIZE		max(MV64360_WINDOW_SIZE_MIN, \
+					CHESTNUT_BOOT_8BIT_SIZE_ACTUAL)
+#define CHESTNUT_BOOT_SRAM_SIZE		max(MV64360_WINDOW_SIZE_MIN, \
+					CHESTNUT_BOOT_SRAM_SIZE_ACTUAL)
+#define CHESTNUT_CPLD_SIZE		max(MV64360_WINDOW_SIZE_MIN, \
+					CHESTNUT_CPLD_SIZE_ACTUAL)
+#define CHESTNUT_UART_SIZE		max(MV64360_WINDOW_SIZE_MIN, \
+					CHESTNUT_UART_SIZE_ACTUAL)
+#define CHESTNUT_FRAM_SIZE		max(MV64360_WINDOW_SIZE_MIN, \
+					CHESTNUT_FRAM_SIZE_ACTUAL)
+#define CHESTNUT_INTERNAL_SRAM_SIZE	max(MV64360_WINDOW_SIZE_MIN, \
+					CHESTNUT_INTERNAL_SRAM_SIZE_ACTUAL)
+
+#define CHESTNUT_BUS_SPEED		200000000
+#define CHESTNUT_PIBS_DATABASE		0xf0000 /* from PIBS src code */
+
+#define MV64360_ETH_PORT_SERIAL_CONTROL_REG_PORT0 	0x243c
+#define MV64360_ETH_PORT_SERIAL_CONTROL_REG_PORT1 	0x283c
+
+/*
+ * PCI windows
+ */
+
+#define CHESTNUT_PCI0_MEM_PROC_ADDR	0x80000000
+#define CHESTNUT_PCI0_MEM_PCI_HI_ADDR	0x00000000
+#define CHESTNUT_PCI0_MEM_PCI_LO_ADDR	0x80000000
+#define CHESTNUT_PCI0_MEM_SIZE		0x10000000
+#define CHESTNUT_PCI0_IO_PROC_ADDR	0xa0000000
+#define CHESTNUT_PCI0_IO_PCI_ADDR	0x00000000
+#define CHESTNUT_PCI0_IO_SIZE		0x01000000
+
+/*
+ * Board-specific IRQ info
+ */
+#define CHESTNUT_PCI_SLOT0_IRQ	64+31
+#define CHESTNUT_PCI_SLOT1_IRQ	64+30
+#define CHESTNUT_PCI_SLOT2_IRQ	64+29
+#define CHESTNUT_PCI_SLOT3_IRQ	64+28
+
+/* serial port definitions */
+#define CHESTNUT_UART0_IO_BASE  CHESTNUT_UART_BASE+8
+#define CHESTNUT_UART1_IO_BASE  CHESTNUT_UART_BASE
+
+#define UART0_INT           	64+25
+#define UART1_INT        	64+26
+
+#ifdef CONFIG_SERIAL_MANY_PORTS
+#define RS_TABLE_SIZE  64
+#else
+#define RS_TABLE_SIZE  2
+#endif
+
+/* Rate for the 3.6864 Mhz clock for the onboard serial chip */
+#define BASE_BAUD 		( 3686400 / 16 )
+
+#ifdef CONFIG_SERIAL_DETECT_IRQ
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
+#else
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
+#endif
+
+#define STD_UART_OP(num)						\
+        { 0, BASE_BAUD, 0, UART##num##_INT, STD_COM_FLAGS,		\
+                iomem_base: (u8 *)CHESTNUT_UART##num##_IO_BASE,	\
+		io_type: SERIAL_IO_MEM},
+
+#define SERIAL_PORT_DFNS        \
+        STD_UART_OP(0)          \
+        STD_UART_OP(1)
+
+#endif /* __PPC_PLATFORMS_CHESTNUT_H__ */

arch/ppc/syslib/Makefile

@@ -42,6 +42,7 @@ obj-$(CONFIG_ADIR)		+= i8259.o indirect_pci.o pci_auto.o \
 obj-$(CONFIG_CPCI690)		+= todc_time.o pci_auto.o
 obj-$(CONFIG_EBONY)		+= indirect_pci.o pci_auto.o todc_time.o
 obj-$(CONFIG_EV64260)		+= todc_time.o pci_auto.o
+obj-$(CONFIG_CHESTNUT)		+= mv64360_pic.o pci_auto.o
 obj-$(CONFIG_GEMINI)		+= open_pic.o indirect_pci.o
 obj-$(CONFIG_GT64260)		+= gt64260_pic.o
 obj-$(CONFIG_K2)		+= i8259.o indirect_pci.o todc_time.o \

drivers/mtd/maps/Kconfig

@@ -397,6 +397,14 @@ config MTD_REDWOOD
 	  Redwood board. If you have one of these boards and would like to
 	  use the flash chips on it, say 'Y'.
 
+config MTD_CHESTNUT
+	tristate "CFI Flash devices mapped on IBM 750FX or IBM 750GX Eval Boards"
+	depends on MTD_CFI && PPC32 && CHESTNUT
+	help
+	  This enables access routines for the flash chips on the IBM
+	  750FX and 750GX Eval Boards. If you have one of these boards and
+	  would like to use the flash chips on it, say 'Y'
+
 config MTD_CSTM_MIPS_IXX
 	tristate "Flash chip mapping on ITE QED-4N-S01B, Globespan IVR or custom board"
 	depends on MIPS && MTD_CFI && MTD_JEDECPROBE && MTD_PARTITIONS

drivers/mtd/maps/Makefile

@@ -54,6 +54,7 @@ obj-$(CONFIG_MTD_EDB7312)	+= edb7312.o
 obj-$(CONFIG_MTD_IMPA7)		+= impa7.o
 obj-$(CONFIG_MTD_FORTUNET)	+= fortunet.o
 obj-$(CONFIG_MTD_REDWOOD)	+= redwood.o
+obj-$(CONFIG_CHESTNUT)		+= chestnut.o
 obj-$(CONFIG_MTD_UCLINUX)	+= uclinux.o
 obj-$(CONFIG_MTD_NETtel)	+= nettel.o
 obj-$(CONFIG_MTD_SCB2_FLASH)	+= scb2_flash.o

drivers/mtd/maps/chestnut.c

+/*
+ * drivers/mtd/maps/chestnut.c
+ *
+ * Flash map driver for IBM Chestnut (750FXGX Eval)
+ *
+ * Chose not to enable 8 bit flash as it contains the firware and board
+ * info.  Thus only the 32bit flash is supported.
+ *
+ * Author: <source@mvista.com>
+ *
+ * 2004 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <asm/io.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <platforms/chestnut.h>
+
+static struct map_info chestnut32_map = {
+   	.name 		= "User FS",
+   	.size 		= CHESTNUT_32BIT_SIZE,
+   	.bankwidth 	= 4,
+	.phys 		= CHESTNUT_32BIT_BASE,
+};
+
+static struct mtd_partition chestnut32_partitions[] = {
+	{
+		.name 	= "User FS",
+		.offset	= 0,
+		.size	= CHESTNUT_32BIT_SIZE,
+	}
+};
+
+static struct mtd_info *flash32;
+
+int __init init_chestnut(void)
+{
+	/* 32-bit FLASH */
+
+   	chestnut32_map.virt = ioremap(chestnut32_map.phys, chestnut32_map.size);
+
+   	if (!chestnut32_map.virt) {
+      		printk(KERN_NOTICE "Failed to ioremap 32-bit flash\n");
+		return -EIO;
+   	}
+
+	simple_map_init(&chestnut32_map);
+
+   	flash32 = do_map_probe("cfi_probe", &chestnut32_map);
+   	if (flash32) {
+   		flash32->owner = THIS_MODULE;
+   		add_mtd_partitions(flash32, chestnut32_partitions,
+					ARRAY_SIZE(chestnut32_partitions));
+   	} else {
+      		printk(KERN_NOTICE "map probe failed for 32-bit flash\n");
+		return -ENXIO;
+	}
+
+   	return 0;
+}
+
+static void __exit
+cleanup_chestnut(void)
+{
+   	if (flash32) {
+      		del_mtd_partitions(flash32);
+		map_destroy(flash32);
+   	}
+
+   	if (chestnut32_map.virt) {
+      		iounmap((void *)chestnut32_map.virt);
+	  	chestnut32_map.virt = 0;
+   	}
+}
+
+module_init(init_chestnut);
+module_exit(cleanup_chestnut);
+
+MODULE_DESCRIPTION("MTD map and partitions for IBM Chestnut (750fxgx Eval)");
+MODULE_AUTHOR("<mvista.com>");
+MODULE_LICENSE("GPL");

include/asm-ppc/mv64x60_defs.h

@@ -849,6 +849,8 @@
 #define	MV64x60_GPP_VALUE			0xf104
 #define	MV64x60_GPP_INTR_CAUSE			0xf108
 #define	MV64x60_GPP_INTR_MASK			0xf10c
+#define	MV64x60_GPP_VALUE_SET			0xf118
+#define	MV64x60_GPP_VALUE_CLR			0xf11c
 
 
 /*

include/asm-ppc/serial.h

@@ -10,6 +10,8 @@
 
 #if defined(CONFIG_EV64260)
 #include <platforms/ev64260.h>
+#elif defined(CONFIG_CHESTNUT)
+#include <platforms/chestnut.h>
 #elif defined(CONFIG_GEMINI)
 #include <platforms/gemini_serial.h>
 #elif defined(CONFIG_POWERPMC250)