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Commit ae510d4c authored by Ben Dooks's avatar Ben Dooks Committed by Russell King
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[ARM PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1] 

Patch from Ben Dooks

This patch is a repost of 1778/1 with the memory.h file fixed.



This patch contains all the necessary include files for include/asm-arm/arch-s3c2410 for Samsing S3C2410 SoC CPU support. 



The patch also includes the support headers for IPAQ H1940, Simtec BAST and VR1000 board support.
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include/asm-arm/arch-s3c2410/bast-cpld.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/bast-cpld.h
*
* (c) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* BAST - CPLD control constants
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 25-May-2003 BJD Created file, added CTRL1 registers
*/
#ifndef __ASM_ARCH_BASTCPLD_H
#define __ASM_ARCH_BASTCPLD_H
#define BAST_CPLD_CTRL1_LRCOFF (0x00)
#define BAST_CPLD_CTRL1_LRCADC (0x01)
#define BAST_CPLD_CTRL1_LRCDAC (0x02)
#define BAST_CPLD_CTRL1_LRCARM (0x03)
#define BAST_CPLD_CTRL1_LRMASK (0x03)
#endif /* __ASM_ARCH_BASTCPLD_H */
include/asm-arm/arch-s3c2410/bast-irq.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/bast-irq.h
*
* (c) 2003,2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Machine BAST - IRQ Number definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 06-Jan-2003 BJD Linux 2.6.0 version
*/
#ifndef __ASM_ARCH_BASTIRQ_H
#define __ASM_ARCH_BASTIRQ_H
/* irq numbers to onboard peripherals */
#define IRQ_USBOC IRQ_EINT19
#define IRQ_IDE0 IRQ_EINT16
#define IRQ_IDE1 IRQ_EINT17
#define IRQ_PCSERIAL1 IRQ_EINT15
#define IRQ_PCSERIAL2 IRQ_EINT14
#define IRQ_PCPARALLEL IRQ_EINT13
#define IRQ_ASIX IRQ_EINT11
#define IRQ_DM9000 IRQ_EINT10
#define IRQ_ISA IRQ_EINT9
#define IRQ_SMALERT IRQ_EINT8
#endif /* __ASM_ARCH_BASTIRQ_H */
include/asm-arm/arch-s3c2410/bast-map.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/bast-map.h
*
* (c) 2003,2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Machine BAST - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 06-Jan-2003 BJD Linux 2.6.0 version, moved bast specifics from arch/map.h
* 12-Mar-2004 BJD Fixed header include protection
*/
/* needs arch/map.h including with this */
/* ok, we've used up to 0x13000000, now we need to find space for the
* peripherals that live in the nGCS[x] areas, which are quite numerous
* in their space. We also have the board's CPLD to find register space
* for.
*/
#ifndef __ASM_ARCH_BASTMAP_H
#define __ASM_ARCH_BASTMAP_H
#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
/* we put the CPLD registers next, to get them out of the way */
#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) /* 0x01300000 */
#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) /* 0x01400000 */
#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) /* 0x01500000 */
#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) /* 0x01600000 */
#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
/* next, we have the PC104 ISA interrupt registers */
#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000)
#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000)
#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
#define BAST_PA_LCD_RCMD1 (0x8800000)
#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000)
#define BAST_PA_LCD_WCMD1 (0x8000000)
#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000)
#define BAST_PA_LCD_RDATA1 (0x9800000)
#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000)
#define BAST_PA_LCD_WDATA1 (0x9000000)
#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000)
#define BAST_PA_LCD_RCMD2 (0xA800000)
#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000)
#define BAST_PA_LCD_WCMD2 (0xA000000)
#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000)
#define BAST_PA_LCD_RDATA2 (0xB800000)
#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000)
#define BAST_PA_LCD_WDATA2 (0xB000000)
#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000)
/* 0xE0000000 contains the IO space that is split by speed and
* wether the access is for 8 or 16bit IO... this ensures that
* the correct access is made
*
* 0x10000000 of space, partitioned as so:
*
* 0x00000000 to 0x04000000 8bit, slow
* 0x04000000 to 0x08000000 16bit, slow
* 0x08000000 to 0x0C000000 16bit, net
* 0x0C000000 to 0x10000000 16bit, fast
*
* each of these spaces has the following in:
*
* 0x00000000 to 0x01000000 16MB ISA IO space
* 0x01000000 to 0x02000000 16MB ISA memory space
* 0x02000000 to 0x02100000 1MB IDE primary channel
* 0x02100000 to 0x02200000 1MB IDE primary channel aux
* 0x02200000 to 0x02400000 1MB IDE secondary channel
* 0x02300000 to 0x02400000 1MB IDE secondary channel aux
* 0x02400000 to 0x02500000 1MB ASIX ethernet controller
* 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller
* 0x02600000 to 0x02700000 1MB PC SuperIO controller
*
* the phyiscal layout of the zones are:
* nGCS2 - 8bit, slow
* nGCS3 - 16bit, slow
* nGCS4 - 16bit, net
* nGCS5 - 16bit, fast
*/
#define BAST_VA_MULTISPACE (0xE0000000)
#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000)
#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000)
#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000)
#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000)
#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000)
#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000)
#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000)
#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000)
#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000)
#define BAST_VA_MULTISPACE (0xE0000000)
#define BAST_VAM_CS2 (0x00000000)
#define BAST_VAM_CS3 (0x04000000)
#define BAST_VAM_CS4 (0x08000000)
#define BAST_VAM_CS5 (0x0C000000)
/* physical offset addresses for the peripherals */
#define BAST_PA_ISAIO (0x00000000)
#define BAST_PA_ASIXNET (0x01000000)
#define BAST_PA_SUPERIO (0x01800000)
#define BAST_PA_IDEPRI (0x02000000)
#define BAST_PA_IDEPRIAUX (0x02800000)
#define BAST_PA_IDESEC (0x03000000)
#define BAST_PA_IDESECAUX (0x03800000)
#define BAST_PA_ISAMEM (0x04000000)
#define BAST_PA_DM9000 (0x05000000)
/* some configurations for the peripherals */
#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
/* */
#define BAST_ASIXNET_CS BAST_VAM_CS5
#define BAST_IDE_CS BAST_VAM_CS5
#define BAST_DM9000_CS BAST_VAM_CS4
#endif /* __ASM_ARCH_BASTMAP_H */
include/asm-arm/arch-s3c2410/dma.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-bast/dma.h
*
* Copyright (C) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Samsung S3C2410X DMA support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* ??-May-2003 BJD Created file
* ??-Jun-2003 BJD Added more dma functionality to go with arch
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#include <linux/config.h>
#include "hardware.h"
/*
* This is the maximum DMA address(physical address) that can be DMAd to.
*
*/
#define MAX_DMA_ADDRESS 0x20000000
#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
/* according to the samsung port, we cannot use the regular
* dma channels... we must therefore provide our own interface
* for DMA, and allow our drivers to use that.
*/
#define MAX_DMA_CHANNELS 0
/* we have 4 dma channels */
#define S3C2410_DMA_CHANNELS (4)
/* dma buffer */
typedef struct s3c2410_dma_buf_s s3c2410_dma_buf_t;
struct s3c2410_dma_buf_s {
s3c2410_dma_buf_t *next;
int magic; /* magic */
int size; /* buffer size in bytes */
dma_addr_t data; /* start of DMA data */
dma_addr_t ptr; /* where the DMA got to [1] */
int ref;
void *id; /* client's id */
unsigned char no_callback; /* disable callback for buffer */
};
/* [1] is this updated for both recv/send modes? */
typedef struct s3c2410_dma_chan_s s3c2410_dma_chan_t;
typedef void (*s3c2410_dma_cbfn_t)(s3c2410_dma_chan_t *, void *buf, int size);
typedef void (*s3c2410_dma_enfn_t)(s3c2410_dma_chan_t *, int on);
typedef void (*s3c2410_dma_pausefn_t)(s3c2410_dma_chan_t *, int on);
struct s3c2410_dma_chan_s {
/* channel state flags */
unsigned char number; /* number of this dma channel */
unsigned char in_use; /* channel allocated */
unsigned char started; /* channel has been started */
unsigned char stopped; /* channel stopped */
unsigned char sleeping;
unsigned char xfer_unit; /* size of an transfer */
unsigned char irq_claimed;
/* channel's hardware position and configuration */
unsigned long regs; /* channels registers */
unsigned int irq; /* channel irq */
unsigned long addr_reg; /* data address register for buffs */
unsigned long dcon; /* default value of DCON */
/* driver handlers for channel */
s3c2410_dma_cbfn_t callback_fn; /* callback function for buf-done */
s3c2410_dma_enfn_t enable_fn; /* channel enable function */
s3c2410_dma_pausefn_t pause_fn; /* channel pause function */
/* buffer list and information */
s3c2410_dma_buf_t *curr; /* current dma buffer */
s3c2410_dma_buf_t *next; /* next buffer to load */
s3c2410_dma_buf_t *end; /* end of queue */
int queue_count; /* number of items in queue */
int loaded_count; /* number of loaded buffers */
};
/* note, we don't really use dma_deivce_t at the moment */
typedef unsigned long dma_device_t;
typedef enum s3c2410_dmasrc_e s3c2410_dmasrc_t;
/* these two defines control the source for the dma channel,
* wether it is from memory or an device
*/
enum s3c2410_dmasrc_e {
S3C2410_DMASRC_HW, /* source is memory */
S3C2410_DMASRC_MEM /* source is hardware */
};
/* dma control routines */
extern int s3c2410_request_dma(dmach_t channel, const char *devid, void *dev);
extern int s3c2410_free_dma(dmach_t channel);
extern int s3c2410_dma_flush_all(dmach_t channel);
extern int s3c2410_dma_stop(dmach_t channel);
extern int s3c2410_dma_resume(dmach_t channel);
extern int s3c2410_dma_queue(dmach_t channel, void *id,
dma_addr_t data, int size);
#define s3c2410_dma_queue_buffer s3c2410_dma_queue
/* channel configuration */
extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
extern int s3c2410_dma_devconfig(int channel, s3c2410_dmasrc_t source,
int hwcfg, unsigned long devaddr);
extern int s3c2410_dma_set_enablefn(dmach_t, s3c2410_dma_enfn_t rtn);
extern int s3c2410_dma_set_pausefn(dmach_t, s3c2410_dma_pausefn_t rtn);
extern int s3c2410_dma_set_callbackfn(dmach_t, s3c2410_dma_cbfn_t rtn);
#define s3c2410_dma_set_callback s3c2410_dma_set_callbackfn
#define S3C2410_DMA_DISRC (0x00)
#define S3C2410_DMA_DISRCC (0x04)
#define S3C2410_DMA_DIDST (0x08)
#define S3C2410_DMA_DIDSTC (0x0C)
#define S3C2410_DMA_DCON (0x10)
#define S3C2410_DMA_DSTAT (0x14)
#define S3C2410_DMA_DCSRC (0x18)
#define S3C2410_DMA_DCDST (0x1C)
#define S3C2410_DMA_DMASKTRIG (0x20)
#define S3C2410_DMASKTRIG_STOP (1<<2)
#define S3C2410_DMASKTRIG_ON (1<<1)
#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
#define S3C2410_DCOM_DEMAND (0<<31)
#define S3C2410_DCON_HANDSHAKE (1<<31)
#define S3C2410_DCON_SYNC_PCLK (0<<30)
#define S3C2410_DCON_SYNC_HCLK (1<<30)
#define S3C2410_DCON_INTREQ (1<<29)
#define S3C2410_DCON_SRCSHIFT (24)
#define S3C2410_DCON_BYTE (0<<20)
#define S3C2410_DCON_HALFWORD (1<<20)
#define S3C2410_DCON_WORD (2<<20)
#define S3C2410_DCON_AUTORELOAD (0<<22)
#define S3C2410_DCON_HWTRIG (1<<23)
#endif /* __ASM_ARCH_DMA_H */
include/asm-arm/arch-s3c2410/hardware.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/hardware.h
*
* (c) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - hardware
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 21-May-2003 BJD Created file
* 06-Jun-2003 BJD Added CPU frequency settings
* 03-Sep-2003 BJD Linux v2.6 support
* 12-Mar-2004 BJD Fixed include protection, fixed type of clock vars
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#ifndef __ASSEMBLY__
/* processor clock settings, in Hz */
extern unsigned long s3c2410_pclk;
extern unsigned long s3c2410_hclk;
extern unsigned long s3c2410_fclk;
#endif /* __ASSEMBLY__ */
#include <asm/sizes.h>
#include <asm/arch/map.h>
/* machine specific includes, such as the BAST */
#if defined(CONFIG_ARCH_BAST)
#include <asm/arch/bast-cpld.h>
#endif
/* currently here until moved into config (todo) */
#define CONFIG_NO_MULTIWORD_IO
#endif /* __ASM_ARCH_HARDWARE_H */
include/asm-arm/arch-s3c2410/ide.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/ide.h
*
* Copyright (C) 1997 Russell King
* Copyright (C) 2003 Simtec Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Modifications:
* 29-07-1998 RMK Major re-work of IDE architecture specific code
* 16-05-2003 BJD Changed to work with BAST IDE ports
* 04-09-2003 BJD Modifications for V2.6
*/
#ifndef __ASM_ARCH_IDE_H
#define __ASM_ARCH_IDE_H
#include <asm/irq.h>
/*
* Set up a hw structure for a specified data port, control port and IRQ.
* This should follow whatever the default interface uses.
*/
static __inline__ void
ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int *irq)
{
ide_ioreg_t reg = (ide_ioreg_t) data_port;
int i;
memset(hw, 0, sizeof(*hw));
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw->io_ports[i] = reg;
reg += 1;
}
hw->io_ports[IDE_CONTROL_OFFSET] = (ide_ioreg_t) ctrl_port;
if (irq)
*irq = 0;
}
/* we initialise our ide devices from the main ide core, due to problems
* with doing it in this function
*/
#define ide_init_default_hwifs() do { } while(0)
#endif /* __ASM_ARCH_IDE_H */
include/asm-arm/arch-s3c2410/io.h 0 → 100644
View file @ ae510d4c
/*
* linux/include/asm-arm/arch-s3c2410/io.h
* from linux/include/asm-arm/arch-rpc/io.h
*
* Copyright (C) 1997 Russell King
* (C) 2003 Simtec Electronics
*
* Modifications:
* 06-Dec-1997 RMK Created.
* 02-Sep-2003 BJD Modified for S3C2410
*
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
/*
* We use two different types of addressing - PC style addresses, and ARM
* addresses. PC style accesses the PC hardware with the normal PC IO
* addresses, eg 0x3f8 for serial#1. ARM addresses are above A28
* and are translated to the start of IO. Note that all addresses are
* not shifted left!
*/
#define __PORT_PCIO(x) ((x) < (1<<28))
#define PCIO_BASE (S3C2410_VA_ISA_WORD)
#define PCIO_BASE_b (S3C2410_VA_ISA_BYTE)
#define PCIO_BASE_w (S3C2410_VA_ISA_WORD)
#define PCIO_BASE_l (S3C2410_VA_ISA_WORD)
/*
* Dynamic IO functions - let the compiler
* optimize the expressions
*/
#define DECLARE_DYN_OUT(sz,fnsuffix,instr) \
static inline void __out##fnsuffix (unsigned int val, unsigned int port) \
{ \
unsigned long temp; \
__asm__ __volatile__( \
"cmp %2, #(1<<28)\n\t" \
"mov %0, %2\n\t" \
"addcc %0, %0, %3\n\t" \
"str" instr " %1, [%0, #0 ] @ out" #fnsuffix \
: "=&r" (temp) \
: "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
: "cc"); \
}
#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
static inline unsigned sz __in##fnsuffix (unsigned int port) \
{ \
unsigned long temp, value; \
__asm__ __volatile__( \
"cmp %2, #(1<<28)\n\t" \
"mov %0, %2\n\t" \
"addcc %0, %0, %3\n\t" \
"ldr" instr " %1, [%0, #0 ] @ in" #fnsuffix \
: "=&r" (temp), "=r" (value) \
: "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
: "cc"); \
return (unsigned sz)value; \
}
static inline unsigned int __ioaddr (unsigned int port)
{
if (__PORT_PCIO(port))
return (unsigned int)(PCIO_BASE + (port));
else
return (unsigned int)(0 + (port));
}
#define DECLARE_IO(sz,fnsuffix,instr) \
DECLARE_DYN_IN(sz,fnsuffix,instr) \
DECLARE_DYN_OUT(sz,fnsuffix,instr)
DECLARE_IO(char,b,"b")
DECLARE_IO(short,w,"h")
DECLARE_IO(int,l,"")
#undef DECLARE_IO
#undef DECLARE_DYN_IN
/*
* Constant address IO functions
*
* These have to be macros for the 'J' constraint to work -
* +/-4096 immediate operand.
*/
#define __outbc(value,port) \
({ \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"strb %0, [%1, %2] @ outbc" \
: : "r" (value), "r" (PCIO_BASE), "Jr" ((port))); \
else \
__asm__ __volatile__( \
"strb %0, [%1, #0] @ outbc" \
: : "r" (value), "r" ((port))); \
})
#define __inbc(port) \
({ \
unsigned char result; \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"ldrb %0, [%1, %2] @ inbc" \
: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
else \
__asm__ __volatile__( \
"ldrb %0, [%1, #0] @ inbc" \
: "=r" (result) : "r" ((port))); \
result; \
})
#define __outwc(value,port) \
({ \
unsigned long v = value; \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"strh %0, [%1, %2] @ outwc" \
: : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
else \
__asm__ __volatile__( \
"strh %0, [%1, #0] @ outwc" \
: : "r" (v), "r" ((port))); \
})
#define __inwc(port) \
({ \
unsigned short result; \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"ldrh %0, [%1, %2] @ inwc" \
: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
else \
__asm__ __volatile__( \
"ldrh %0, [%1, #0] @ inwc" \
: "=r" (result) : "r" ((port))); \
result; \
})
#define __outlc(value,port) \
({ \
unsigned long v = value; \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"str %0, [%1, %2] @ outlc" \
: : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
else \
__asm__ __volatile__( \
"str %0, [%1, #0] @ outlc" \
: : "r" (v), "r" ((port))); \
})
#define __inlc(port) \
({ \
unsigned long result; \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"ldr %0, [%1, %2] @ inlc" \
: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
else \
__asm__ __volatile__( \
"ldr %0, [%1, #0] @ inlc" \
: "=r" (result) : "r" ((port))); \
result; \
})
#define __ioaddrc(port) (__PORT_PCIO((port)) ? PCIO_BASE + ((port)) : ((port)))
#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p))
/* the following macro is deprecated */
#define ioaddr(port) __ioaddr((port))
#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l)
#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
#define insl(p,d,l) __raw_readsl(__ioaddr(p),d,l)
#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
#define outsl(p,d,l) __raw_writesl(__ioaddr(p),d,l)
/*
* 1:1 mapping for ioremapped regions.
*/
#define __mem_pci(x) (x)
#endif
include/asm-arm/arch-s3c2410/irqs.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/irqs.h
*
* Copyright (c) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 12-May-2003 BJD Created file
* 08-Jan-2003 BJD Linux 2.6.0 version, moved BAST bits out
* 12-Mar-2004 BJD Fixed bug in header protection
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H __FILE__
/* we keep the first set of CPU IRQs out of the range of
* the ISA space, so that the PC104 has them to itself
* and we don't end up having to do horrible things to the
* standard ISA drivers....
*/
#define S3C2410_CPUIRQ_OFFSET (16)
#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
/* main cpu interrupts */
#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */
#define IRQ_EINT1 S3C2410_IRQ(1)
#define IRQ_EINT2 S3C2410_IRQ(2)
#define IRQ_EINT3 S3C2410_IRQ(3)
#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */
#define IRQ_EINT8t23 S3C2410_IRQ(5)
#define IRQ_RESERVED6 S3C2410_IRQ(6)
#define IRQ_BATT_FLT S3C2410_IRQ(7)
#define IRQ_TICK S3C2410_IRQ(8) /* 24 */
#define IRQ_WDT S3C2410_IRQ(9)
#define IRQ_TIMER0 S3C2410_IRQ(10)
#define IRQ_TIMER1 S3C2410_IRQ(11)
#define IRQ_TIMER2 S3C2410_IRQ(12)
#define IRQ_TIMER3 S3C2410_IRQ(13)
#define IRQ_TIMER4 S3C2410_IRQ(14)
#define IRQ_UART2 S3C2410_IRQ(15)
#define IRQ_LCD S3C2410_IRQ(16) /* 32 */
#define IRQ_DMA0 S3C2410_IRQ(17)
#define IRQ_DMA1 S3C2410_IRQ(18)
#define IRQ_DMA2 S3C2410_IRQ(19)
#define IRQ_DMA3 S3C2410_IRQ(20)
#define IRQ_SDI S3C2410_IRQ(21)
#define IRQ_SPI0 S3C2410_IRQ(22)
#define IRQ_UART1 S3C2410_IRQ(23)
#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */
#define IRQ_USBD S3C2410_IRQ(25)
#define IRQ_USBH S3C2410_IRQ(26)
#define IRQ_IIC S3C2410_IRQ(27)
#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */
#define IRQ_SPI1 S3C2410_IRQ(29)
#define IRQ_RTC S3C2410_IRQ(30)
#define IRQ_ADCPARENT S3C2410_IRQ(31)
/* interrupts generated from the external interrupts sources */
#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */
#define IRQ_EINT5 S3C2410_IRQ(33)
#define IRQ_EINT6 S3C2410_IRQ(34)
#define IRQ_EINT7 S3C2410_IRQ(35)
#define IRQ_EINT8 S3C2410_IRQ(36)
#define IRQ_EINT9 S3C2410_IRQ(37)
#define IRQ_EINT10 S3C2410_IRQ(38)
#define IRQ_EINT11 S3C2410_IRQ(39)
#define IRQ_EINT12 S3C2410_IRQ(40)
#define IRQ_EINT13 S3C2410_IRQ(41)
#define IRQ_EINT14 S3C2410_IRQ(42)
#define IRQ_EINT15 S3C2410_IRQ(43)
#define IRQ_EINT16 S3C2410_IRQ(44)
#define IRQ_EINT17 S3C2410_IRQ(45)
#define IRQ_EINT18 S3C2410_IRQ(46)
#define IRQ_EINT19 S3C2410_IRQ(47)
#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */
#define IRQ_EINT21 S3C2410_IRQ(49)
#define IRQ_EINT22 S3C2410_IRQ(50)
#define IRQ_EINT23 S3C2410_IRQ(51)
#define IRQ_EINT(x) S3C2410_IRQ((x >= 4) ? (IRQ_EINT4 + (x) - 4) : (S3C2410_IRQ(0) + (x)))
#define IRQ_LCD_FIFO S3C2410_IRQ(52)
#define IRQ_LCD_FRAME S3C2410_IRQ(53)
/* IRQs for the interal UARTs, and ADC
* these need to be ordered in number of appearance in the
* SUBSRC mask register
*/
#define IRQ_S3CUART_RX0 S3C2410_IRQ(54) /* 70 */
#define IRQ_S3CUART_TX0 S3C2410_IRQ(55) /* 71 */
#define IRQ_S3CUART_ERR0 S3C2410_IRQ(56)
#define IRQ_S3CUART_RX1 S3C2410_IRQ(57)
#define IRQ_S3CUART_TX1 S3C2410_IRQ(58)
#define IRQ_S3CUART_ERR1 S3C2410_IRQ(59)
#define IRQ_S3CUART_RX2 S3C2410_IRQ(60)
#define IRQ_S3CUART_TX2 S3C2410_IRQ(61)
#define IRQ_S3CUART_ERR2 S3C2410_IRQ(62)
#define IRQ_TC S3C2410_IRQ(63)
#define IRQ_ADC S3C2410_IRQ(64)
#define NR_IRQS (IRQ_ADC+1)
#endif /* __ASM_ARCH_IRQ_H */
include/asm-arm/arch-s3c2410/map.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/map.h
*
* (c) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 12-May-2003 BJD Created file
* 06-Jan-2003 BJD Linux 2.6.0 version, moved bast specifics out
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H
/* we have a bit of a tight squeeze to fit all our registers from
* 0xF00000000 upwards, since we use all of the nGCS space in some
* capacity, and also need to fit the S3C2410 registers in as well...
*
* we try to ensure stuff like the IRQ registers are available for
* an single MOVS instruction (ie, only 8 bits of set data)
*
* Note, we are trying to remove some of these from the implementation
* as they are only useful to certain drivers...
*/
#define S3C2410_ADDR(x) (0xF0000000 + (x))
/* interrupt controller is the first thing we put in, to make
* the assembly code for the irq detection easier
*/
#define S3C2410_VA_IRQ S3C2410_ADDR(0x00000000)
#define S3C2410_PA_IRQ (0x4A000000)
#define S3C2410_SZ_IRQ SZ_1M
/* memory controller registers */
#define S3C2410_VA_MEMCTRL S3C2410_ADDR(0x00100000)
#define S3C2410_PA_MEMCTRL (0x48000000)
#define S3C2410_SZ_MEMCTRL SZ_1M
/* USB host controller */
#define S3C2410_VA_USBHOST S3C2410_ADDR(0x00200000)
#define S3C2410_PA_USBHOST (0x49000000)
#define S3C2410_SZ_USBHOST SZ_1M
/* DMA controller */
#define S3C2410_VA_DMA S3C2410_ADDR(0x00300000)
#define S3C2410_PA_DMA (0x4B000000)
#define S3C2410_SZ_DMA SZ_1M
/* Clock and Power management */
#define S3C2410_VA_CLKPWR S3C2410_ADDR(0x00400000)
#define S3C2410_PA_CLKPWR (0x4C000000)
#define S3C2410_SZ_CLKPWR SZ_1M
/* LCD controller */
#define S3C2410_VA_LCD S3C2410_ADDR(0x00600000)
#define S3C2410_PA_LCD (0x4D000000)
#define S3C2410_SZ_LCD SZ_1M
/* NAND flash controller */
#define S3C2410_VA_NAND S3C2410_ADDR(0x00700000)
#define S3C2410_PA_NAND (0x4E000000)
#define S3C2410_SZ_NAND SZ_1M
/* UARTs */
#define S3C2410_VA_UART S3C2410_ADDR(0x00800000)
#define S3C2410_PA_UART (0x50000000)
#define S3C2410_SZ_UART SZ_1M
/* Timers */
#define S3C2410_VA_TIMER S3C2410_ADDR(0x00900000)
#define S3C2410_PA_TIMER (0x51000000)
#define S3C2410_SZ_TIMER SZ_1M
/* USB Device port */
#define S3C2410_VA_USBDEV S3C2410_ADDR(0x00A00000)
#define S3C2410_PA_USBDEV (0x52000000)
#define S3C2410_SZ_USBDEV SZ_1M
/* Watchdog */
#define S3C2410_VA_WATCHDOG S3C2410_ADDR(0x00B00000)
#define S3C2410_PA_WATCHDOG (0x53000000)
#define S3C2410_SZ_WATCHDOG SZ_1M
/* IIC hardware controller */
#define S3C2410_VA_IIC S3C2410_ADDR(0x00C00000)
#define S3C2410_PA_IIC (0x54000000)
#define S3C2410_SZ_IIC SZ_1M
#define VA_IIC_BASE (S3C2410_VA_IIC)
/* IIS controller */
#define S3C2410_VA_IIS S3C2410_ADDR(0x00D00000)
#define S3C2410_PA_IIS (0x55000000)
#define S3C2410_SZ_IIS SZ_1M
/* GPIO ports */
#define S3C2410_VA_GPIO S3C2410_ADDR(0x00E00000)
#define S3C2410_PA_GPIO (0x56000000)
#define S3C2410_SZ_GPIO SZ_1M
/* RTC */
#define S3C2410_VA_RTC S3C2410_ADDR(0x00F00000)
#define S3C2410_PA_RTC (0x57000000)
#define S3C2410_SZ_RTC SZ_1M
/* ADC */
#define S3C2410_VA_ADC S3C2410_ADDR(0x01000000)
#define S3C2410_PA_ADC (0x58000000)
#define S3C2410_SZ_ADC SZ_1M
/* SPI */
#define S3C2410_VA_SPI S3C2410_ADDR(0x01100000)
#define S3C2410_PA_SPI (0x59000000)
#define S3C2410_SZ_SPI SZ_1M
/* SDI */
#define S3C2410_VA_SDI S3C2410_ADDR(0x01200000)
#define S3C2410_PA_SDI (0x5A000000)
#define S3C2410_SZ_SDI SZ_1M
/* ISA style IO, for each machine to sort out mappings for, if it
* implements it. We reserve two 16M regions for ISA.
*/
#define S3C2410_VA_ISA_WORD S3C2410_ADDR(0x02000000)
#define S3C2410_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
/* physical addresses of all the chip-select areas */
#define S3C2410_CS0 (0x00000000)
#define S3C2410_CS1 (0x08000000)
#define S3C2410_CS2 (0x10000000)
#define S3C2410_CS3 (0x18000000)
#define S3C2410_CS4 (0x20000000)
#define S3C2410_CS5 (0x28000000)
#define S3C2410_CS6 (0x30000000)
#define S3C2410_CS7 (0x38000000)
#define S3C2410_SDRAM_PA (S3C2410_CS6)
#endif /* __ASM_ARCH_MAP_H */
include/asm-arm/arch-s3c2410/memory.h 0 → 100644
View file @ ae510d4c
/*
* linux/include/asm-arm/arch-s3c2410/memory.h
*
* from linux/include/asm-arm/arch-rpc/memory.h
*
* Copyright (C) 1996,1997,1998 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 20-Oct-1996 RMK Created
* 31-Dec-1997 RMK Fixed definitions to reduce warnings
* 11-Jan-1998 RMK Uninlined to reduce hits on cache
* 08-Feb-1998 RMK Added __virt_to_bus and __bus_to_virt
* 21-Mar-1999 RMK Renamed to memory.h
* RMK Added TASK_SIZE and PAGE_OFFSET
* 05-Apr-2004 BJD Copied and altered for arch-s3c2410
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Task size: 3GB
*/
#define TASK_SIZE (0xbf000000UL)
#define TASK_SIZE_26 (0x04000000UL)
/*
* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
*/
#define TASK_UNMAPPED_BASE (0x40000000)
/*
* Page offset: 3GB
*
* DRAM starts at 0x30000000
*/
#define PAGE_OFFSET (0xc0000000UL)
#define PHYS_OFFSET (0x30000000UL)
#define __virt_to_phys__is_a_macro
#define __virt_to_phys(vpage) ((vpage) - PAGE_OFFSET + PHYS_OFFSET)
#define __phys_to_virt__is_a_macro
#define __phys_to_virt(ppage) ((ppage) + PAGE_OFFSET - PHYS_OFFSET)
/*
* These are exactly the same on the S3C2410 as the
* physical memory view.
*/
#define __virt_to_bus__is_a_macro
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt__is_a_macro
#define __bus_to_virt(x) __phys_to_virt(x)
#endif
include/asm-arm/arch-s3c2410/param.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/param.h
*
* (c) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - Machine parameters
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 02-Sep-2003 BJD Created file
* 12-Mar-2004 BJD Added include protection
*/
#ifndef __ASM_ARCH_PARAM_H
#define __ASM_ARCH_PARAM_H
/* we cannot get our timer down to 100Hz with the setup as is, but we can
* manage 200 clock ticks per second... if this is a problem, we can always
* add a software pre-scaler to the evil timer systems.
*/
#define __KERNEL_HZ 200
#endif /* __ASM_ARCH_PARAM_H */
include/asm-arm/arch-s3c2410/regs-clock.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm/arch-s3c2410/regs-clock.h
*
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2410 clock register definitions
*
* Changelog:
* 19-06-2003 BJD Created file
* 12-03-2004 BJD Updated include protection
*/
#ifndef __ASM_ARM_REGS_CLOCK
#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
#define S3C2410_CLKREG(x) ((x) + S3C2410_VA_CLKPWR)
#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
#define S3C2410_LOCKTIME S3C2410_CLKREG(0x00)
#define S3C2410_MPLLCON S3C2410_CLKREG(0x04)
#define S3C2410_UPLLCON S3C2410_CLKREG(0x08)
#define S3C2410_CLKCON S3C2410_CLKREG(0x0C)
#define S3C2410_CLKSLOW S3C2410_CLKREG(0x10)
#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
#define S3C2410_PLLCON_MDIVSHIFT 12
#define S3C2410_PLLCON_PDIVSHIFT 4
#define S3C2410_PLLCON_SDIVSHIFT 0
#define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
#define S3C2410_PLLCON_PDIVMASK ((1<<5)-1)
#define S3C2410_PLLCON_SDIVMASK 3
/* DCLKCON register addresses in gpio.h */
#define S3C2410_DCLKCON_DCLK0EN (1<<0)
#define S3C2410_DCLKCON_DCLK0_PCLK (0<<1)
#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
#define S3C2410_DCLKCON_DCLK1EN (1<<16)
#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
#define S3C2410_CLKDIVN_PDIVN (1<<0)
#define S3C2410_CLKDIVN_HDIVN (1<<1)
static inline unsigned int
s3c2410_get_pll(int pllval, int baseclk)
{
int mdiv, pdiv, sdiv;
mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
mdiv &= S3C2410_PLLCON_MDIVMASK;
pdiv &= S3C2410_PLLCON_PDIVMASK;
sdiv &= S3C2410_PLLCON_SDIVMASK;
return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv);
}
#endif /* __ASM_ARM_REGS_CLOCK */
include/asm-arm/arch-s3c2410/regs-gpio.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm/hardware/s3c2410/
*
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2410 GPIO register definitions
*
* Changelog:
* 19-06-2003 BJD Created file
* 23-06-2003 BJD Updated GSTATUS registers
* 12-03-2004 BJD Updated include protection
*/
#ifndef __ASM_ARCH_REGS_GPIO_H
#define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $"
/* configure GPIO ports A..G */
#define S3C2410_GPIOREG(x) ((x) + S3C2410_VA_GPIO)
/* port A - 22bits, zero in bit X makes pin X output
* 1 makes port special function, this is default
*/
#define S3C2410_GPACON S3C2410_GPIOREG(0x00)
#define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
/* 0x08 and 0x0c are reserved */
/* GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
* 00 = input, 01 = output, 10=special function, 11=reserved
* bit 0,1 = pin 0, 2,3= pin 1...
*
* CPBUP = pull up resistor control, 1=disabled, 0=enabled
*/
#define S3C2410_GPBCON S3C2410_GPIOREG(0x10)
#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)
#define S3C2410_GPBUP S3C2410_GPIOREG(0x18)
/* no i/o pin in port b can have value 3! */
#define S3C2410_GPB0_INP (0x00 << 0)
#define S3C2410_GPB0_OUTP (0x01 << 0)
#define S3C2410_GPB0_TOUT0 (0x02 << 0)
#define S3C2410_GPB1_INP (0x00 << 2)
#define S3C2410_GPB1_OUTP (0x01 << 2)
#define S3C2410_GPB1_TOUT1 (0x02 << 2)
#define S3C2410_GPB2_INP (0x00 << 4)
#define S3C2410_GPB2_OUTP (0x01 << 4)
#define S3C2410_GPB2_TOUT2 (0x02 << 4)
#define S3C2410_GPB3_INP (0x00 << 6)
#define S3C2410_GPB3_OUTP (0x01 << 6)
#define S3C2410_GPB3_TOUT3 (0x02 << 6)
#define S3C2410_GPB4_INP (0x00 << 8)
#define S3C2410_GPB4_OUTP (0x01 << 8)
#define S3C2410_GPB4_TCLK0 (0x02 << 8)
#define S3C2410_GPB4_MASK (0x03 << 8)
#define S3C2410_GPB5_INP (0x00 << 10)
#define S3C2410_GPB5_OUTP (0x01 << 10)
#define S3C2410_GPB5_nXBACK (0x02 << 10)
#define S3C2410_GPB6_INP (0x00 << 12)
#define S3C2410_GPB6_OUTP (0x01 << 12)
#define S3C2410_GPB6_nXBREQ (0x02 << 12)
#define S3C2410_GPB7_INP (0x00 << 14)
#define S3C2410_GPB7_OUTP (0x01 << 14)
#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
#define S3C2410_GPB8_INP (0x00 << 16)
#define S3C2410_GPB8_OUTP (0x01 << 16)
#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
#define S3C2410_GPB9_INP (0x00 << 18)
#define S3C2410_GPB9_OUTP (0x01 << 18)
#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
#define S3C2410_GPB10_INP (0x00 << 18)
#define S3C2410_GPB10_OUTP (0x01 << 18)
#define S3C2410_GPB10_nXDRE0 (0x02 << 18)
/* Port C consits of 16 GPIO/Special function
*
* almost identical setup to port b, but the special functions are mostly
* to do with the video system's sync/etc.
*/
#define S3C2410_GPCCON S3C2410_GPIOREG(0x20)
#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
#define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
#define S3C2410_GPC0_INP (0x00 << 0)
#define S3C2410_GPC0_OUTP (0x01 << 0)
#define S3C2410_GPC0_LEND (0x02 << 0)
#define S3C2410_GPC1_INP (0x00 << 2)
#define S3C2410_GPC1_OUTP (0x01 << 2)
#define S3C2410_GPC1_VCLK (0x02 << 2)
#define S3C2410_GPC2_INP (0x00 << 4)
#define S3C2410_GPC2_OUTP (0x01 << 4)
#define S3C2410_GPC2_VLINE (0x02 << 4)
#define S3C2410_GPC3_INP (0x00 << 6)
#define S3C2410_GPC3_OUTP (0x01 << 6)
#define S3C2410_GPC3_VFRAME (0x02 << 6)
#define S3C2410_GPC4_INP (0x00 << 8)
#define S3C2410_GPC4_OUTP (0x01 << 8)
#define S3C2410_GPC4_VM (0x02 << 8)
#define S3C2410_GPC5_INP (0x00 << 10)
#define S3C2410_GPC5_OUTP (0x01 << 10)
#define S3C2410_GPC5_LCDVF0 (0x02 << 10)
#define S3C2410_GPC6_INP (0x00 << 12)
#define S3C2410_GPC6_OUTP (0x01 << 12)
#define S3C2410_GPC6_LCDVF1 (0x02 << 12)
#define S3C2410_GPC7_INP (0x00 << 14)
#define S3C2410_GPC7_OUTP (0x01 << 14)
#define S3C2410_GPC7_LCDVF2 (0x02 << 14)
#define S3C2410_GPC8_INP (0x00 << 16)
#define S3C2410_GPC8_OUTP (0x01 << 16)
#define S3C2410_GPC8_VD0 (0x02 << 16)
#define S3C2410_GPC9_INP (0x00 << 18)
#define S3C2410_GPC9_OUTP (0x01 << 18)
#define S3C2410_GPC9_VD1 (0x02 << 18)
#define S3C2410_GPC10_INP (0x00 << 20)
#define S3C2410_GPC10_OUTP (0x01 << 20)
#define S3C2410_GPC10_VD2 (0x02 << 20)
#define S3C2410_GPC11_INP (0x00 << 22)
#define S3C2410_GPC11_OUTP (0x01 << 22)
#define S3C2410_GPC11_VD3 (0x02 << 22)
#define S3C2410_GPC12_INP (0x00 << 24)
#define S3C2410_GPC12_OUTP (0x01 << 24)
#define S3C2410_GPC12_VD4 (0x02 << 24)
#define S3C2410_GPC13_INP (0x00 << 26)
#define S3C2410_GPC13_OUTP (0x01 << 26)
#define S3C2410_GPC13_VD5 (0x02 << 26)
#define S3C2410_GPC14_INP (0x00 << 28)
#define S3C2410_GPC14_OUTP (0x01 << 28)
#define S3C2410_GPC14_VD6 (0x02 << 28)
#define S3C2410_GPC15_INP (0x00 << 30)
#define S3C2410_GPC15_OUTP (0x01 << 30)
#define S3C2410_GPC15_VD7 (0x02 << 30)
/* Port D consists of 16 GPIO/Special function
*
* almost identical setup to port b, but the special functions are mostly
* to do with the video system's data.
*/
#define S3C2410_GPDCON S3C2410_GPIOREG(0x30)
#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
#define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
#define S3C2410_GPD0_INP (0x00 << 0)
#define S3C2410_GPD0_OUTP (0x01 << 0)
#define S3C2410_GPD0_VD8 (0x02 << 0)
#define S3C2410_GPD1_INP (0x00 << 2)
#define S3C2410_GPD1_OUTP (0x01 << 2)
#define S3C2410_GPD1_VD9 (0x02 << 2)
#define S3C2410_GPD2_INP (0x00 << 4)
#define S3C2410_GPD2_OUTP (0x01 << 4)
#define S3C2410_GPD2_VD10 (0x02 << 4)
#define S3C2410_GPD3_INP (0x00 << 6)
#define S3C2410_GPD3_OUTP (0x01 << 6)
#define S3C2410_GPD3_VD11 (0x02 << 6)
#define S3C2410_GPD4_INP (0x00 << 8)
#define S3C2410_GPD4_OUTP (0x01 << 8)
#define S3C2410_GPD4_VD12 (0x02 << 8)
#define S3C2410_GPD5_INP (0x00 << 10)
#define S3C2410_GPD5_OUTP (0x01 << 10)
#define S3C2410_GPD5_VD13 (0x02 << 10)
#define S3C2410_GPD6_INP (0x00 << 12)
#define S3C2410_GPD6_OUTP (0x01 << 12)
#define S3C2410_GPD6_VD14 (0x02 << 12)
#define S3C2410_GPD7_INP (0x00 << 14)
#define S3C2410_GPD7_OUTP (0x01 << 14)
#define S3C2410_GPD7_VD15 (0x02 << 14)
#define S3C2410_GPD8_INP (0x00 << 16)
#define S3C2410_GPD8_OUTP (0x01 << 16)
#define S3C2410_GPD8_VD16 (0x02 << 16)
#define S3C2410_GPD9_INP (0x00 << 18)
#define S3C2410_GPD9_OUTP (0x01 << 18)
#define S3C2410_GPD9_VD17 (0x02 << 18)
#define S3C2410_GPD10_INP (0x00 << 20)
#define S3C2410_GPD10_OUTP (0x01 << 20)
#define S3C2410_GPD10_VD18 (0x02 << 20)
#define S3C2410_GPD11_INP (0x00 << 22)
#define S3C2410_GPD11_OUTP (0x01 << 22)
#define S3C2410_GPD11_VD19 (0x02 << 22)
#define S3C2410_GPD12_INP (0x00 << 24)
#define S3C2410_GPD12_OUTP (0x01 << 24)
#define S3C2410_GPD12_VD20 (0x02 << 24)
#define S3C2410_GPD13_INP (0x00 << 26)
#define S3C2410_GPD13_OUTP (0x01 << 26)
#define S3C2410_GPD13_VD21 (0x02 << 26)
#define S3C2410_GPD14_INP (0x00 << 28)
#define S3C2410_GPD14_OUTP (0x01 << 28)
#define S3C2410_GPD14_VD22 (0x02 << 28)
#define S3C2410_GPD15_INP (0x00 << 30)
#define S3C2410_GPD15_OUTP (0x01 << 30)
#define S3C2410_GPD15_VD23 (0x02 << 30)
/* Port E consists of 16 GPIO/Special function
*
* again, the same as port B, but dealing with I2S, SDI, and
* more miscellaneous functions
*/
#define S3C2410_GPECON S3C2410_GPIOREG(0x40)
#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
#define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
#define S3C2410_GPE0_INP (0x00 << 0)
#define S3C2410_GPE0_OUTP (0x01 << 0)
#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
#define S3C2410_GPE0_MASK (0x03 << 0)
#define S3C2410_GPE1_INP (0x00 << 2)
#define S3C2410_GPE1_OUTP (0x01 << 2)
#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
#define S3C2410_GPE1_MASK (0x03 << 2)
#define S3C2410_GPE2_INP (0x00 << 4)
#define S3C2410_GPE2_OUTP (0x01 << 4)
#define S3C2410_GPE2_CDCLK (0x02 << 4)
#define S3C2410_GPE3_INP (0x00 << 6)
#define S3C2410_GPE3_OUTP (0x01 << 6)
#define S3C2410_GPE3_I2SSDI (0x02 << 6)
#define S3C2410_GPE3_MASK (0x03 << 6)
#define S3C2410_GPE4_INP (0x00 << 8)
#define S3C2410_GPE4_OUTP (0x01 << 8)
#define S3C2410_GPE4_I2SSDO (0x02 << 8)
#define S3C2410_GPE4_MASK (0x03 << 8)
#define S3C2410_GPE5_INP (0x00 << 10)
#define S3C2410_GPE5_OUTP (0x01 << 10)
#define S3C2410_GPE5_SDCLK (0x02 << 10)
#define S3C2410_GPE6_INP (0x00 << 12)
#define S3C2410_GPE6_OUTP (0x01 << 12)
#define S3C2410_GPE6_SDCLK (0x02 << 12)
#define S3C2410_GPE7_INP (0x00 << 14)
#define S3C2410_GPE7_OUTP (0x01 << 14)
#define S3C2410_GPE7_SDCMD (0x02 << 14)
#define S3C2410_GPE8_INP (0x00 << 16)
#define S3C2410_GPE8_OUTP (0x01 << 16)
#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
#define S3C2410_GPE9_INP (0x00 << 18)
#define S3C2410_GPE9_OUTP (0x01 << 18)
#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
#define S3C2410_GPE10_INP (0x00 << 20)
#define S3C2410_GPE10_OUTP (0x01 << 20)
#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
#define S3C2410_GPE11_INP (0x00 << 22)
#define S3C2410_GPE11_OUTP (0x01 << 22)
#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
#define S3C2410_GPE12_INP (0x00 << 24)
#define S3C2410_GPE12_OUTP (0x01 << 24)
#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
#define S3C2410_GPE13_INP (0x00 << 26)
#define S3C2410_GPE13_OUTP (0x01 << 26)
#define S3C2410_GPE13_SPICLK0 (0x02 << 26)
#define S3C2410_GPE14_INP (0x00 << 28)
#define S3C2410_GPE14_OUTP (0x01 << 28)
#define S3C2410_GPE14_IICSCL (0x02 << 28)
#define S3C2410_GPE14_MASK (0x03 << 28)
#define S3C2410_GPE15_INP (0x00 << 30)
#define S3C2410_GPE15_OUTP (0x01 << 30)
#define S3C2410_GPE15_IICSDA (0x02 << 30)
#define S3C2410_GPE15_MASK (0x03 << 30)
#define S3C2410_GPE_PUPDIS(x) (1<<(x))
/* Port F consists of 8 GPIO/Special function
*
* GPIO / interrupt inputs
*
* GPFCON has 2 bits for each of the input pins on port F
* 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
*
* pull up works like all other ports.
*/
#define S3C2410_GPFCON S3C2410_GPIOREG(0x50)
#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
#define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
#define S3C2410_GPF0_INP (0x00 << 0)
#define S3C2410_GPF0_OUTP (0x01 << 0)
#define S3C2410_GPF0_EINT0 (0x02 << 0)
#define S3C2410_GPF1_INP (0x00 << 2)
#define S3C2410_GPF1_OUTP (0x01 << 2)
#define S3C2410_GPF1_EINT1 (0x02 << 2)
#define S3C2410_GPF2_INP (0x00 << 4)
#define S3C2410_GPF2_OUTP (0x01 << 4)
#define S3C2410_GPF2_EINT2 (0x02 << 4)
#define S3C2410_GPF3_INP (0x00 << 6)
#define S3C2410_GPF3_OUTP (0x01 << 6)
#define S3C2410_GPF3_EINT3 (0x02 << 6)
#define S3C2410_GPF4_INP (0x00 << 8)
#define S3C2410_GPF4_OUTP (0x01 << 8)
#define S3C2410_GPF4_EINT4 (0x02 << 8)
#define S3C2410_GPF5_INP (0x00 << 10)
#define S3C2410_GPF5_OUTP (0x01 << 10)
#define S3C2410_GPF5_EINT5 (0x02 << 10)
#define S3C2410_GPF6_INP (0x00 << 12)
#define S3C2410_GPF6_OUTP (0x01 << 12)
#define S3C2410_GPF6_EINT6 (0x02 << 12)
#define S3C2410_GPF7_INP (0x00 << 14)
#define S3C2410_GPF7_OUTP (0x01 << 14)
#define S3C2410_GPF7_EINT7 (0x02 << 14)
/* Port G consists of 8 GPIO/IRQ/Special function
*
* GPGCON has 2 bits for each of the input pins on port F
* 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
*
* pull up works like all other ports.
*/
#define S3C2410_GPGCON S3C2410_GPIOREG(0x60)
#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
#define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
#define S3C2410_GPG0_INP (0x00 << 0)
#define S3C2410_GPG0_OUTP (0x01 << 0)
#define S3C2410_GPG0_EINT8 (0x02 << 0)
#define S3C2410_GPG1_INP (0x00 << 2)
#define S3C2410_GPG1_OUTP (0x01 << 2)
#define S3C2410_GPG1_EINT9 (0x02 << 2)
#define S3C2410_GPG2_INP (0x00 << 4)
#define S3C2410_GPG2_OUTP (0x01 << 4)
#define S3C2410_GPG2_EINT10 (0x02 << 4)
#define S3C2410_GPG3_INP (0x00 << 6)
#define S3C2410_GPG3_OUTP (0x01 << 6)
#define S3C2410_GPG3_EINT11 (0x02 << 6)
#define S3C2410_GPG4_INP (0x00 << 8)
#define S3C2410_GPG4_OUTP (0x01 << 8)
#define S3C2410_GPG4_EINT12 (0x02 << 8)
#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
#define S3C2410_GPG5_INP (0x00 << 10)
#define S3C2410_GPG5_OUTP (0x01 << 10)
#define S3C2410_GPG5_EINT13 (0x02 << 10)
#define S3C2410_GPG5_SPIMISO1 (0x03 << 10)
#define S3C2410_GPG6_INP (0x00 << 12)
#define S3C2410_GPG6_OUTP (0x01 << 12)
#define S3C2410_GPG6_EINT14 (0x02 << 12)
#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
#define S3C2410_GPG7_INP (0x00 << 14)
#define S3C2410_GPG7_OUTP (0x01 << 14)
#define S3C2410_GPG7_EINT15 (0x02 << 14)
#define S3C2410_GPG7_SPICLK1 (0x03 << 14)
#define S3C2410_GPG8_INP (0x00 << 16)
#define S3C2410_GPG8_OUTP (0x01 << 16)
#define S3C2410_GPG8_EINT16 (0x02 << 16)
#define S3C2410_GPG9_INP (0x00 << 18)
#define S3C2410_GPG9_OUTP (0x01 << 18)
#define S3C2410_GPG9_EINT17 (0x02 << 18)
#define S3C2410_GPG10_INP (0x00 << 20)
#define S3C2410_GPG10_OUTP (0x01 << 20)
#define S3C2410_GPG10_EINT18 (0x02 << 20)
#define S3C2410_GPG11_INP (0x00 << 22)
#define S3C2410_GPG11_OUTP (0x01 << 22)
#define S3C2410_GPG11_EINT19 (0x02 << 22)
#define S3C2410_GPG11_TCLK1 (0x03 << 22)
#define S3C2410_GPG12_INP (0x00 << 24)
#define S3C2410_GPG12_OUTP (0x01 << 24)
#define S3C2410_GPG12_EINT18 (0x02 << 24)
#define S3C2410_GPG12_XMON (0x03 << 24)
#define S3C2410_GPG13_INP (0x00 << 26)
#define S3C2410_GPG13_OUTP (0x01 << 26)
#define S3C2410_GPG13_EINT18 (0x02 << 26)
#define S3C2410_GPG13_nXPON (0x03 << 26)
#define S3C2410_GPG14_INP (0x00 << 28)
#define S3C2410_GPG14_OUTP (0x01 << 28)
#define S3C2410_GPG14_EINT18 (0x02 << 28)
#define S3C2410_GPG14_YMON (0x03 << 28)
#define S3C2410_GPG15_INP (0x00 << 30)
#define S3C2410_GPG15_OUTP (0x01 << 30)
#define S3C2410_GPG15_EINT18 (0x02 << 30)
#define S3C2410_GPG15_nYPON (0x03 << 30)
#define S3C2410_GPG_PUPDIS(x) (1<<(x))
/* Port H consists of11 GPIO/serial/Misc pins
*
* GPGCON has 2 bits for each of the input pins on port F
* 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
*
* pull up works like all other ports.
*/
#define S3C2410_GPHCON S3C2410_GPIOREG(0x70)
#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
#define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
#define S3C2410_GPH0_INP (0x00 << 0)
#define S3C2410_GPH0_OUTP (0x01 << 0)
#define S3C2410_GPH0_nCTS0 (0x02 << 0)
#define S3C2410_GPH1_INP (0x00 << 2)
#define S3C2410_GPH1_OUTP (0x01 << 2)
#define S3C2410_GPH1_nRTS0 (0x02 << 2)
#define S3C2410_GPH2_INP (0x00 << 4)
#define S3C2410_GPH2_OUTP (0x01 << 4)
#define S3C2410_GPH2_TXD0 (0x02 << 4)
#define S3C2410_GPH3_INP (0x00 << 6)
#define S3C2410_GPH3_OUTP (0x01 << 6)
#define S3C2410_GPH3_RXD0 (0x02 << 6)
#define S3C2410_GPH4_INP (0x00 << 8)
#define S3C2410_GPH4_OUTP (0x01 << 8)
#define S3C2410_GPH4_TXD1 (0x02 << 8)
#define S3C2410_GPH5_INP (0x00 << 10)
#define S3C2410_GPH5_OUTP (0x01 << 10)
#define S3C2410_GPH5_RXD1 (0x02 << 10)
#define S3C2410_GPH6_INP (0x00 << 12)
#define S3C2410_GPH6_OUTP (0x01 << 12)
#define S3C2410_GPH6_TXD2 (0x02 << 12)
#define S3C2410_GPH6_nRTS1 (0x03 << 12)
#define S3C2410_GPH7_INP (0x00 << 14)
#define S3C2410_GPH7_OUTP (0x01 << 14)
#define S3C2410_GPH7_RXD2 (0x02 << 14)
#define S3C2410_GPH7_nCTS1 (0x03 << 14)
#define S3C2410_GPH8_INP (0x00 << 16)
#define S3C2410_GPH8_OUTP (0x01 << 16)
#define S3C2410_GPH8_UCLK (0x02 << 16)
#define S3C2410_GPH9_INP (0x00 << 18)
#define S3C2410_GPH9_OUTP (0x01 << 18)
#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
#define S3C2410_GPH10_INP (0x00 << 20)
#define S3C2410_GPH10_OUTP (0x01 << 20)
#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
/* miscellaneous control */
#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
/* see clock.h for dclk definitions */
/* pullup control on databus */
#define S3C2410_MISCCR_SPUCR_HEN (0)
#define S3C2410_MISCCR_SPUCR_HDIS (1<<0)
#define S3C2410_MISCCR_SPUCR_LEN (0)
#define S3C2410_MISCCR_SPUCR_LDIS (1<<1)
#define S3C2410_MISCCR_USBDEV (0)
#define S3C2410_MISCCR_USBHOST (1<<3)
#define S3C2410_MISCCR_CLK0_MPLL (0<<4)
#define S3C2410_MISCCR_CLK0_UPLL (1<<4)
#define S3C2410_MISCCR_CLK0_FCLK (2<<4)
#define S3C2410_MISCCR_CLK0_HCLK (3<<4)
#define S3C2410_MISCCR_CLK0_PCLK (4<<4)
#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
#define S3C2410_MISCCR_CLK1_MPLL (0<<8)
#define S3C2410_MISCCR_CLK1_UPLL (1<<8)
#define S3C2410_MISCCR_CLK1_FCLK (2<<8)
#define S3C2410_MISCCR_CLK1_HCLK (3<<8)
#define S3C2410_MISCCR_CLK1_PCLK (4<<8)
#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
#define S3C2410_MISCCR_nRSTCON (1<<16)
/* external interrupt control... */
/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
* S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
* S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
*
* note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
*
* Samsung datasheet p9-25
*/
#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)
#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
/* values for S3C2410_EXTINT0/1/2 */
#define S3C2410_EXTINT_LOWLEV (0x00)
#define S3C2410_EXTINT_HILEV (0x01)
#define S3C2410_EXTINT_FALLEDGE (0x02)
#define S3C2410_EXTINT_RISEEDGE (0x04)
#define S3C2410_EXTINT_BOTHEDGE (0x06)
/* interrupt filtering conrrol for EINT16..EINT23 */
#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)
#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)
/* mask: 0=enable, 1=disable
* 1 bit EINT, 4=EINT4, 23=EINT23
* EINT0,1,2,3 are not handled here.
*/
#define S3C2410_EINTMASK S3C2410_GPIOREG(0xA4)
#define S3C2410_EINTPEND S3C2410_GPIOREG(0xA8)
/* GSTATUS have miscellaneous information in them
*
*/
#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)
#define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0)
#define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4)
#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)
#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)
#define S3C2410_GSTATUS0_nWAIT (1<<3)
#define S3C2410_GSTATUS0_NCON (1<<2)
#define S3C2410_GSTATUS0_RnB (1<<1)
#define S3C2410_GSTATUS0_nBATTFLT (1<<0)
#define S3C2410_GSTATUS2_WTRESET (1<<2)
#define S3C2410_GSTATUs2_OFFRESET (1<<1)
#define S3C2410_GSTATUS2_PONRESET (1<<0)
#endif /* __ASM_ARCH_REGS_GPIO_H */
include/asm-arm/arch-s3c2410/regs-iis.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm/arch-s3c2410/regs-iis.h
*
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2410 IIS register definition
*
* Changelog:
* 19-06-2003 BJD Created file
* 26-06-2003 BJD Finished off definitions for register addresses
* 12-03-2004 BJD Updated include protection
*/
#ifndef __ASM_ARCH_REGS_IIS_H
#define __ASM_ARCH_REGS_IIS_H
#define S3C2410_IISCON (S3C2410_VA_IIS + 0x00)
#define S3C2410_IISCON_LRINDEX (1<<8)
#define S3C2410_IISCON_TXFIFORDY (1<<7)
#define S3C2410_IISCON_RXFIFORDY (1<<6)
#define S3C2410_IISCON_TXDMAEN (1<<5)
#define S3C2410_IISCON_RXDMAEN (1<<4)
#define S3C2410_IISCON_TXIDLE (1<<3)
#define S3C2410_IISCON_RXIDLE (1<<2)
#define S3C2410_IISCON_IISEN (1<<0)
#define S3C2410_IISMOD (S3C2410_VA_IIS + 0x04)
#define S3C2410_IISMOD_SLAVE (1<<8)
#define S3C2410_IISMOD_NOXFER (0<<6)
#define S3C2410_IISMOD_RXMODE (1<<6)
#define S3C2410_IISMOD_TXMODE (2<<6)
#define S3C2410_IISMOD_TXRXMODE (3<<6)
#define S3C2410_IISMOD_LR_LLOW (0<<5)
#define S3C2410_IISMOD_LR_RLOW (1<<5)
#define S3C2410_IISMOD_IIS (0<<4)
#define S3C2410_IISMOD_MSB (1<<4)
#define S3C2410_IISMOD_8BIT (0<<3)
#define S3C2410_IISMOD_16BIT (1<<3)
#define S3C2410_IISMOD_256FS (0<<1)
#define S3C2410_IISMOD_384FS (1<<1)
#define S3C2410_IISMOD_16FS (0<<0)
#define S3C2410_IISMOD_32FS (1<<0)
#define S3C2410_IISMOD_48FS (2<<0)
#define S3C2410_IISPSR (S3C2410_VA_IIS + 0x08)
#define S3C2410_IISFCON (S3C2410_VA_IIS + 0x0c)
#define S3C2410_IISFCON_TXDMA (1<<15)
#define S3C2410_IISFCON_RXDMA (1<<14)
#define S3C2410_IISFCON_TXENABLE (1<<13)
#define S3C2410_IISFCON_RXENABLE (1<<12)
#define S3C2410_IISFIFO (S3C2410_VA_IIS + 0x10)
#endif /* __ASM_ARCH_REGS_IIS_H */
include/asm-arm/arch-s3c2410/regs-irq.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm/arch-s3c2410/regs-irq.h
*
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*
*
* Changelog:
* 19-06-2003 BJD Created file
* 12-03-2004 BJD Updated include protection
*/
#ifndef ___ASM_ARCH_REGS_IRQ_H
#define ___ASM_ARCH_REGS_IRQ_H "$Id: irq.h,v 1.3 2003/03/25 21:29:06 ben Exp $"
/* interrupt controller */
#define S3C2410_IRQREG(x) ((x) + S3C2410_VA_IRQ)
#define S3C2410_EINTREG(x) ((x) + S3C2410_VA_GPIO)
#define S3C2410_SRCPND S3C2410_IRQREG(0x000)
#define S3C2410_INTMOD S3C2410_IRQREG(0x004)
#define S3C2410_INTMSK S3C2410_IRQREG(0x008)
#define S3C2410_PRIORITY S3C2410_IRQREG(0x00C)
#define S3C2410_INTPND S3C2410_IRQREG(0x010)
#define S3C2410_INTOFFSET S3C2410_IRQREG(0x014)
#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018)
#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C)
#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4)
#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8)
#endif /* ___ASM_ARCH_REGS_IRQ_H */
include/asm-arm/arch-s3c2410/regs-lcd.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm/arch-s3c2410/regs-lcd.h
*
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*
*
* Changelog:
* 12-06-2003 BJD Created file
* 26-06-2003 BJD Updated LCDCON register definitions
* 12-03-2004 BJD Updated include protection
*/
#ifndef ___ASM_ARCH_REGS_LCD_H
#define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $"
#define S3C2410_LCDREG(x) ((x) + S3C2410_VA_LCD)
/* LCD control registers */
#define S3C2410_LCDCON1 S3C2410_LCDREG(0x00)
#define S3C2410_LCDCON2 S3C2410_LCDREG(0x04)
#define S3C2410_LCDCON3 S3C2410_LCDREG(0x08)
#define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C)
#define S3C2410_LCDCON5 S3C2410_LCDREG(0x10)
#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8)
#define S3C2410_LCDCON1_MMODE (1<<6)
#define S3C2410_LCDCON1_DSCAN4 (0<<5)
#define S3C2410_LCDCON1_STN4 (1<<5)
#define S3C2410_LCDCON1_STN8 (2<<5)
#define S3C2410_LCDCON1_TFT (3<<5)
#define S3C2410_LCDCON1_STN1BPP (0<<1)
#define S3C2410_LCDCON1_STN2GREY (1<<1)
#define S3C2410_LCDCON1_STN4GREY (2<<1)
#define S3C2410_LCDCON1_STN8BPP (3<<1)
#define S3C2410_LCDCON1_STN12BPP (4<<1)
#define S3C2410_LCDCON1_TFT1BPP (8<<1)
#define S3C2410_LCDCON1_TFT2BPP (9<<1)
#define S3C2410_LCDCON1_TFT4BPP (10<<1)
#define S3C2410_LCDCON1_TFT8BPP (11<<1)
#define S3C2410_LCDCON1_TFT16BPP (12<<1)
#define S3C2410_LCDCON1_TFT24BPP (13<<1)
#define S3C2410_LCDCON1_ENVDI (1)
#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
#define S3C2410_LCDCON3_HBPD(x) ((x) << 25)
#define S3C2410_LCDCON3_WDLY(x) ((x) << 25)
#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
#define S3C2410_LCDCON5_BPP24BL (1<<12)
#define S3C2410_LCDCON5_FRM565 (1<<11)
#define S3C2410_LCDCON5_INVVCLK (1<<10)
#define S3C2410_LCDCON5_INVVLINE (1<<9)
#define S3C2410_LCDCON5_INVVFRAME (1<<8)
#define S3C2410_LCDCON5_INVVD (1<<7)
#define S3C2410_LCDCON5_INVVDEN (1<<6)
#define S3C2410_LCDCON5_INVPWREN (1<<5)
#define S3C2410_LCDCON5_INVLEND (1<<4)
#define S3C2410_LCDCON5_PWREN (1<<3)
#define S3C2410_LCDCON5_ENLEND (1<<2)
#define S3C2410_LCDCON5_BSWP (1<<1)
#define S3C2410_LCDCON5_HWSWP (1<<0)
/* framebuffer start addressed */
#define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14)
#define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18)
#define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C)
/* colour lookup and miscellaneous controls */
#define S3C2410_REDLUT S3C2410_LCDREG(0x20)
#define S3C2410_GREENLUT S3C2410_LCDREG(0x24)
#define S3C2410_BLUELUT S3C2410_LCDREG(0x28)
#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C)
#define S3C2410_TPAL S3C2410_LCDREG(0x50)
/* interrupt info */
#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54)
#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58)
#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C)
#define S3C2410_LPCSEL S3C2410_LCDREG(0x60)
#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4))
#endif /* ___ASM_ARCH_REGS_LCD_H */
include/asm-arm/arch-s3c2410/regs-rtc.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm/arch-s3c2410/regs-rtc.h
*
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2410 Internal RTC register definition
*
* Changelog:
* 19-06-2003 BJD Created file
* 12-03-2004 BJD Updated include protection
*/
#ifndef __ASM_ARCH_REGS_RTC_H
#define __ASM_ARCH_REGS_RTC_H __FILE__
#define S3C2410_RTCREG(x) ((x) + S3C2410_VA_RTC)
#define S3C2410_RTCCON S3C2410_RTCREG(0x40)
#define S3C2410_RTCCON_RTCEN (1<<0)
#define S3C2410_RTCCON_CLKRST (1<<3)
#define S3C2410_TICNT S3C2410_RTCREG(0x44)
#define S3C2410_TICNT_ENABLE (1<<7)
#define S3C2410_RTCALM S3C2410_RTCREG(0x50)
#define S3C2410_RTCALM_ALMEN (1<<6)
#define S3C2410_RTCALM_YEAREN (1<<5)
#define S3C2410_RTCALM_MONEN (1<<4)
#define S3C2410_RTCALM_DAYEN (1<<3)
#define S3C2410_RTCALM_HOUREN (1<<2)
#define S3C2410_RTCALM_MINEN (1<<1)
#define S3C2410_RTCALM_SECEN (1<<0)
#define S3C2410_RTCALM_ALL \
S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
S3C2410_RTCALM_SECEN
#define S3C2410_ALMSEC S3C2410_RTCREG(0x54)
#define S3C2410_ALMMIN S3C2410_RTCREG(0x58)
#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c)
#define S3C2410_ALMDATE S3C2410_RTCREG(0x60)
#define S3C2410_ALMMON S3C2410_RTCREG(0x64)
#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68)
#define S3C2410_RTCRST S3C2410_RTCREG(0x6c)
#define S3C2410_RTCSEC S3C2410_RTCREG(0x70)
#define S3C2410_RTCMIN S3C2410_RTCREG(0x74)
#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78)
#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c)
#define S3C2410_RTCDAY S3C2410_RTCREG(0x80)
#define S3C2410_RTCMON S3C2410_RTCREG(0x84)
#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88)
#endif /* __ASM_ARCH_REGS_RTC_H */
include/asm-arm/arch-s3c2410/regs-serial.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/regs-serial.h
*
* From linux/include/asm-arm/hardware/serial_s3c2410.h
*
* Internal header file for Samsung S3C2410 serial ports (UART0-2)
*
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
*
* Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
*
* Adapted from:
*
* Internal header file for MX1ADS serial ports (UART1 & 2)
*
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_REGS_SERIAL_H
#define __ASM_ARM_REGS_SERIAL_H
#define S3C2410_VA_UART0 (S3C2410_VA_UART)
#define S3C2410_VA_UART1 (S3C2410_VA_UART + 0x4000 )
#define S3C2410_VA_UART2 (S3C2410_VA_UART + 0x8000 )
#define S3C2410_PA_UART0 (S3C2410_PA_UART)
#define S3C2410_PA_UART1 (S3C2410_PA_UART + 0x4000 )
#define S3C2410_PA_UART2 (S3C2410_PA_UART + 0x8000 )
#define S3C2410_URXH (0x24)
#define S3C2410_UTXH (0x20)
#define S3C2410_ULCON (0x00)
#define S3C2410_UCON (0x04)
#define S3C2410_UFCON (0x08)
#define S3C2410_UMCON (0x0C)
#define S3C2410_UBRDIV (0x28)
#define S3C2410_UTRSTAT (0x10)
#define S3C2410_UERSTAT (0x14)
#define S3C2410_UFSTAT (0x18)
#define S3C2410_UMSTAT (0x1C)
#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
#define S3C2410_LCON_CS5 (0x0)
#define S3C2410_LCON_CS6 (0x1)
#define S3C2410_LCON_CS7 (0x2)
#define S3C2410_LCON_CS8 (0x3)
#define S3C2410_LCON_CSMASK (0x3)
#define S3C2410_LCON_PNONE (0x0)
#define S3C2410_LCON_PEVEN (0x5 << 3)
#define S3C2410_LCON_PODD (0x4 << 3)
#define S3C2410_LCON_PMASK (0x7 << 3)
#define S3C2410_LCON_STOPB (1<<2)
#define S3C2410_UCON_UCLK (1<<10)
#define S3C2410_UCON_SBREAK (1<<4)
#define S3C2410_UCON_TXILEVEL (1<<9)
#define S3C2410_UCON_RXILEVEL (1<<8)
#define S3C2410_UCON_TXIRQMODE (1<<2)
#define S3C2410_UCON_RXIRQMODE (1<<0)
#define S3C2410_UCON_RXFIFO_TOI (1<<7)
#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL \
| S3C2410_UCON_TXIRQMODE | S3C2410_UCON_RXIRQMODE \
| S3C2410_UCON_RXFIFO_TOI)
#define S3C2410_UFCON_FIFOMODE (1<<0)
#define S3C2410_UFCON_TXTRIG0 (0<<6)
#define S3C2410_UFCON_RXTRIG8 (1<<4)
#define S3C2410_UFCON_RXTRIG12 (2<<4)
#define S3C2410_UFCON_RESETBOTH (3<<1)
#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | S3C2410_UFCON_TXTRIG0 \
| S3C2410_UFCON_RXTRIG8 )
#define S3C2410_UFSTAT_TXFULL (1<<9)
#define S3C2410_UFSTAT_RXFULL (1<<8)
#define S3C2410_UFSTAT_TXMASK (15<<4)
#define S3C2410_UFSTAT_TXSHIFT (4)
#define S3C2410_UFSTAT_RXMASK (15<<0)
#define S3C2410_UFSTAT_RXSHIFT (0)
#define S3C2410_UTRSTAT_TXFE (1<<1)
#define S3C2410_UTRSTAT_RXDR (1<<0)
#define S3C2410_UERSTAT_OVERRUN (1<<0)
#define S3C2410_UERSTAT_FRAME (1<<2)
#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | S3C2410_UERSTAT_FRAME)
/* fifo size information */
#define S3C2410_UFCON_RXC(fcon) (((fcon) & S3C2410_UFSTAT_RXMASK) >> S3C2410_UFSTAT_RXSHIFT)
#define S3C2410_UFCON_TXC(fcon) (((fcon) & S3C2410_UFSTAT_TXMASK) >> S3C2410_UFSTAT_TXSHIFT)
#define S3C2410_UMSTAT_CTS (1<<0)
#define S3C2410_UMSTAT_DeltaCTS (1<<2)
#ifndef __ASSEMBLY__
/* configuration structure for per-machine configurations for the
* serial port
*
* the pointer is setup by the machine specific initialisation from the
* arch/arm/mach-s3c2410/ directory.
*/
struct s3c2410_uartcfg {
unsigned char hwport; /* hardware port number */
unsigned char unused;
unsigned short flags;
unsigned long *clock; /* pointer to clock rate */
unsigned long ucon; /* value of ucon for port */
unsigned long ulcon; /* value of ulcon for port */
unsigned long ufcon; /* value of ufcon for port */
};
extern struct s3c2410_uartcfg *s3c2410_uartcfgs;
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARM_REGS_SERIAL_H */
include/asm-arm/arch-s3c2410/regs-timer.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm/arch-s3c2410/regs-timer.h
*
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2410 Timer configuration
*
* Changelog:
* 05-06-2003 BJD Created file
* 26-06-2003 BJD Added more timer definitions to mux / control
* 12-03-2004 BJD Updated include protection
*/
#ifndef __ASM_ARCH_REGS_TIMER_H
#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
#define S3C2410_TIMERREG(x) (S3C2410_VA_TIMER + (x))
#define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c))
#define S3C2410_TCFG0 S3C2410_TIMERREG(0x00)
#define S3C2410_TCFG1 S3C2410_TIMERREG(0x04)
#define S3C2410_TCON S3C2410_TIMERREG(0x08)
#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
#define S3C2410_TCFG1_MUX4_DIV2 (0<<16)
#define S3C2410_TCFG1_MUX4_DIV4 (1<<16)
#define S3C2410_TCFG1_MUX4_DIV8 (2<<16)
#define S3C2410_TCFG1_MUX4_DIV16 (3<<16)
#define S3C2410_TCFG1_MUX4_TCLK1 (4<<16)
#define S3C2410_TCFG1_MUX4_MASK (15<<16)
#define S3C2410_TCFG1_MUX3_DIV2 (0<<12)
#define S3C2410_TCFG1_MUX3_DIV4 (1<<12)
#define S3C2410_TCFG1_MUX3_DIV8 (2<<12)
#define S3C2410_TCFG1_MUX3_DIV16 (3<<12)
#define S3C2410_TCFG1_MUX3_TCLK1 (4<<12)
#define S3C2410_TCFG1_MUX3_MASK (15<<12)
#define S3C2410_TCFG1_MUX2_DIV2 (0<<8)
#define S3C2410_TCFG1_MUX2_DIV4 (1<<8)
#define S3C2410_TCFG1_MUX2_DIV8 (2<<8)
#define S3C2410_TCFG1_MUX2_DIV16 (3<<8)
#define S3C2410_TCFG1_MUX2_TCLK1 (4<<8)
#define S3C2410_TCFG1_MUX2_MASK (15<<8)
#define S3C2410_TCFG1_MUX1_DIV2 (0<<4)
#define S3C2410_TCFG1_MUX1_DIV4 (1<<4)
#define S3C2410_TCFG1_MUX1_DIV8 (2<<4)
#define S3C2410_TCFG1_MUX1_DIV16 (3<<4)
#define S3C2410_TCFG1_MUX1_TCLK0 (4<<4)
#define S3C2410_TCFG1_MUX1_MASK (15<<4)
#define S3C2410_TCFG1_MUX0_DIV2 (0<<0)
#define S3C2410_TCFG1_MUX0_DIV4 (1<<0)
#define S3C2410_TCFG1_MUX0_DIV8 (2<<0)
#define S3C2410_TCFG1_MUX0_DIV16 (3<<0)
#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0)
#define S3C2410_TCFG1_MUX0_MASK (15<<0)
/* for each timer, we have an count buffer, an compare buffer and
* an observation buffer
*/
/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
#define S3C2410_TCNTB(tmr) S3C2410_TIMERREG2(tmr, 0x00)
#define S3C2410_TCMPB(tmr) S3C2410_TIMERREG2(tmr, 0x04)
#define S3C2410_TCNTO(tmr) S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
#define S3C2410_TCON_T4RELOAD (1<<22)
#define S3C2410_TCON_T4MANUALUPD (1<<21)
#define S3C2410_TCON_T4START (1<<20)
#define S3C2410_TCON_T3RELOAD (1<<19)
#define S3C2410_TCON_T3INVERT (1<<18)
#define S3C2410_TCON_T3MANUALUPD (1<<17)
#define S3C2410_TCON_T3START (1<<16)
#define S3C2410_TCON_T2RELOAD (1<<15)
#define S3C2410_TCON_T2INVERT (1<<14)
#define S3C2410_TCON_T2MANUALUPD (1<<13)
#define S3C2410_TCON_T2START (1<<12)
#define S3C2410_TCON_T1RELOAD (1<<11)
#define S3C2410_TCON_T1INVERT (1<<10)
#define S3C2410_TCON_T1MANUALUPD (1<<9)
#define S3C2410_TCON_T1START (1<<8)
#define S3C2410_TCON_T0DEADZONE (1<<4)
#define S3C2410_TCON_T0RELOAD (1<<3)
#define S3C2410_TCON_T0INVERT (1<<2)
#define S3C2410_TCON_T0MANUALUPD (1<<1)
#define S3C2410_TCON_T0START (1<<0)
#endif /* __ASM_ARCH_REGS_TIMER_H */
include/asm-arm/arch-s3c2410/regs-watchdog.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm/arch-s3c2410/regs0watchdog.h
*
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2410 Watchdog timer control
*
* Changelog:
* 21-06-2003 BJD Created file
* 12-03-2004 BJD Updated include protection
*/
#ifndef __ASM_ARCH_REGS_WATCHDOG_H
#define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
#define S3C2410_WDOGREG(x) ((x) + S3C2410_VA_WATCHDOG)
#define S3C2410_WTCON S3C2410_WDOGREG(0x00)
#define S3C2410_WTDAT S3C2410_WDOGREG(0x04)
#define S3C2410_WTCNT S3C2410_WDOGREG(0x08)
/* the watchdog can either generate a reset pulse, or an
* interrupt.
*/
#define S3C2410_WTCON_RSTEN (0x01)
#define S3C2410_WTCON_INTEN (1<<2)
#define S3C2410_WTCON_ENABLE (1<<5)
#define S3C2410_WTCON_DIV16 (0<<3)
#define S3C2410_WTCON_DIV32 (1<<3)
#define S3C2410_WTCON_DIV64 (2<<3)
#define S3C2410_WTCON_DIV128 (3<<3)
#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
include/asm-arm/arch-s3c2410/serial.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/serial.h
*
* (c) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - serial port definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 03-Sep-2003 BJD Created file
* 19-Mar-2004 BJD Removed serial port definitions, inserted elsewhere
*/
#ifndef __ASM_ARCH_SERIAL_H
#define __ASM_ARCH_SERIAL_H
/* Standard COM flags */
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
#define BASE_BAUD ( 1843200 / 16 )
#define STD_SERIAL_PORT_DEFNS
#define EXTRA_SERIAL_PORT_DEFNS
#endif /* __ASM_ARCH_SERIAL_H */
include/asm-arm/arch-s3c2410/system.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/system.h
*
* (c) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - System function defines and includes
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 12-May-2003 BJD Created file
* 14-May-2003 BJD Removed idle to aid debugging
* 12-Jun-2003 BJD Added reset via watchdog
* 04-Sep-2003 BJD Moved to v2.6
*/
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/arch/map.h>
#include <asm/arch/regs-watchdog.h>
#include <asm/arch/regs-clock.h>
extern void printascii(const char *);
void
arch_idle(void)
{
//unsigned long reg = S3C2410_CLKCON;
//printascii("arch_idle:\n");
/* idle the system by using the idle mode which will wait for an
* interrupt to happen before restarting the system.
*/
/* going into idle state upsets the jtag, so don't do it
* at the moment */
#if 0
__raw_writel(__raw_readl(reg) | (1<<2), reg);
/* the samsung port seems to do a loop and then unset idle.. */
for (i = 0; i < 50; i++) {
tmp = __raw_readl(reg); /* ensure loop not optimised out */
}
//printascii("arch_idle: done\n");
__raw_writel(__raw_readl(reg) & ~(1<<2), reg);
#endif
}
static void
arch_reset(char mode)
{
if (mode == 's') {
cpu_reset(0);
}
printk("arch_reset: attempting watchdog reset\n");
__raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
/* put initial values into count and data */
__raw_writel(0x100, S3C2410_WTCNT);
__raw_writel(0x100, S3C2410_WTDAT);
/* set the watchdog to go and reset... */
__raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
/* wait for reset to assert... */
mdelay(5000);
panic("Watchdog reset failed to assert reset\n");
/* we'll take a jump through zero as a poor second */
cpu_reset(0);
}
include/asm-arm/arch-s3c2410/time.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/time.h
*
* Copyright (C) 2003 Simtec Electronics <linux@simtec.co.uk>
* Ben Dooks, <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <asm/system.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/arch/map.h>
#include <asm/arch/regs-timer.h>
extern unsigned long (*gettimeoffset)(void);
static unsigned long timer_startval;
static unsigned long timer_ticks_usec;
#ifdef CONFIG_S3C2410_RTC
extern void s3c2410_rtc_check();
#endif
/* with an 12MHz clock, we get 12 ticks per-usec
*/
/***
* Returns microsecond since last clock interrupt. Note that interrupts
* will have been disabled by do_gettimeoffset()
* IRQs are disabled before entering here from do_gettimeofday()
*/
static unsigned long s3c2410_gettimeoffset (void)
{
unsigned long tdone;
unsigned long usec;
/* work out how many ticks have gone since last timer interrupt */
tdone = timer_startval - __raw_readl(S3C2410_TCNTO(4));
/* currently, tcnt is in 12MHz units, but this may change
* for non-bast machines...
*/
usec = tdone / timer_ticks_usec;
return usec;
}
/*
* IRQ handler for the timer
*/
static irqreturn_t
s3c2410_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
do_leds();
do_timer(regs);
do_set_rtc();
//s3c2410_rtc_check();
do_profile(regs);
return IRQ_HANDLED;
}
/*
* Set up timer interrupt, and return the current time in seconds.
*/
/* currently we only use timer4, as it is the only timer which has no
* other function that can be exploited externally
*/
void __init time_init (void)
{
unsigned long tcon;
unsigned long tcnt;
unsigned long tcfg1;
unsigned long tcfg0;
gettimeoffset = s3c2410_gettimeoffset;
timer_irq.handler = s3c2410_timer_interrupt;
tcnt = 0xffff; /* default value for tcnt */
/* read the current timer configuration bits */
tcon = __raw_readl(S3C2410_TCON);
tcfg1 = __raw_readl(S3C2410_TCFG1);
tcfg0 = __raw_readl(S3C2410_TCFG0);
/* configure the system for whichever machine is in use */
if (machine_is_bast() || machine_is_vr1000()) {
timer_ticks_usec = 12; /* timer is at 12MHz */
tcnt = (timer_ticks_usec * (1000*1000)) / HZ;
}
/* for the h1940, we use the pclk from the core to generate
* the timer values. since 67.5MHz is not a value we can directly
* generate the timer value from, we need to pre-scale and
* divied before using it.
*
* overall divsior to get 200Hz is 337500
* we can fit tcnt if we pre-scale by 6, producing a tick rate
* of 11.25MHz, and a tcnt of 56250.
*/
if (machine_is_h1940()) {
timer_ticks_usec = s3c2410_pclk / (1000*1000);
timer_ticks_usec /= 6;
tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
tcfg1 |= S3C2410_TCFG1_MUX4_DIV2;
tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT;
tcnt = (s3c2410_pclk / 6) / HZ;
}
printk("setup_timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx\n",
tcon, tcnt, tcfg0, tcfg1);
/* check to see if timer is within 16bit range... */
if (tcnt > 0xffff) {
panic("setup_timer: HZ is too small, cannot configure timer!");
return;
}
__raw_writel(tcfg1, S3C2410_TCFG1);
__raw_writel(tcfg0, S3C2410_TCFG0);
timer_startval = tcnt;
__raw_writel(tcnt, S3C2410_TCNTB(4));
/* ensure timer is stopped... */
tcon &= ~(7<<20);
tcon |= S3C2410_TCON_T4RELOAD;
tcon |= S3C2410_TCON_T4MANUALUPD;
__raw_writel(tcon, S3C2410_TCON);
__raw_writel(tcnt, S3C2410_TCNTB(4));
__raw_writel(tcnt, S3C2410_TCMPB(4));
setup_irq(IRQ_TIMER4, &timer_irq);
/* start the timer running */
tcon |= S3C2410_TCON_T4START;
tcon &= ~S3C2410_TCON_T4MANUALUPD;
__raw_writel(tcon, S3C2410_TCON);
}
include/asm-arm/arch-s3c2410/timex.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/timex.h
*
* (c) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - time parameters
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 02-Sep-2003 BJD Created file
* 05-Jan-2004 BJD Updated for Linux 2.6.0
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
#if 0
/* todo - this does not seem to work with 2.6.0 -> division by zero
* in header files
*/
extern int s3c2410_clock_tick_rate;
#define CLOCK_TICK_RATE (s3c2410_clock_tick_rate)
#endif
/* currently, the BAST uses 24MHz as a base clock rate */
#define CLOCK_TICK_RATE 24000000
#endif /* __ASM_ARCH_TIMEX_H */
include/asm-arm/arch-s3c2410/uncompress.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/uncompress.h
*
* (c) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - uncompress code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 22-May-2003 BJD Created
* 08-Sep-2003 BJD Moved to linux v2.6
* 12-Mar-2004 BJD Updated header protection
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
/* defines for UART registers */
#include "asm/arch/regs-serial.h"
#include <asm/arch/map.h>
/* how many bytes we allow into the FIFO at a time in FIFO mode */
#define FIFO_MAX (14)
#if 1
#define uart_base S3C2410_PA_UART
#else
static unsigned int uart_base = S3C2410_PA_UART;
#endif
static __inline__ void
uart_wr(unsigned int reg, unsigned int val)
{
volatile unsigned int *ptr;
ptr = (volatile unsigned int *)(reg + uart_base);
*ptr = val;
}
static __inline__ unsigned int
uart_rd(unsigned int reg)
{
volatile unsigned int *ptr;
ptr = (volatile unsigned int *)(reg + uart_base);
return *ptr;
}
/* currently we do not need the watchdog... */
#define arch_decomp_wdog()
static void error(char *err);
static void
arch_decomp_setup(void)
{
/* we may need to setup the uart(s) here if we are not running
* on an BAST... the BAST will have left the uarts configured
* after calling linux.
*/
}
/* we can deal with the case the UARTs are being run
* in FIFO mode, so that we don't hold up our execution
* waiting for tx to happen...
*/
static void
putc(char ch)
{
if (ch == '\n')
putc('\r'); /* expand newline to \r\n */
if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
int level;
while (1) {
level = uart_rd(S3C2410_UFSTAT);
level &= S3C2410_UFSTAT_TXMASK;
level >>= S3C2410_UFSTAT_TXSHIFT;
if (level < FIFO_MAX)
break;
}
} else {
/* not using fifos */
while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE) != S3C2410_UTRSTAT_TXFE);
}
/* write byte to transmission register */
uart_wr(S3C2410_UTXH, ch);
}
static void
puts(const char *ptr)
{
for (; *ptr != '\0'; ptr++) {
putc(*ptr);
}
}
#endif /* __ASM_ARCH_UNCOMPRESS_H */
include/asm-arm/arch-s3c2410/vmalloc.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/vmalloc.h
*
* from linux/include/asm-arm/arch-iop3xx/vmalloc.h
*
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2410 vmalloc definition
*
* Changelog:
* 12-Mar-2004 BJD Fixed header, added include protection
* 12=Mar-2004 BJD Fixed VMALLOC_END definitions
*/
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END (0xE0000000)
#define MODULE_START (PAGE_OFFSET - 16*1048576)
#define MODULE_END (PAGE_OFFSET)
#endif /* __ASM_ARCH_VMALLOC_H */
include/asm-arm/arch-s3c2410/vr1000-cpld.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/vr1000-cpld.h
*
* (c) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* VR1000 - CPLD control constants
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 25-May-2003 BJD Created file, added CTRL1 registers
* 19-Mar-2004 BJD Added VR1000 CPLD definitions
*/
#ifndef __ASM_ARCH_VR1000CPLD_H
#define __ASM_ARCH_VR1000CPLD_H
#define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
#endif /* __ASM_ARCH_VR1000CPLD_H */
include/asm-arm/arch-s3c2410/vr1000-irq.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/vr1000-irq.h
*
* (c) 2003,2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Machine VR1000 - IRQ Number definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 06-Jan-2003 BJD Linux 2.6.0 version
* 19-Mar-2004 BJD Updates for VR1000
*/
#ifndef __ASM_ARCH_VR1000IRQ_H
#define __ASM_ARCH_VR1000IRQ_H
/* irq numbers to onboard peripherals */
#define IRQ_USBOC IRQ_EINT19
#define IRQ_IDE0 IRQ_EINT16
#define IRQ_IDE1 IRQ_EINT17
#define IRQ_VR1000_SERIAL IRQ_EINT12
#define IRQ_VR1000_DM9000A IRQ_EINT10
#define IRQ_VR1000_DM9000N IRQ_EINT9
#define IRQ_SMALERT IRQ_EINT8
#endif /* __ASM_ARCH_VR1000IRQ_H */
include/asm-arm/arch-s3c2410/vr1000-map.h 0 → 100644
View file @ ae510d4c
/* linux/include/asm-arm/arch-s3c2410/vr1000-map.h
*
* (c) 2003,2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Machine VR1000 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 06-Jan-2003 BJD Linux 2.6.0 version, split specifics from arch/map.h
* 12-Mar-2004 BJD Fixed header include protection
* 19-Mar-2004 BJD Copied to VR1000 machine headers.
*/
/* needs arch/map.h including with this */
/* ok, we've used up to 0x13000000, now we need to find space for the
* peripherals that live in the nGCS[x] areas, which are quite numerous
* in their space. We also have the board's CPLD to find register space
* for.
*/
#ifndef __ASM_ARCH_VR1000MAP_H
#define __ASM_ARCH_VR1000MAP_H
#include <asm/arch/bast-map.h>
#define VR1000_IOADDR(x) BAST_IOADDR(x)
/* we put the CPLD registers next, to get them out of the way */
#define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
#define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
#define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
#define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
#define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
#define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
#define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
#define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
/* next, we have the PC104 ISA interrupt registers */
#define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
#define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000)
#define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
#define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000)
#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
/* 0xE0000000 contains the IO space that is split by speed and
* wether the access is for 8 or 16bit IO... this ensures that
* the correct access is made
*
* 0x10000000 of space, partitioned as so:
*
* 0x00000000 to 0x04000000 8bit, slow
* 0x04000000 to 0x08000000 16bit, slow
* 0x08000000 to 0x0C000000 16bit, net
* 0x0C000000 to 0x10000000 16bit, fast
*
* each of these spaces has the following in:
*
* 0x02000000 to 0x02100000 1MB IDE primary channel
* 0x02100000 to 0x02200000 1MB IDE primary channel aux
* 0x02200000 to 0x02400000 1MB IDE secondary channel
* 0x02300000 to 0x02400000 1MB IDE secondary channel aux
* 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers
* 0x02600000 to 0x02700000 1MB
*
* the phyiscal layout of the zones are:
* nGCS2 - 8bit, slow
* nGCS3 - 16bit, slow
* nGCS4 - 16bit, net
* nGCS5 - 16bit, fast
*/
#define VR1000_VA_MULTISPACE (0xE0000000)
#define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000)
#define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000)
#define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000)
#define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000)
#define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000)
#define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000)
#define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000)
#define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000)
#define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000)
/* physical offset addresses for the peripherals */
#define VR1000_PA_IDEPRI (0x02000000)
#define VR1000_PA_IDEPRIAUX (0x02800000)
#define VR1000_PA_IDESEC (0x03000000)
#define VR1000_PA_IDESECAUX (0x03800000)
#define VR1000_PA_DM9000 (0x05000000)
#define VR1000_PA_SERIAL (0x11800000)
/* some configurations for the peripherals */
#define VR1000_DM9000_CS VR1000_VAM_CS4
#endif /* __ASM_ARCH_VR1000MAP_H */
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