Commit af79ef72 authored by Andrey Smirnov's avatar Andrey Smirnov Committed by Shawn Guo

ARM: dts: vf610-zii-dev: Add QSPI node

Both rev C and rev B of the board come with two QSPI-NOR chips
attached to the SoC. Add DT code describing all of this.
Signed-off-by: default avatarAndrey Smirnov <andrew.smirnov@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 36b7ee5f
...@@ -177,6 +177,36 @@ &i2c2 { ...@@ -177,6 +177,36 @@ &i2c2 {
status = "okay"; status = "okay";
}; };
&qspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi0>;
status = "okay";
/*
* Attached MT25QL02 can go up to 90Mhz in DTR and 166 in STR
* modes, so, spi-max-frequency is limited to 90MHz
*/
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <90000000>;
spi-rx-bus-width = <4>;
reg = <0>;
m25p,fast-read;
};
flash@2 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <90000000>;
spi-rx-bus-width = <4>;
reg = <2>;
m25p,fast-read;
};
};
&uart0 { &uart0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>; pinctrl-0 = <&pinctrl_uart0>;
...@@ -360,12 +390,18 @@ VF610_PAD_PTD20__GPIO_74 0x31c2 ...@@ -360,12 +390,18 @@ VF610_PAD_PTD20__GPIO_74 0x31c2
pinctrl_qspi0: qspi0grp { pinctrl_qspi0: qspi0grp {
fsl,pins = < fsl,pins = <
VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3 VF610_PAD_PTD0__QSPI0_A_QSCK 0x38c2
VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff VF610_PAD_PTD1__QSPI0_A_CS0 0x38c2
VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3 VF610_PAD_PTD2__QSPI0_A_DATA3 0x38c3
VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3 VF610_PAD_PTD3__QSPI0_A_DATA2 0x38c3
VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3 VF610_PAD_PTD4__QSPI0_A_DATA1 0x38c3
VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3 VF610_PAD_PTD5__QSPI0_A_DATA0 0x38c3
VF610_PAD_PTD7__QSPI0_B_QSCK 0x38c2
VF610_PAD_PTD8__QSPI0_B_CS0 0x38c2
VF610_PAD_PTD9__QSPI0_B_DATA3 0x38c3
VF610_PAD_PTD10__QSPI0_B_DATA2 0x38c3
VF610_PAD_PTD11__QSPI0_B_DATA1 0x38c3
VF610_PAD_PTD12__QSPI0_B_DATA0 0x38c3
>; >;
}; };
......
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