Commit b134165e authored by Michael Ellerman's avatar Michael Ellerman

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux into fixes

Merge one commit from Scott which I missed while away.
parents 5d298baa a4e89ffb
...@@ -437,6 +437,7 @@ static inline int check_io_access(struct pt_regs *regs) ...@@ -437,6 +437,7 @@ static inline int check_io_access(struct pt_regs *regs)
int machine_check_e500mc(struct pt_regs *regs) int machine_check_e500mc(struct pt_regs *regs)
{ {
unsigned long mcsr = mfspr(SPRN_MCSR); unsigned long mcsr = mfspr(SPRN_MCSR);
unsigned long pvr = mfspr(SPRN_PVR);
unsigned long reason = mcsr; unsigned long reason = mcsr;
int recoverable = 1; int recoverable = 1;
...@@ -478,9 +479,16 @@ int machine_check_e500mc(struct pt_regs *regs) ...@@ -478,9 +479,16 @@ int machine_check_e500mc(struct pt_regs *regs)
* may still get logged and cause a machine check. We should * may still get logged and cause a machine check. We should
* only treat the non-write shadow case as non-recoverable. * only treat the non-write shadow case as non-recoverable.
*/ */
/* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
* is not implemented but L1 data cache always runs in write
* shadow mode. Hence on data cache parity errors HW will
* automatically invalidate the L1 Data Cache.
*/
if (PVR_VER(pvr) != PVR_VER_E6500) {
if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
recoverable = 0; recoverable = 0;
} }
}
if (reason & MCSR_L2MMU_MHIT) { if (reason & MCSR_L2MMU_MHIT) {
printk("Hit on multiple TLB entries\n"); printk("Hit on multiple TLB entries\n");
......
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