Commit b2e40d7a authored by Rakesh Pillai's avatar Rakesh Pillai Committed by Kalle Valo

ath10k: add hw params for shadow register support

wcn3990 supports shadow register for ce write.

Add a hw param for shadow register support.
Signed-off-by: default avatarRakesh Pillai <pillair@codeaurora.org>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent 20529b33
...@@ -90,6 +90,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -90,6 +90,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.num_wds_entries = 0x20, .num_wds_entries = 0x20,
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.shadow_reg_support = false,
}, },
{ {
.id = QCA988X_HW_2_0_VERSION, .id = QCA988X_HW_2_0_VERSION,
...@@ -120,6 +121,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -120,6 +121,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false,
}, },
{ {
.id = QCA9887_HW_1_0_VERSION, .id = QCA9887_HW_1_0_VERSION,
...@@ -150,6 +152,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -150,6 +152,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false,
}, },
{ {
.id = QCA6174_HW_2_1_VERSION, .id = QCA6174_HW_2_1_VERSION,
...@@ -179,6 +182,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -179,6 +182,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false,
}, },
{ {
.id = QCA6174_HW_2_1_VERSION, .id = QCA6174_HW_2_1_VERSION,
...@@ -208,6 +212,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -208,6 +212,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false,
}, },
{ {
.id = QCA6174_HW_3_0_VERSION, .id = QCA6174_HW_3_0_VERSION,
...@@ -237,6 +242,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -237,6 +242,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false,
}, },
{ {
.id = QCA6174_HW_3_2_VERSION, .id = QCA6174_HW_3_2_VERSION,
...@@ -269,6 +275,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -269,6 +275,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false,
}, },
{ {
.id = QCA99X0_HW_2_0_DEV_VERSION, .id = QCA99X0_HW_2_0_DEV_VERSION,
...@@ -304,6 +311,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -304,6 +311,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false,
}, },
{ {
.id = QCA9984_HW_1_0_DEV_VERSION, .id = QCA9984_HW_1_0_DEV_VERSION,
...@@ -344,6 +352,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -344,6 +352,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false,
}, },
{ {
.id = QCA9888_HW_2_0_DEV_VERSION, .id = QCA9888_HW_2_0_DEV_VERSION,
...@@ -383,6 +392,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -383,6 +392,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false,
}, },
{ {
.id = QCA9377_HW_1_0_DEV_VERSION, .id = QCA9377_HW_1_0_DEV_VERSION,
...@@ -412,6 +422,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -412,6 +422,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false,
}, },
{ {
.id = QCA9377_HW_1_1_DEV_VERSION, .id = QCA9377_HW_1_1_DEV_VERSION,
...@@ -443,6 +454,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -443,6 +454,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false,
}, },
{ {
.id = QCA4019_HW_1_0_DEV_VERSION, .id = QCA4019_HW_1_0_DEV_VERSION,
...@@ -479,6 +491,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -479,6 +491,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.target_64bit = false, .target_64bit = false,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
.per_ce_irq = false, .per_ce_irq = false,
.shadow_reg_support = false,
}, },
{ {
.id = WCN3990_HW_1_0_DEV_VERSION, .id = WCN3990_HW_1_0_DEV_VERSION,
...@@ -500,6 +513,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -500,6 +513,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.target_64bit = true, .target_64bit = true,
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC, .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC,
.per_ce_irq = true, .per_ce_irq = true,
.shadow_reg_support = true,
}, },
}; };
......
/* /*
* Copyright (c) 2005-2011 Atheros Communications Inc. * Copyright (c) 2005-2011 Atheros Communications Inc.
* Copyright (c) 2011-2017 Qualcomm Atheros, Inc. * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
* Copyright (c) 2018 The Linux Foundation. All rights reserved.
* *
* Permission to use, copy, modify, and/or distribute this software for any * Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above * purpose with or without fee is hereby granted, provided that the above
...@@ -571,6 +572,9 @@ struct ath10k_hw_params { ...@@ -571,6 +572,9 @@ struct ath10k_hw_params {
/* target supporting per ce IRQ */ /* target supporting per ce IRQ */
bool per_ce_irq; bool per_ce_irq;
/* target supporting shadow register for ce write */
bool shadow_reg_support;
}; };
struct htt_rx_desc; struct htt_rx_desc;
......
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