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Commit b6c31960 authored by Peter Vernia's avatar Peter Vernia Committed by Greg Kroah-Hartman
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staging: mt7621-pci: Fix spaces around parenthesis in pci-7621.c 

Adds spaces before open parenthesis, and removes spaces after open parenthesis
Signed-off-by: default avatarPeter Vernia <peter.vernia@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 4cc4dbbc
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Showing with 14 additions and 14 deletions
drivers/staging/mt7621-pci/pci-mt7621.c
View file @ b6c31960
...@@ -139,14 +139,14 @@ ...@@ -139,14 +139,14 @@
rt_sysc_m32(0, val, RALINK_RSTCTRL); \ rt_sysc_m32(0, val, RALINK_RSTCTRL); \
else \ else \
rt_sysc_m32(val, 0, RALINK_RSTCTRL); \ rt_sysc_m32(val, 0, RALINK_RSTCTRL); \
} while(0) } while (0)
#define DEASSERT_SYSRST_PCIE(val) \ #define DEASSERT_SYSRST_PCIE(val) \
do { \ do { \
if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \ if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \
rt_sysc_m32(val, 0, RALINK_RSTCTRL); \ rt_sysc_m32(val, 0, RALINK_RSTCTRL); \
else \ else \
rt_sysc_m32(0, val, RALINK_RSTCTRL); \ rt_sysc_m32(0, val, RALINK_RSTCTRL); \
} while(0) } while (0)
#define RALINK_CLKCFG1 0x30 #define RALINK_CLKCFG1 0x30
#define RALINK_RSTCTRL 0x34 #define RALINK_RSTCTRL 0x34
#define RALINK_GPIOMODE 0x60 #define RALINK_GPIOMODE 0x60
...@@ -195,7 +195,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, ...@@ -195,7 +195,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
(func << 8) | (where & 0xfc) | 0x80000000; (func << 8) | (where & 0xfc) | 0x80000000;
MV_WRITE(address_reg, address); MV_WRITE(address_reg, address);
switch(access_type) { switch (access_type) {
case PCI_ACCESS_WRITE_1: case PCI_ACCESS_WRITE_1:
MV_WRITE_8(data_reg+(where&0x3), *data); MV_WRITE_8(data_reg+(where&0x3), *data);
break; break;
...@@ -206,7 +206,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, ...@@ -206,7 +206,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
MV_WRITE(data_reg, *data); MV_WRITE(data_reg, *data);
break; break;
case PCI_ACCESS_READ_1: case PCI_ACCESS_READ_1:
MV_READ_8( data_reg+(where&0x3), data); MV_READ_8(data_reg+(where&0x3), data);
break; break;
case PCI_ACCESS_READ_2: case PCI_ACCESS_READ_2:
MV_READ_16(data_reg+(where&0x3), data); MV_READ_16(data_reg+(where&0x3), data);
...@@ -391,7 +391,7 @@ set_phy_for_ssc(void) ...@@ -391,7 +391,7 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
if(reg <= 5 && reg >= 3) { // 40MHz Xtal if (reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
printk("***** Xtal 40MHz *****\n"); printk("***** Xtal 40MHz *****\n");
} else { // 25MHz | 20MHz Xtal } else { // 25MHz | 20MHz Xtal
...@@ -414,7 +414,7 @@ set_phy_for_ssc(void) ...@@ -414,7 +414,7 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
if(reg <= 5 && reg >= 3) { // 40MHz Xtal if (reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
} }
...@@ -430,7 +430,7 @@ set_phy_for_ssc(void) ...@@ -430,7 +430,7 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
if(reg <= 5 && reg >= 3) { // 40MHz Xtal if (reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
} else { // 25MHz | 20MHz Xtal } else { // 25MHz | 20MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
...@@ -449,7 +449,7 @@ set_phy_for_ssc(void) ...@@ -449,7 +449,7 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
if(reg <= 5 && reg >= 3) { // 40MHz Xtal if (reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
} }
...@@ -532,7 +532,7 @@ static int mt7621_pci_probe(struct platform_device *pdev) ...@@ -532,7 +532,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
mdelay(1000); mdelay(1000);
if(( RALINK_PCI0_STATUS & 0x1) == 0) if ((RALINK_PCI0_STATUS & 0x1) == 0)
{ {
printk("PCIE0 no card, disable it(RST&CLK)\n"); printk("PCIE0 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST); ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
...@@ -543,7 +543,7 @@ static int mt7621_pci_probe(struct platform_device *pdev) ...@@ -543,7 +543,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
} }
if(( RALINK_PCI1_STATUS & 0x1) == 0) if ((RALINK_PCI1_STATUS & 0x1) == 0)
{ {
printk("PCIE1 no card, disable it(RST&CLK)\n"); printk("PCIE1 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST); ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
...@@ -554,7 +554,7 @@ static int mt7621_pci_probe(struct platform_device *pdev) ...@@ -554,7 +554,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
} }
if (( RALINK_PCI2_STATUS & 0x1) == 0) { if ((RALINK_PCI2_STATUS & 0x1) == 0) {
printk("PCIE2 no card, disable it(RST&CLK)\n"); printk("PCIE2 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST); ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1); rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1);
...@@ -578,7 +578,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num ...@@ -578,7 +578,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
3'b110 1 0 x 3'b110 1 0 x
3'b111 2 1 0 3'b111 2 1 0
*/ */
switch(pcie_link_status) { switch (pcie_link_status) {
case 2: case 2:
RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000; RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0 RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
...@@ -613,7 +613,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num ...@@ -613,7 +613,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE; RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
//PCIe0 //PCIe0
if((pcie_link_status & 0x1) != 0) { if ((pcie_link_status & 0x1) != 0) {
RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE; RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
RALINK_PCI0_CLASS = 0x06040001; RALINK_PCI0_CLASS = 0x06040001;
...@@ -636,7 +636,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num ...@@ -636,7 +636,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
printk("PCIE2 enabled\n"); printk("PCIE2 enabled\n");
} }
switch(pcie_link_status) { switch (pcie_link_status) {
case 7: case 7:
read_config(0, 2, 0, 0x4, &val); read_config(0, 2, 0, 0x4, &val);
write_config(0, 2, 0, 0x4, val|0x4); write_config(0, 2, 0, 0x4, val|0x4);
......
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