Commit b824efae authored by Tony Lindgren's avatar Tony Lindgren Committed by Russell King

[ARM] 3426/1: ARM: OMAP: 1/8 Update clock framework

Patch from Tony Lindgren

Update OMAP clock framework from linux-omap tree.
The highlights of the patch are:

- Add support for omap730 clocks by Andrzej Zaborowski
- Fix compile warnings by Dirk Behme
- Add support for using dev id by Tony Lindgren and Komal Shah
- Move memory timings and PRCM into separate files by Tony Lindgren
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 3267c077
...@@ -345,7 +345,7 @@ static unsigned calc_ext_dsor(unsigned long rate) ...@@ -345,7 +345,7 @@ static unsigned calc_ext_dsor(unsigned long rate)
*/ */
for (dsor = 2; dsor < 96; ++dsor) { for (dsor = 2; dsor < 96; ++dsor) {
if ((dsor & 1) && dsor > 8) if ((dsor & 1) && dsor > 8)
continue; continue;
if (rate >= 96000000 / dsor) if (rate >= 96000000 / dsor)
break; break;
} }
...@@ -687,6 +687,11 @@ int __init omap1_clk_init(void) ...@@ -687,6 +687,11 @@ int __init omap1_clk_init(void)
clk_register(*clkp); clk_register(*clkp);
continue; continue;
} }
if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) {
clk_register(*clkp);
continue;
}
} }
info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
...@@ -784,7 +789,7 @@ int __init omap1_clk_init(void) ...@@ -784,7 +789,7 @@ int __init omap1_clk_init(void)
clk_enable(&armxor_ck.clk); clk_enable(&armxor_ck.clk);
clk_enable(&armtim_ck.clk); /* This should be done by timer code */ clk_enable(&armtim_ck.clk); /* This should be done by timer code */
if (cpu_is_omap1510()) if (cpu_is_omap15xx())
clk_enable(&arm_gpio_ck); clk_enable(&arm_gpio_ck);
return 0; return 0;
......
This diff is collapsed.
...@@ -28,14 +28,14 @@ ...@@ -28,14 +28,14 @@
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
#include <asm/arch/sram.h> #include <asm/arch/sram.h>
#include <asm/arch/prcm.h>
#include "prcm-regs.h"
#include "memory.h"
#include "clock.h" #include "clock.h"
//#define DOWN_VARIABLE_DPLL 1 /* Experimental */ //#define DOWN_VARIABLE_DPLL 1 /* Experimental */
static struct prcm_config *curr_prcm_set; static struct prcm_config *curr_prcm_set;
static struct memory_timings mem_timings;
static u32 curr_perf_level = PRCM_FULL_SPEED; static u32 curr_perf_level = PRCM_FULL_SPEED;
/*------------------------------------------------------------------------- /*-------------------------------------------------------------------------
...@@ -54,11 +54,13 @@ static void omap2_sys_clk_recalc(struct clk * clk) ...@@ -54,11 +54,13 @@ static void omap2_sys_clk_recalc(struct clk * clk)
static u32 omap2_get_dpll_rate(struct clk * tclk) static u32 omap2_get_dpll_rate(struct clk * tclk)
{ {
int dpll_clk, dpll_mult, dpll_div, amult; long long dpll_clk;
int dpll_mult, dpll_div, amult;
dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */ dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */
dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */ dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */
dpll_clk = (tclk->parent->rate * dpll_mult) / (dpll_div + 1); dpll_clk = (long long)tclk->parent->rate * dpll_mult;
do_div(dpll_clk, dpll_div + 1);
amult = CM_CLKSEL2_PLL & 0x3; amult = CM_CLKSEL2_PLL & 0x3;
dpll_clk *= amult; dpll_clk *= amult;
...@@ -385,75 +387,23 @@ static u32 omap2_dll_force_needed(void) ...@@ -385,75 +387,23 @@ static u32 omap2_dll_force_needed(void)
return 0; return 0;
} }
static void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
{
unsigned long dll_cnt;
u32 fast_dll = 0;
mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
* In the case of 2422, its ok to use CS1 instead of CS0.
*/
#if 0 /* FIXME: Enable after 24xx cpu detection works */
ctype = get_cpu_type();
if (cpu_is_omap2422())
mem_timings.base_cs = 1;
else
#endif
mem_timings.base_cs = 0;
if (mem_timings.m_type != M_DDR)
return;
/* With DDR we need to determine the low frequency DLL value */
if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
mem_timings.dll_mode = M_UNLOCK;
else
mem_timings.dll_mode = M_LOCK;
if (mem_timings.base_cs == 0) {
fast_dll = SDRC_DLLA_CTRL;
dll_cnt = SDRC_DLLA_STATUS & 0xff00;
} else {
fast_dll = SDRC_DLLB_CTRL;
dll_cnt = SDRC_DLLB_STATUS & 0xff00;
}
if (force_lock_to_unlock_mode) {
fast_dll &= ~0xff00;
fast_dll |= dll_cnt; /* Current lock mode */
}
mem_timings.fast_dll_ctrl = fast_dll;
/* No disruptions, DDR will be offline & C-ABI not followed */
omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
mem_timings.fast_dll_ctrl,
mem_timings.base_cs,
force_lock_to_unlock_mode);
mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
/* Turn status into unlock ctrl */
mem_timings.slow_dll_ctrl |=
((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
/* 90 degree phase for anything below 133Mhz */
mem_timings.slow_dll_ctrl |= (1 << 1);
}
static u32 omap2_reprogram_sdrc(u32 level, u32 force) static u32 omap2_reprogram_sdrc(u32 level, u32 force)
{ {
u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
u32 prev = curr_perf_level, flags; u32 prev = curr_perf_level, flags;
if ((curr_perf_level == level) && !force) if ((curr_perf_level == level) && !force)
return prev; return prev;
m_type = omap2_memory_get_type();
slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
if (level == PRCM_HALF_SPEED) { if (level == PRCM_HALF_SPEED) {
local_irq_save(flags); local_irq_save(flags);
PRCM_VOLTSETUP = 0xffff; PRCM_VOLTSETUP = 0xffff;
omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED, omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
mem_timings.slow_dll_ctrl, slow_dll_ctrl, m_type);
mem_timings.m_type);
curr_perf_level = PRCM_HALF_SPEED; curr_perf_level = PRCM_HALF_SPEED;
local_irq_restore(flags); local_irq_restore(flags);
} }
...@@ -461,8 +411,7 @@ static u32 omap2_reprogram_sdrc(u32 level, u32 force) ...@@ -461,8 +411,7 @@ static u32 omap2_reprogram_sdrc(u32 level, u32 force)
local_irq_save(flags); local_irq_save(flags);
PRCM_VOLTSETUP = 0xffff; PRCM_VOLTSETUP = 0xffff;
omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED, omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
mem_timings.fast_dll_ctrl, fast_dll_ctrl, m_type);
mem_timings.m_type);
curr_perf_level = PRCM_FULL_SPEED; curr_perf_level = PRCM_FULL_SPEED;
local_irq_restore(flags); local_irq_restore(flags);
} }
...@@ -650,7 +599,7 @@ static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask, ...@@ -650,7 +599,7 @@ static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
case 13: /* dss2 */ case 13: /* dss2 */
mask = 0x1; break; mask = 0x1; break;
case 25: /* usb */ case 25: /* usb */
mask = 0xf; break; mask = 0x7; break;
} }
} }
......
...@@ -33,20 +33,6 @@ static u32 omap2_clksel_get_divisor(struct clk *clk); ...@@ -33,20 +33,6 @@ static u32 omap2_clksel_get_divisor(struct clk *clk);
#define RATE_IN_242X (1 << 0) #define RATE_IN_242X (1 << 0)
#define RATE_IN_243X (1 << 1) #define RATE_IN_243X (1 << 1)
/* Memory timings */
#define M_DDR 1
#define M_LOCK_CTRL (1 << 2)
#define M_UNLOCK 0
#define M_LOCK 1
struct memory_timings {
u32 m_type; /* ddr = 1, sdr = 0 */
u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
u32 base_cs; /* base chip select to use for calculations */
};
/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
* CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
...@@ -731,6 +717,16 @@ static struct clk sys_clkout2 = { ...@@ -731,6 +717,16 @@ static struct clk sys_clkout2 = {
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
static struct clk emul_ck = {
.name = "emul_ck",
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X,
.enable_reg = (void __iomem *)&PRCM_CLKEMUL_CTRL,
.enable_bit = 0,
.recalc = &omap2_propagate_rate,
};
/* /*
* MPU clock domain * MPU clock domain
* Clocks: * Clocks:
...@@ -1702,7 +1698,8 @@ static struct clk hdq_fck = { ...@@ -1702,7 +1698,8 @@ static struct clk hdq_fck = {
}; };
static struct clk i2c2_ick = { static struct clk i2c2_ick = {
.name = "i2c2_ick", .name = "i2c_ick",
.id = 2,
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
...@@ -1711,7 +1708,8 @@ static struct clk i2c2_ick = { ...@@ -1711,7 +1708,8 @@ static struct clk i2c2_ick = {
}; };
static struct clk i2c2_fck = { static struct clk i2c2_fck = {
.name = "i2c2_fck", .name = "i2c_fck",
.id = 2,
.parent = &func_12m_ck, .parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
...@@ -1729,7 +1727,8 @@ static struct clk i2chs2_fck = { ...@@ -1729,7 +1727,8 @@ static struct clk i2chs2_fck = {
}; };
static struct clk i2c1_ick = { static struct clk i2c1_ick = {
.name = "i2c1_ick", .name = "i2c_ick",
.id = 1,
.parent = &l4_ck, .parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
...@@ -1738,7 +1737,8 @@ static struct clk i2c1_ick = { ...@@ -1738,7 +1737,8 @@ static struct clk i2c1_ick = {
}; };
static struct clk i2c1_fck = { static struct clk i2c1_fck = {
.name = "i2c1_fck", .name = "i2c_fck",
.id = 1,
.parent = &func_12m_ck, .parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
...@@ -1971,6 +1971,7 @@ static struct clk *onchip_clks[] = { ...@@ -1971,6 +1971,7 @@ static struct clk *onchip_clks[] = {
&wdt1_osc_ck, &wdt1_osc_ck,
&sys_clkout, &sys_clkout,
&sys_clkout2, &sys_clkout2,
&emul_ck,
/* mpu domain clocks */ /* mpu domain clocks */
&mpu_ck, &mpu_ck,
/* dsp domain clocks */ /* dsp domain clocks */
......
/*
* linux/arch/arm/mach-omap2/memory.c
*
* Memory timing related functions for OMAP24XX
*
* Copyright (C) 2005 Texas Instruments Inc.
* Richard Woodruff <r-woodruff2@ti.com>
*
* Copyright (C) 2005 Nokia Corporation
* Tony Lindgren <tony@atomide.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/sram.h>
#include "prcm-regs.h"
#include "memory.h"
static struct memory_timings mem_timings;
u32 omap2_memory_get_slow_dll_ctrl(void)
{
return mem_timings.slow_dll_ctrl;
}
u32 omap2_memory_get_fast_dll_ctrl(void)
{
return mem_timings.fast_dll_ctrl;
}
u32 omap2_memory_get_type(void)
{
return mem_timings.m_type;
}
void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
{
unsigned long dll_cnt;
u32 fast_dll = 0;
mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
* In the case of 2422, its ok to use CS1 instead of CS0.
*/
if (cpu_is_omap2422())
mem_timings.base_cs = 1;
else
mem_timings.base_cs = 0;
if (mem_timings.m_type != M_DDR)
return;
/* With DDR we need to determine the low frequency DLL value */
if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
mem_timings.dll_mode = M_UNLOCK;
else
mem_timings.dll_mode = M_LOCK;
if (mem_timings.base_cs == 0) {
fast_dll = SDRC_DLLA_CTRL;
dll_cnt = SDRC_DLLA_STATUS & 0xff00;
} else {
fast_dll = SDRC_DLLB_CTRL;
dll_cnt = SDRC_DLLB_STATUS & 0xff00;
}
if (force_lock_to_unlock_mode) {
fast_dll &= ~0xff00;
fast_dll |= dll_cnt; /* Current lock mode */
}
/* set fast timings with DLL filter disabled */
mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
/* No disruptions, DDR will be offline & C-ABI not followed */
omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
mem_timings.fast_dll_ctrl,
mem_timings.base_cs,
force_lock_to_unlock_mode);
mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
/* Turn status into unlock ctrl */
mem_timings.slow_dll_ctrl |=
((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
/* 90 degree phase for anything below 133Mhz + disable DLL filter */
mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
}
/*
* linux/arch/arm/mach-omap2/memory.h
*
* Interface for memory timing related functions for OMAP24XX
*
* Copyright (C) 2005 Texas Instruments Inc.
* Richard Woodruff <r-woodruff2@ti.com>
*
* Copyright (C) 2005 Nokia Corporation
* Tony Lindgren <tony@atomide.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Memory timings */
#define M_DDR 1
#define M_LOCK_CTRL (1 << 2)
#define M_UNLOCK 0
#define M_LOCK 1
struct memory_timings {
u32 m_type; /* ddr = 1, sdr = 0 */
u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
u32 base_cs; /* base chip select to use for calculations */
};
extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode);
extern u32 omap2_memory_get_slow_dll_ctrl(void);
extern u32 omap2_memory_get_fast_dll_ctrl(void);
extern u32 omap2_memory_get_type(void);
/*
* linux/arch/arm/mach-omap2/prcm.c
*
* OMAP 24xx Power Reset and Clock Management (PRCM) functions
*
* Copyright (C) 2005 Nokia Corporation
*
* Written by Tony Lindgren <tony.lindgren@nokia.com>
*
* Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/clk.h>
#include "prcm-regs.h"
u32 omap_prcm_get_reset_sources(void)
{
return RM_RSTST_WKUP & 0x7f;
}
EXPORT_SYMBOL(omap_prcm_get_reset_sources);
/* Resets clock rates and reboots the system. Only called from system.h */
void omap_prcm_arch_reset(char mode)
{
u32 rate;
struct clk *vclk, *sclk;
vclk = clk_get(NULL, "virt_prcm_set");
sclk = clk_get(NULL, "sys_ck");
rate = clk_get_rate(sclk);
clk_set_rate(vclk, rate); /* go to bypass for OMAP limitation */
RM_RSTCTRL_WKUP |= 2;
}
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#include <linux/string.h> #include <linux/string.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/mutex.h> #include <linux/mutex.h>
#include <linux/platform_device.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/semaphore.h> #include <asm/semaphore.h>
...@@ -37,17 +38,37 @@ static struct clk_functions *arch_clock; ...@@ -37,17 +38,37 @@ static struct clk_functions *arch_clock;
* Standard clock functions defined in include/linux/clk.h * Standard clock functions defined in include/linux/clk.h
*-------------------------------------------------------------------------*/ *-------------------------------------------------------------------------*/
/*
* Returns a clock. Note that we first try to use device id on the bus
* and clock name. If this fails, we try to use clock name only.
*/
struct clk * clk_get(struct device *dev, const char *id) struct clk * clk_get(struct device *dev, const char *id)
{ {
struct clk *p, *clk = ERR_PTR(-ENOENT); struct clk *p, *clk = ERR_PTR(-ENOENT);
int idno;
if (dev == NULL || dev->bus != &platform_bus_type)
idno = -1;
else
idno = to_platform_device(dev)->id;
mutex_lock(&clocks_mutex); mutex_lock(&clocks_mutex);
list_for_each_entry(p, &clocks, node) {
if (p->id == idno &&
strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
clk = p;
break;
}
}
list_for_each_entry(p, &clocks, node) { list_for_each_entry(p, &clocks, node) {
if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
clk = p; clk = p;
break; break;
} }
} }
mutex_unlock(&clocks_mutex); mutex_unlock(&clocks_mutex);
return clk; return clk;
...@@ -59,6 +80,9 @@ int clk_enable(struct clk *clk) ...@@ -59,6 +80,9 @@ int clk_enable(struct clk *clk)
unsigned long flags; unsigned long flags;
int ret = 0; int ret = 0;
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
spin_lock_irqsave(&clockfw_lock, flags); spin_lock_irqsave(&clockfw_lock, flags);
if (arch_clock->clk_enable) if (arch_clock->clk_enable)
ret = arch_clock->clk_enable(clk); ret = arch_clock->clk_enable(clk);
...@@ -72,6 +96,9 @@ void clk_disable(struct clk *clk) ...@@ -72,6 +96,9 @@ void clk_disable(struct clk *clk)
{ {
unsigned long flags; unsigned long flags;
if (clk == NULL || IS_ERR(clk))
return;
spin_lock_irqsave(&clockfw_lock, flags); spin_lock_irqsave(&clockfw_lock, flags);
if (arch_clock->clk_disable) if (arch_clock->clk_disable)
arch_clock->clk_disable(clk); arch_clock->clk_disable(clk);
...@@ -84,6 +111,9 @@ int clk_get_usecount(struct clk *clk) ...@@ -84,6 +111,9 @@ int clk_get_usecount(struct clk *clk)
unsigned long flags; unsigned long flags;
int ret = 0; int ret = 0;
if (clk == NULL || IS_ERR(clk))
return 0;
spin_lock_irqsave(&clockfw_lock, flags); spin_lock_irqsave(&clockfw_lock, flags);
ret = clk->usecount; ret = clk->usecount;
spin_unlock_irqrestore(&clockfw_lock, flags); spin_unlock_irqrestore(&clockfw_lock, flags);
...@@ -97,6 +127,9 @@ unsigned long clk_get_rate(struct clk *clk) ...@@ -97,6 +127,9 @@ unsigned long clk_get_rate(struct clk *clk)
unsigned long flags; unsigned long flags;
unsigned long ret = 0; unsigned long ret = 0;
if (clk == NULL || IS_ERR(clk))
return 0;
spin_lock_irqsave(&clockfw_lock, flags); spin_lock_irqsave(&clockfw_lock, flags);
ret = clk->rate; ret = clk->rate;
spin_unlock_irqrestore(&clockfw_lock, flags); spin_unlock_irqrestore(&clockfw_lock, flags);
...@@ -121,6 +154,9 @@ long clk_round_rate(struct clk *clk, unsigned long rate) ...@@ -121,6 +154,9 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
unsigned long flags; unsigned long flags;
long ret = 0; long ret = 0;
if (clk == NULL || IS_ERR(clk))
return ret;
spin_lock_irqsave(&clockfw_lock, flags); spin_lock_irqsave(&clockfw_lock, flags);
if (arch_clock->clk_round_rate) if (arch_clock->clk_round_rate)
ret = arch_clock->clk_round_rate(clk, rate); ret = arch_clock->clk_round_rate(clk, rate);
...@@ -133,7 +169,10 @@ EXPORT_SYMBOL(clk_round_rate); ...@@ -133,7 +169,10 @@ EXPORT_SYMBOL(clk_round_rate);
int clk_set_rate(struct clk *clk, unsigned long rate) int clk_set_rate(struct clk *clk, unsigned long rate)
{ {
unsigned long flags; unsigned long flags;
int ret = 0; int ret = -EINVAL;
if (clk == NULL || IS_ERR(clk))
return ret;
spin_lock_irqsave(&clockfw_lock, flags); spin_lock_irqsave(&clockfw_lock, flags);
if (arch_clock->clk_set_rate) if (arch_clock->clk_set_rate)
...@@ -147,7 +186,10 @@ EXPORT_SYMBOL(clk_set_rate); ...@@ -147,7 +186,10 @@ EXPORT_SYMBOL(clk_set_rate);
int clk_set_parent(struct clk *clk, struct clk *parent) int clk_set_parent(struct clk *clk, struct clk *parent)
{ {
unsigned long flags; unsigned long flags;
int ret = 0; int ret = -EINVAL;
if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
return ret;
spin_lock_irqsave(&clockfw_lock, flags); spin_lock_irqsave(&clockfw_lock, flags);
if (arch_clock->clk_set_parent) if (arch_clock->clk_set_parent)
...@@ -163,6 +205,9 @@ struct clk *clk_get_parent(struct clk *clk) ...@@ -163,6 +205,9 @@ struct clk *clk_get_parent(struct clk *clk)
unsigned long flags; unsigned long flags;
struct clk * ret = NULL; struct clk * ret = NULL;
if (clk == NULL || IS_ERR(clk))
return ret;
spin_lock_irqsave(&clockfw_lock, flags); spin_lock_irqsave(&clockfw_lock, flags);
if (arch_clock->clk_get_parent) if (arch_clock->clk_get_parent)
ret = arch_clock->clk_get_parent(clk); ret = arch_clock->clk_get_parent(clk);
...@@ -199,6 +244,9 @@ __setup("mpurate=", omap_clk_setup); ...@@ -199,6 +244,9 @@ __setup("mpurate=", omap_clk_setup);
/* Used for clocks that always have same value as the parent clock */ /* Used for clocks that always have same value as the parent clock */
void followparent_recalc(struct clk *clk) void followparent_recalc(struct clk *clk)
{ {
if (clk == NULL || IS_ERR(clk))
return;
clk->rate = clk->parent->rate; clk->rate = clk->parent->rate;
} }
...@@ -207,6 +255,9 @@ void propagate_rate(struct clk * tclk) ...@@ -207,6 +255,9 @@ void propagate_rate(struct clk * tclk)
{ {
struct clk *clkp; struct clk *clkp;
if (tclk == NULL || IS_ERR(tclk))
return;
list_for_each_entry(clkp, &clocks, node) { list_for_each_entry(clkp, &clocks, node) {
if (likely(clkp->parent != tclk)) if (likely(clkp->parent != tclk))
continue; continue;
...@@ -217,6 +268,9 @@ void propagate_rate(struct clk * tclk) ...@@ -217,6 +268,9 @@ void propagate_rate(struct clk * tclk)
int clk_register(struct clk *clk) int clk_register(struct clk *clk)
{ {
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
mutex_lock(&clocks_mutex); mutex_lock(&clocks_mutex);
list_add(&clk->node, &clocks); list_add(&clk->node, &clocks);
if (clk->init) if (clk->init)
...@@ -229,6 +283,9 @@ EXPORT_SYMBOL(clk_register); ...@@ -229,6 +283,9 @@ EXPORT_SYMBOL(clk_register);
void clk_unregister(struct clk *clk) void clk_unregister(struct clk *clk)
{ {
if (clk == NULL || IS_ERR(clk))
return;
mutex_lock(&clocks_mutex); mutex_lock(&clocks_mutex);
list_del(&clk->node); list_del(&clk->node);
mutex_unlock(&clocks_mutex); mutex_unlock(&clocks_mutex);
...@@ -239,6 +296,9 @@ void clk_deny_idle(struct clk *clk) ...@@ -239,6 +296,9 @@ void clk_deny_idle(struct clk *clk)
{ {
unsigned long flags; unsigned long flags;
if (clk == NULL || IS_ERR(clk))
return;
spin_lock_irqsave(&clockfw_lock, flags); spin_lock_irqsave(&clockfw_lock, flags);
if (arch_clock->clk_deny_idle) if (arch_clock->clk_deny_idle)
arch_clock->clk_deny_idle(clk); arch_clock->clk_deny_idle(clk);
...@@ -250,6 +310,9 @@ void clk_allow_idle(struct clk *clk) ...@@ -250,6 +310,9 @@ void clk_allow_idle(struct clk *clk)
{ {
unsigned long flags; unsigned long flags;
if (clk == NULL || IS_ERR(clk))
return;
spin_lock_irqsave(&clockfw_lock, flags); spin_lock_irqsave(&clockfw_lock, flags);
if (arch_clock->clk_allow_idle) if (arch_clock->clk_allow_idle)
arch_clock->clk_allow_idle(clk); arch_clock->clk_allow_idle(clk);
......
...@@ -19,6 +19,7 @@ struct clk { ...@@ -19,6 +19,7 @@ struct clk {
struct list_head node; struct list_head node;
struct module *owner; struct module *owner;
const char *name; const char *name;
int id;
struct clk *parent; struct clk *parent;
unsigned long rate; unsigned long rate;
__u32 flags; __u32 flags;
...@@ -57,6 +58,7 @@ extern void propagate_rate(struct clk *clk); ...@@ -57,6 +58,7 @@ extern void propagate_rate(struct clk *clk);
extern void followparent_recalc(struct clk * clk); extern void followparent_recalc(struct clk * clk);
extern void clk_allow_idle(struct clk *clk); extern void clk_allow_idle(struct clk *clk);
extern void clk_deny_idle(struct clk *clk); extern void clk_deny_idle(struct clk *clk);
extern int clk_get_usecount(struct clk *clk);
/* Clock flags */ /* Clock flags */
#define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ #define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */
...@@ -80,10 +82,11 @@ extern void clk_deny_idle(struct clk *clk); ...@@ -80,10 +82,11 @@ extern void clk_deny_idle(struct clk *clk);
#define CM_PLL_SEL1 (1 << 18) #define CM_PLL_SEL1 (1 << 18)
#define CM_PLL_SEL2 (1 << 19) #define CM_PLL_SEL2 (1 << 19)
#define CM_SYSCLKOUT_SEL1 (1 << 20) #define CM_SYSCLKOUT_SEL1 (1 << 20)
#define CLOCK_IN_OMAP730 (1 << 21) #define CLOCK_IN_OMAP310 (1 << 21)
#define CLOCK_IN_OMAP1510 (1 << 22) #define CLOCK_IN_OMAP730 (1 << 22)
#define CLOCK_IN_OMAP16XX (1 << 23) #define CLOCK_IN_OMAP1510 (1 << 23)
#define CLOCK_IN_OMAP242X (1 << 24) #define CLOCK_IN_OMAP16XX (1 << 24)
#define CLOCK_IN_OMAP243X (1 << 25) #define CLOCK_IN_OMAP242X (1 << 25)
#define CLOCK_IN_OMAP243X (1 << 26)
#endif #endif
This diff is collapsed.
...@@ -9,12 +9,13 @@ ...@@ -9,12 +9,13 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/hardware.h> #include <asm/hardware.h>
#include <asm/arch/prcm.h>
#ifndef CONFIG_MACH_VOICEBLUE #ifndef CONFIG_MACH_VOICEBLUE
#define voiceblue_reset() do {} while (0) #define voiceblue_reset() do {} while (0)
#endif #endif
extern void omap_prcm_arch_reset(char mode);
static inline void arch_idle(void) static inline void arch_idle(void)
{ {
cpu_do_idle(); cpu_do_idle();
...@@ -38,24 +39,12 @@ static inline void omap1_arch_reset(char mode) ...@@ -38,24 +39,12 @@ static inline void omap1_arch_reset(char mode)
omap_writew(1, ARM_RSTCT1); omap_writew(1, ARM_RSTCT1);
} }
static inline void omap2_arch_reset(char mode)
{
u32 rate;
struct clk *vclk, *sclk;
vclk = clk_get(NULL, "virt_prcm_set");
sclk = clk_get(NULL, "sys_ck");
rate = clk_get_rate(sclk);
clk_set_rate(vclk, rate); /* go to bypass for OMAP limitation */
RM_RSTCTRL_WKUP |= 2;
}
static inline void arch_reset(char mode) static inline void arch_reset(char mode)
{ {
if (!cpu_is_omap24xx()) if (!cpu_is_omap24xx())
omap1_arch_reset(mode); omap1_arch_reset(mode);
else else
omap2_arch_reset(mode); omap_prcm_arch_reset(mode);
} }
#endif #endif
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