drm/nouveau/gr: rename from graph (no binary change)

Shorter device name, match Tegra and our existing enums.

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/include/nvif/class.h

@@ -122,7 +122,7 @@ struct nv_device_v0 {
 #define NV_DEVICE_V0_DISABLE_CORE                         0x0000000000000008ULL
 #define NV_DEVICE_V0_DISABLE_DISP                         0x0000000000010000ULL
 #define NV_DEVICE_V0_DISABLE_FIFO                         0x0000000000020000ULL
-#define NV_DEVICE_V0_DISABLE_GRAPH                        0x0000000100000000ULL
+#define NV_DEVICE_V0_DISABLE_GR                           0x0000000100000000ULL
 #define NV_DEVICE_V0_DISABLE_MPEG                         0x0000000200000000ULL
 #define NV_DEVICE_V0_DISABLE_ME                           0x0000000400000000ULL
 #define NV_DEVICE_V0_DISABLE_VP                           0x0000000800000000ULL

drivers/gpu/drm/nouveau/include/nvif/device.h

@@ -52,11 +52,11 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
 
 #include <engine/device.h>
 #include <engine/fifo.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/software.h>
 
 #define nvkm_fifo(a) nouveau_fifo(nvkm_device(a))
 #define nvkm_fifo_chan(a) ((struct nouveau_fifo_chan *)nvkm_object(a))
-#define nvkm_gr(a) ((struct nouveau_graph *)nouveau_engine(nvkm_object(a), NVDEV_ENGINE_GR))
+#define nvkm_gr(a) ((struct nouveau_gr *)nouveau_engine(nvkm_object(a), NVDEV_ENGINE_GR))
 
 #endif

drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h

+#ifndef __NOUVEAU_GR_H__
+#define __NOUVEAU_GR_H__
+
+#include <core/engine.h>
+#include <core/engctx.h>
+#include <core/enum.h>
+
+struct nouveau_gr_chan {
+	struct nouveau_engctx base;
+};
+
+#define nouveau_gr_context_create(p,e,c,g,s,a,f,d)                          \
+	nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
+#define nouveau_gr_context_destroy(d)                                       \
+	nouveau_engctx_destroy(&(d)->base)
+#define nouveau_gr_context_init(d)                                          \
+	nouveau_engctx_init(&(d)->base)
+#define nouveau_gr_context_fini(d,s)                                        \
+	nouveau_engctx_fini(&(d)->base, (s))
+
+#define _nouveau_gr_context_dtor _nouveau_engctx_dtor
+#define _nouveau_gr_context_init _nouveau_engctx_init
+#define _nouveau_gr_context_fini _nouveau_engctx_fini
+#define _nouveau_gr_context_rd32 _nouveau_engctx_rd32
+#define _nouveau_gr_context_wr32 _nouveau_engctx_wr32
+
+struct nouveau_gr {
+	struct nouveau_engine base;
+
+	/* Returns chipset-specific counts of units packed into an u64.
+	 */
+	u64 (*units)(struct nouveau_gr *);
+};
+
+static inline struct nouveau_gr *
+nouveau_gr(void *obj)
+{
+	return (void *)nouveau_engine(obj, NVDEV_ENGINE_GR);
+}
+
+#define nouveau_gr_create(p,e,c,y,d)                                        \
+	nouveau_engine_create((p), (e), (c), (y), "PGR", "graphics", (d))
+#define nouveau_gr_destroy(d)                                               \
+	nouveau_engine_destroy(&(d)->base)
+#define nouveau_gr_init(d)                                                  \
+	nouveau_engine_init(&(d)->base)
+#define nouveau_gr_fini(d,s)                                                \
+	nouveau_engine_fini(&(d)->base, (s))
+
+#define _nouveau_gr_dtor _nouveau_engine_dtor
+#define _nouveau_gr_init _nouveau_engine_init
+#define _nouveau_gr_fini _nouveau_engine_fini
+
+extern struct nouveau_oclass nv04_gr_oclass;
+extern struct nouveau_oclass nv10_gr_oclass;
+extern struct nouveau_oclass nv20_gr_oclass;
+extern struct nouveau_oclass nv25_gr_oclass;
+extern struct nouveau_oclass nv2a_gr_oclass;
+extern struct nouveau_oclass nv30_gr_oclass;
+extern struct nouveau_oclass nv34_gr_oclass;
+extern struct nouveau_oclass nv35_gr_oclass;
+extern struct nouveau_oclass nv40_gr_oclass;
+extern struct nouveau_oclass nv50_gr_oclass;
+extern struct nouveau_oclass *nvc0_gr_oclass;
+extern struct nouveau_oclass *nvc1_gr_oclass;
+extern struct nouveau_oclass *nvc4_gr_oclass;
+extern struct nouveau_oclass *nvc8_gr_oclass;
+extern struct nouveau_oclass *nvd7_gr_oclass;
+extern struct nouveau_oclass *nvd9_gr_oclass;
+extern struct nouveau_oclass *nve4_gr_oclass;
+extern struct nouveau_oclass *gk20a_gr_oclass;
+extern struct nouveau_oclass *nvf0_gr_oclass;
+extern struct nouveau_oclass *gk110b_gr_oclass;
+extern struct nouveau_oclass *nv108_gr_oclass;
+extern struct nouveau_oclass *gm107_gr_oclass;
+
+extern const struct nouveau_bitfield nv04_gr_nsource[];
+extern struct nouveau_ofuncs nv04_gr_ofuncs;
+bool nv04_gr_idle(void *obj);
+
+extern const struct nouveau_bitfield nv10_gr_intr_name[];
+extern const struct nouveau_bitfield nv10_gr_nstatus[];
+
+extern const struct nouveau_enum nv50_data_error_names[];
+
+#endif

drivers/gpu/drm/nouveau/include/nvkm/engine/graph.h

-#ifndef __NOUVEAU_GRAPH_H__
-#define __NOUVEAU_GRAPH_H__
-
-#include <core/engine.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-struct nouveau_graph_chan {
-	struct nouveau_engctx base;
-};
-
-#define nouveau_graph_context_create(p,e,c,g,s,a,f,d)                          \
-	nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
-#define nouveau_graph_context_destroy(d)                                       \
-	nouveau_engctx_destroy(&(d)->base)
-#define nouveau_graph_context_init(d)                                          \
-	nouveau_engctx_init(&(d)->base)
-#define nouveau_graph_context_fini(d,s)                                        \
-	nouveau_engctx_fini(&(d)->base, (s))
-
-#define _nouveau_graph_context_dtor _nouveau_engctx_dtor
-#define _nouveau_graph_context_init _nouveau_engctx_init
-#define _nouveau_graph_context_fini _nouveau_engctx_fini
-#define _nouveau_graph_context_rd32 _nouveau_engctx_rd32
-#define _nouveau_graph_context_wr32 _nouveau_engctx_wr32
-
-struct nouveau_graph {
-	struct nouveau_engine base;
-
-	/* Returns chipset-specific counts of units packed into an u64.
-	 */
-	u64 (*units)(struct nouveau_graph *);
-};
-
-static inline struct nouveau_graph *
-nouveau_graph(void *obj)
-{
-	return (void *)nouveau_engine(obj, NVDEV_ENGINE_GR);
-}
-
-#define nouveau_graph_create(p,e,c,y,d)                                        \
-	nouveau_engine_create((p), (e), (c), (y), "PGRAPH", "graphics", (d))
-#define nouveau_graph_destroy(d)                                               \
-	nouveau_engine_destroy(&(d)->base)
-#define nouveau_graph_init(d)                                                  \
-	nouveau_engine_init(&(d)->base)
-#define nouveau_graph_fini(d,s)                                                \
-	nouveau_engine_fini(&(d)->base, (s))
-
-#define _nouveau_graph_dtor _nouveau_engine_dtor
-#define _nouveau_graph_init _nouveau_engine_init
-#define _nouveau_graph_fini _nouveau_engine_fini
-
-extern struct nouveau_oclass nv04_graph_oclass;
-extern struct nouveau_oclass nv10_graph_oclass;
-extern struct nouveau_oclass nv20_graph_oclass;
-extern struct nouveau_oclass nv25_graph_oclass;
-extern struct nouveau_oclass nv2a_graph_oclass;
-extern struct nouveau_oclass nv30_graph_oclass;
-extern struct nouveau_oclass nv34_graph_oclass;
-extern struct nouveau_oclass nv35_graph_oclass;
-extern struct nouveau_oclass nv40_graph_oclass;
-extern struct nouveau_oclass nv50_graph_oclass;
-extern struct nouveau_oclass *nvc0_graph_oclass;
-extern struct nouveau_oclass *nvc1_graph_oclass;
-extern struct nouveau_oclass *nvc4_graph_oclass;
-extern struct nouveau_oclass *nvc8_graph_oclass;
-extern struct nouveau_oclass *nvd7_graph_oclass;
-extern struct nouveau_oclass *nvd9_graph_oclass;
-extern struct nouveau_oclass *nve4_graph_oclass;
-extern struct nouveau_oclass *gk20a_graph_oclass;
-extern struct nouveau_oclass *nvf0_graph_oclass;
-extern struct nouveau_oclass *gk110b_graph_oclass;
-extern struct nouveau_oclass *nv108_graph_oclass;
-extern struct nouveau_oclass *gm107_graph_oclass;
-
-extern const struct nouveau_bitfield nv04_graph_nsource[];
-extern struct nouveau_ofuncs nv04_graph_ofuncs;
-bool nv04_graph_idle(void *obj);
-
-extern const struct nouveau_bitfield nv10_graph_intr_name[];
-extern const struct nouveau_bitfield nv10_graph_nstatus[];
-
-extern const struct nouveau_enum nv50_data_error_names[];
-
-#endif

drivers/gpu/drm/nouveau/nouveau_abi16.c

@@ -165,7 +165,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS)
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	struct nvif_device *device = &drm->device;
 	struct nouveau_timer *ptimer = nvkm_timer(device);
-	struct nouveau_graph *graph = nvkm_gr(device);
+	struct nouveau_gr *gr = nvkm_gr(device);
 	struct drm_nouveau_getparam *getparam = data;
 
 	switch (getparam->param) {
@@ -215,7 +215,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS)
 		getparam->value = 1;
 		break;
 	case NOUVEAU_GETPARAM_GRAPH_UNITS:
-		getparam->value = graph->units ? graph->units(graph) : 0;
+		getparam->value = gr->units ? gr->units(gr) : 0;
 		break;
 	default:
 		NV_PRINTK(debug, cli, "unknown parameter %lld\n", getparam->param);

drivers/gpu/drm/nouveau/nvkm/engine/Kbuild

@@ -8,7 +8,7 @@ include $(src)/nvkm/engine/device/Kbuild
 include $(src)/nvkm/engine/disp/Kbuild
 include $(src)/nvkm/engine/dmaobj/Kbuild
 include $(src)/nvkm/engine/fifo/Kbuild
-include $(src)/nvkm/engine/graph/Kbuild
+include $(src)/nvkm/engine/gr/Kbuild
 include $(src)/nvkm/engine/mpeg/Kbuild
 include $(src)/nvkm/engine/msvld/Kbuild
 include $(src)/nvkm/engine/perfmon/Kbuild

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

@@ -228,7 +228,7 @@ static const u64 disable_map[] = {
 	[NVDEV_ENGINE_PERFMON]  = NV_DEVICE_V0_DISABLE_CORE,
 	[NVDEV_ENGINE_FIFO]	= NV_DEVICE_V0_DISABLE_FIFO,
 	[NVDEV_ENGINE_SW]	= NV_DEVICE_V0_DISABLE_FIFO,
-	[NVDEV_ENGINE_GR]	= NV_DEVICE_V0_DISABLE_GRAPH,
+	[NVDEV_ENGINE_GR]	= NV_DEVICE_V0_DISABLE_GR,
 	[NVDEV_ENGINE_MPEG]	= NV_DEVICE_V0_DISABLE_MPEG,
 	[NVDEV_ENGINE_ME]	= NV_DEVICE_V0_DISABLE_ME,
 	[NVDEV_ENGINE_VP]	= NV_DEVICE_V0_DISABLE_VP,

drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c

@@ -46,7 +46,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/disp.h>
 #include <engine/ce.h>
 #include <engine/bsp.h>
@@ -86,7 +86,7 @@ gm100_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gm107_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 #if 0
@@ -130,7 +130,7 @@ gm100_identify(struct nouveau_device *device)
 #if 0
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_gr_oclass;
 #endif
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gm204_disp_oclass;
 #if 0

drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c

@@ -37,7 +37,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/disp.h>
 
 int
@@ -59,7 +59,7 @@ nv04_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv04_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv04_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x05:
@@ -77,7 +77,7 @@ nv04_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv04_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv04_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	default:

drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c

@@ -38,7 +38,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/disp.h>
 
 int
@@ -59,7 +59,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
 		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x15:
@@ -78,7 +78,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x16:
@@ -97,7 +97,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x1a:
@@ -116,7 +116,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x11:
@@ -135,7 +135,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x17:
@@ -154,7 +154,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x1f:
@@ -173,7 +173,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x18:
@@ -192,7 +192,7 @@ nv10_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	default:

drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c

@@ -39,7 +39,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/disp.h>
 
 int
@@ -62,7 +62,7 @@ nv20_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv20_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv20_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x25:
@@ -81,7 +81,7 @@ nv20_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x28:
@@ -100,7 +100,7 @@ nv20_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x2a:
@@ -119,7 +119,7 @@ nv20_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv2a_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv2a_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	default:

drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c

@@ -38,7 +38,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/mpeg.h>
 #include <engine/disp.h>
 
@@ -62,7 +62,7 @@ nv30_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv30_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv30_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x35:
@@ -81,7 +81,7 @@ nv30_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv35_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv35_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	case 0x31:
@@ -100,7 +100,7 @@ nv30_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv30_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv30_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
@@ -120,7 +120,7 @@ nv30_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv35_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv35_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
@@ -140,7 +140,7 @@ nv30_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv34_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv34_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;

drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c

@@ -41,7 +41,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/mpeg.h>
 #include <engine/disp.h>
 #include <engine/perfmon.h>
@@ -68,7 +68,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -91,7 +91,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -114,7 +114,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -137,7 +137,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -160,7 +160,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -183,7 +183,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -206,7 +206,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -229,7 +229,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -252,7 +252,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -275,7 +275,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -298,7 +298,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -321,7 +321,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -344,7 +344,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -367,7 +367,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -390,7 +390,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;
@@ -413,7 +413,7 @@ nv40_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv40_perfmon_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c

@@ -44,7 +44,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/mpeg.h>
 #include <engine/vp.h>
 #include <engine/cipher.h>
@@ -81,7 +81,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv50_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv50_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv50_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] =  nv50_perfmon_oclass;
@@ -107,7 +107,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -136,7 +136,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -165,7 +165,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -194,7 +194,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -223,7 +223,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -252,7 +252,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 		device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
@@ -281,7 +281,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
@@ -310,7 +310,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 		device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
@@ -339,7 +339,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 		device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
@@ -369,7 +369,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
@@ -400,7 +400,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
@@ -430,7 +430,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
@@ -460,7 +460,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c

@@ -46,7 +46,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/vp.h>
 #include <engine/bsp.h>
 #include <engine/msvld.h>
@@ -83,7 +83,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc0_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvc0_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -116,7 +116,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -149,7 +149,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -181,7 +181,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -214,7 +214,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -246,7 +246,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc1_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvc1_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -278,7 +278,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvc0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvc8_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvc8_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -311,7 +311,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvd9_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvd9_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -341,7 +341,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvd7_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvd7_gr_oclass;
 		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c

@@ -46,7 +46,7 @@
 #include <engine/dmaobj.h>
 #include <engine/fifo.h>
 #include <engine/software.h>
-#include <engine/graph.h>
+#include <engine/gr.h>
 #include <engine/disp.h>
 #include <engine/ce.h>
 #include <engine/bsp.h>
@@ -83,7 +83,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nve0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &nve0_ce1_oclass;
@@ -117,7 +117,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nve0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &nve0_ce1_oclass;
@@ -151,7 +151,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nve0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &nve0_ce1_oclass;
@@ -177,7 +177,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk20a_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gk20a_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  gk20a_gr_oclass;
 		device->oclass[NVDEV_ENGINE_CE2    ] = &nve0_ce2_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &gk20a_volt_oclass;
@@ -207,7 +207,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nvf0_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nvf0_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &nve0_ce1_oclass;
@@ -241,7 +241,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gk110b_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  gk110b_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &nve0_ce1_oclass;
@@ -275,7 +275,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &nve0_ce1_oclass;
@@ -308,7 +308,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_graph_oclass;
+		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_gr_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &nve0_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &nve0_ce1_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild

+nvkm-y += nvkm/engine/gr/ctxnv40.o
+nvkm-y += nvkm/engine/gr/ctxnv50.o
+nvkm-y += nvkm/engine/gr/ctxnvc0.o
+nvkm-y += nvkm/engine/gr/ctxnvc1.o
+nvkm-y += nvkm/engine/gr/ctxnvc4.o
+nvkm-y += nvkm/engine/gr/ctxnvc8.o
+nvkm-y += nvkm/engine/gr/ctxnvd7.o
+nvkm-y += nvkm/engine/gr/ctxnvd9.o
+nvkm-y += nvkm/engine/gr/ctxnve4.o
+nvkm-y += nvkm/engine/gr/ctxgk20a.o
+nvkm-y += nvkm/engine/gr/ctxnvf0.o
+nvkm-y += nvkm/engine/gr/ctxgk110b.o
+nvkm-y += nvkm/engine/gr/ctxnv108.o
+nvkm-y += nvkm/engine/gr/ctxgm107.o
+nvkm-y += nvkm/engine/gr/nv04.o
+nvkm-y += nvkm/engine/gr/nv10.o
+nvkm-y += nvkm/engine/gr/nv20.o
+nvkm-y += nvkm/engine/gr/nv25.o
+nvkm-y += nvkm/engine/gr/nv2a.o
+nvkm-y += nvkm/engine/gr/nv30.o
+nvkm-y += nvkm/engine/gr/nv34.o
+nvkm-y += nvkm/engine/gr/nv35.o
+nvkm-y += nvkm/engine/gr/nv40.o
+nvkm-y += nvkm/engine/gr/nv50.o
+nvkm-y += nvkm/engine/gr/nvc0.o
+nvkm-y += nvkm/engine/gr/nvc1.o
+nvkm-y += nvkm/engine/gr/nvc4.o
+nvkm-y += nvkm/engine/gr/nvc8.o
+nvkm-y += nvkm/engine/gr/nvd7.o
+nvkm-y += nvkm/engine/gr/nvd9.o
+nvkm-y += nvkm/engine/gr/nve4.o
+nvkm-y += nvkm/engine/gr/gk20a.o
+nvkm-y += nvkm/engine/gr/nvf0.o
+nvkm-y += nvkm/engine/gr/gk110b.o
+nvkm-y += nvkm/engine/gr/nv108.o
+nvkm-y += nvkm/engine/gr/gm107.o

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk110b.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gk110b_grctx_init_sm_0[] = {
 	{ 0x419e04,   1, 0x04, 0x00000000 },
 	{ 0x419e08,   1, 0x04, 0x0000001d },
@@ -56,7 +56,7 @@ gk110b_grctx_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gk110b_grctx_pack_tpc[] = {
 	{ nvd7_grctx_init_pe_0 },
 	{ nvf0_grctx_init_tex_0 },
@@ -74,12 +74,12 @@ struct nouveau_oclass *
 gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xf1),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nve4_grctx_generate_main,
 	.unkn  = nve4_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgk20a.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c

@@ -22,7 +22,7 @@
 
 #include "ctxnvc0.h"
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gk20a_grctx_pack_mthd[] = {
 	{ nve4_grctx_init_a097_0, 0xa297 },
 	{ nvc0_grctx_init_902d_0, 0x902d },
@@ -33,12 +33,12 @@ struct nouveau_oclass *
 gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xea),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nve4_grctx_generate_main,
 	.unkn  = nve4_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxgm107.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_icmd_0[] = {
 	{ 0x001000,   1, 0x01, 0x00000004 },
 	{ 0x000039,   3, 0x01, 0x00000000 },
@@ -287,13 +287,13 @@ gm107_grctx_init_icmd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gm107_grctx_pack_icmd[] = {
 	{ gm107_grctx_init_icmd_0 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_b097_0[] = {
 	{ 0x000800,   8, 0x40, 0x00000000 },
 	{ 0x000804,   8, 0x40, 0x00000000 },
@@ -610,14 +610,14 @@ gm107_grctx_init_b097_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gm107_grctx_pack_mthd[] = {
 	{ gm107_grctx_init_b097_0, 0xb097 },
 	{ nvc0_grctx_init_902d_0, 0x902d },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_fe_0[] = {
 	{ 0x404004,   8, 0x04, 0x00000000 },
 	{ 0x404024,   1, 0x04, 0x0000e000 },
@@ -639,7 +639,7 @@ gm107_grctx_init_fe_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_ds_0[] = {
 	{ 0x405800,   1, 0x04, 0x0f8001bf },
 	{ 0x405830,   1, 0x04, 0x0aa01000 },
@@ -653,7 +653,7 @@ gm107_grctx_init_ds_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_pd_0[] = {
 	{ 0x406020,   1, 0x04, 0x07410001 },
 	{ 0x406028,   4, 0x04, 0x00000001 },
@@ -669,7 +669,7 @@ gm107_grctx_init_pd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_be_0[] = {
 	{ 0x408800,   1, 0x04, 0x32802a3c },
 	{ 0x408804,   1, 0x04, 0x00000040 },
@@ -682,7 +682,7 @@ gm107_grctx_init_be_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gm107_grctx_pack_hub[] = {
 	{ nvc0_grctx_init_main_0 },
 	{ gm107_grctx_init_fe_0 },
@@ -697,13 +697,13 @@ gm107_grctx_pack_hub[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_gpc_unk_0[] = {
 	{ 0x418380,   1, 0x04, 0x00000056 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_gpc_unk_1[] = {
 	{ 0x418600,   1, 0x04, 0x0000007f },
 	{ 0x418684,   1, 0x04, 0x0000001f },
@@ -714,7 +714,7 @@ gm107_grctx_init_gpc_unk_1[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x7006863a },
 	{ 0x418810,   1, 0x04, 0x00000000 },
@@ -727,7 +727,7 @@ gm107_grctx_init_setup_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_gpc_unk_2[] = {
 	{ 0x418d24,   1, 0x04, 0x00000000 },
 	{ 0x418e00,   1, 0x04, 0x90000000 },
@@ -741,7 +741,7 @@ gm107_grctx_init_gpc_unk_2[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gm107_grctx_pack_gpc[] = {
 	{ gm107_grctx_init_gpc_unk_0 },
 	{ nv108_grctx_init_prop_0 },
@@ -755,7 +755,7 @@ gm107_grctx_pack_gpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_tex_0[] = {
 	{ 0x419a00,   1, 0x04, 0x000300f0 },
 	{ 0x419a04,   1, 0x04, 0x00000005 },
@@ -771,7 +771,7 @@ gm107_grctx_init_tex_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_mpc_0[] = {
 	{ 0x419c00,   1, 0x04, 0x0000001a },
 	{ 0x419c04,   1, 0x04, 0x80000006 },
@@ -785,13 +785,13 @@ gm107_grctx_init_mpc_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_l1c_0[] = {
 	{ 0x419c84,   1, 0x04, 0x00000020 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_sm_0[] = {
 	{ 0x419e04,   3, 0x04, 0x00000000 },
 	{ 0x419e10,   1, 0x04, 0x00001c02 },
@@ -812,7 +812,7 @@ gm107_grctx_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gm107_grctx_pack_tpc[] = {
 	{ nvd7_grctx_init_pe_0 },
 	{ gm107_grctx_init_tex_0 },
@@ -822,7 +822,7 @@ gm107_grctx_pack_tpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_cbm_0[] = {
 	{ 0x41bec0,   1, 0x04, 0x00000000 },
 	{ 0x41bec4,   1, 0x04, 0x01050000 },
@@ -832,7 +832,7 @@ gm107_grctx_init_cbm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 gm107_grctx_init_wwdx_0[] = {
 	{ 0x41bf00,   1, 0x04, 0x0a418820 },
 	{ 0x41bf04,   1, 0x04, 0x062080e6 },
@@ -846,7 +846,7 @@ gm107_grctx_init_wwdx_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 gm107_grctx_pack_ppc[] = {
 	{ nve4_grctx_init_pes_0 },
 	{ gm107_grctx_init_cbm_0 },
@@ -893,7 +893,7 @@ gm107_grctx_generate_pagepool(struct nvc0_grctx *info)
 static void
 gm107_grctx_generate_attrib(struct nvc0_grctx *info)
 {
-	struct nvc0_graph_priv *priv = info->priv;
+	struct nvc0_gr_priv *priv = info->priv;
 	const struct nvc0_grctx_oclass *impl = (void *)nvc0_grctx_impl(priv);
 	const u32  alpha = impl->alpha_nr;
 	const u32 attrib = impl->attrib_nr;
@@ -930,7 +930,7 @@ gm107_grctx_generate_attrib(struct nvc0_grctx *info)
 }
 
 static void
-gm107_grctx_generate_tpcid(struct nvc0_graph_priv *priv)
+gm107_grctx_generate_tpcid(struct nvc0_gr_priv *priv)
 {
 	int gpc, tpc, id;
 
@@ -950,16 +950,16 @@ gm107_grctx_generate_tpcid(struct nvc0_graph_priv *priv)
 }
 
 static void
-gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+gm107_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
 {
 	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
 	int i;
 
-	nvc0_graph_mmio(priv, oclass->hub);
-	nvc0_graph_mmio(priv, oclass->gpc);
-	nvc0_graph_mmio(priv, oclass->zcull);
-	nvc0_graph_mmio(priv, oclass->tpc);
-	nvc0_graph_mmio(priv, oclass->ppc);
+	nvc0_gr_mmio(priv, oclass->hub);
+	nvc0_gr_mmio(priv, oclass->gpc);
+	nvc0_gr_mmio(priv, oclass->zcull);
+	nvc0_gr_mmio(priv, oclass->tpc);
+	nvc0_gr_mmio(priv, oclass->ppc);
 
 	nv_wr32(priv, 0x404154, 0x00000000);
 
@@ -988,9 +988,9 @@ gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
 		nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
 	}
 
-	nvc0_graph_icmd(priv, oclass->icmd);
+	nvc0_gr_icmd(priv, oclass->icmd);
 	nv_wr32(priv, 0x404154, 0x00000400);
-	nvc0_graph_mthd(priv, oclass->mthd);
+	nvc0_gr_mthd(priv, oclass->mthd);
 
 	nv_mask(priv, 0x419e00, 0x00808080, 0x00808080);
 	nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000);
@@ -1002,12 +1002,12 @@ struct nouveau_oclass *
 gm107_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0x08),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = gm107_grctx_generate_main,
 	.unkn  = nve4_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv108.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_icmd_0[] = {
 	{ 0x001000,   1, 0x01, 0x00000004 },
 	{ 0x000039,   3, 0x01, 0x00000000 },
@@ -278,13 +278,13 @@ nv108_grctx_init_icmd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nv108_grctx_pack_icmd[] = {
 	{ nv108_grctx_init_icmd_0 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_fe_0[] = {
 	{ 0x404004,   8, 0x04, 0x00000000 },
 	{ 0x404024,   1, 0x04, 0x0000e000 },
@@ -311,7 +311,7 @@ nv108_grctx_init_fe_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_ds_0[] = {
 	{ 0x405800,   1, 0x04, 0x0f8000bf },
 	{ 0x405830,   1, 0x04, 0x02180648 },
@@ -325,7 +325,7 @@ nv108_grctx_init_ds_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_pd_0[] = {
 	{ 0x406020,   1, 0x04, 0x034103c1 },
 	{ 0x406028,   4, 0x04, 0x00000001 },
@@ -340,7 +340,7 @@ nv108_grctx_init_pd_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nv108_grctx_init_rstr2d_0[] = {
 	{ 0x407804,   1, 0x04, 0x00000063 },
 	{ 0x40780c,   1, 0x04, 0x0a418820 },
@@ -353,7 +353,7 @@ nv108_grctx_init_rstr2d_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_be_0[] = {
 	{ 0x408800,   1, 0x04, 0x32802a3c },
 	{ 0x408804,   1, 0x04, 0x00000040 },
@@ -366,7 +366,7 @@ nv108_grctx_init_be_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nv108_grctx_pack_hub[] = {
 	{ nvc0_grctx_init_main_0 },
 	{ nv108_grctx_init_fe_0 },
@@ -381,7 +381,7 @@ nv108_grctx_pack_hub[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nv108_grctx_init_prop_0[] = {
 	{ 0x418400,   1, 0x04, 0x38005e00 },
 	{ 0x418404,   1, 0x04, 0x71e0ffff },
@@ -394,7 +394,7 @@ nv108_grctx_init_prop_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_gpc_unk_1[] = {
 	{ 0x418600,   1, 0x04, 0x0000007f },
 	{ 0x418684,   1, 0x04, 0x0000001f },
@@ -404,7 +404,7 @@ nv108_grctx_init_gpc_unk_1[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x7006863a },
 	{ 0x418808,   1, 0x04, 0x00000000 },
@@ -419,7 +419,7 @@ nv108_grctx_init_setup_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nv108_grctx_init_crstr_0[] = {
 	{ 0x418b00,   1, 0x04, 0x0000001e },
 	{ 0x418b08,   1, 0x04, 0x0a418820 },
@@ -432,7 +432,7 @@ nv108_grctx_init_crstr_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_gpm_0[] = {
 	{ 0x418c08,   1, 0x04, 0x00000001 },
 	{ 0x418c10,   8, 0x04, 0x00000000 },
@@ -443,7 +443,7 @@ nv108_grctx_init_gpm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nv108_grctx_pack_gpc[] = {
 	{ nvc0_grctx_init_gpc_unk_0 },
 	{ nv108_grctx_init_prop_0 },
@@ -457,7 +457,7 @@ nv108_grctx_pack_gpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_tex_0[] = {
 	{ 0x419a00,   1, 0x04, 0x000100f0 },
 	{ 0x419a04,   1, 0x04, 0x00000001 },
@@ -472,7 +472,7 @@ nv108_grctx_init_tex_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_sm_0[] = {
 	{ 0x419e04,   1, 0x04, 0x00000000 },
 	{ 0x419e08,   1, 0x04, 0x0000001d },
@@ -500,7 +500,7 @@ nv108_grctx_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nv108_grctx_pack_tpc[] = {
 	{ nvd7_grctx_init_pe_0 },
 	{ nv108_grctx_init_tex_0 },
@@ -510,7 +510,7 @@ nv108_grctx_pack_tpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nv108_grctx_init_cbm_0[] = {
 	{ 0x41bec0,   1, 0x04, 0x10000000 },
 	{ 0x41bec4,   1, 0x04, 0x00037f7f },
@@ -519,7 +519,7 @@ nv108_grctx_init_cbm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nv108_grctx_pack_ppc[] = {
 	{ nve4_grctx_init_pes_0 },
 	{ nv108_grctx_init_cbm_0 },
@@ -535,12 +535,12 @@ struct nouveau_oclass *
 nv108_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0x08),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nve4_grctx_generate_main,
 	.unkn  = nve4_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnv40.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c

@@ -119,7 +119,7 @@
  */
 
 static int
-nv40_graph_vs_count(struct nouveau_device *device)
+nv40_gr_vs_count(struct nouveau_device *device)
 {
 
 	switch (device->chipset) {
@@ -158,7 +158,7 @@ enum cp_label {
 };
 
 static void
-nv40_graph_construct_general(struct nouveau_grctx *ctx)
+nv40_gr_construct_general(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int i;
@@ -208,7 +208,7 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx)
 		gr_def(ctx, 0x4009dc, 0x80000000);
 	} else {
 		cp_ctx(ctx, 0x400840, 20);
-		if (nv44_graph_class(ctx->device)) {
+		if (nv44_gr_class(ctx->device)) {
 			for (i = 0; i < 8; i++)
 				gr_def(ctx, 0x400860 + (i * 4), 0x00000001);
 		}
@@ -217,7 +217,7 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx)
 		gr_def(ctx, 0x400888, 0x00000040);
 		cp_ctx(ctx, 0x400894, 11);
 		gr_def(ctx, 0x400894, 0x00000040);
-		if (!nv44_graph_class(ctx->device)) {
+		if (!nv44_gr_class(ctx->device)) {
 			for (i = 0; i < 8; i++)
 				gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000);
 		}
@@ -264,7 +264,7 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx)
 }
 
 static void
-nv40_graph_construct_state3d(struct nouveau_grctx *ctx)
+nv40_gr_construct_state3d(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int i;
@@ -369,7 +369,7 @@ nv40_graph_construct_state3d(struct nouveau_grctx *ctx)
 }
 
 static void
-nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx)
+nv40_gr_construct_state3d_2(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	int i;
@@ -504,8 +504,8 @@ nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx)
 
 	cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3);
 	cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3);
-	cp_ctx(ctx, 0x403420, nv40_graph_vs_count(ctx->device));
-	for (i = 0; i < nv40_graph_vs_count(ctx->device); i++)
+	cp_ctx(ctx, 0x403420, nv40_gr_vs_count(ctx->device));
+	for (i = 0; i < nv40_gr_vs_count(ctx->device); i++)
 		gr_def(ctx, 0x403420 + (i * 4), 0x00005555);
 
 	if (device->chipset != 0x40) {
@@ -533,9 +533,9 @@ nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx)
 }
 
 static void
-nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx)
+nv40_gr_construct_state3d_3(struct nouveau_grctx *ctx)
 {
-	int len = nv44_graph_class(ctx->device) ? 0x0084 : 0x0684;
+	int len = nv44_gr_class(ctx->device) ? 0x0084 : 0x0684;
 
 	cp_out (ctx, 0x300000);
 	cp_lsr (ctx, len - 4);
@@ -548,14 +548,14 @@ nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx)
 }
 
 static void
-nv40_graph_construct_shader(struct nouveau_grctx *ctx)
+nv40_gr_construct_shader(struct nouveau_grctx *ctx)
 {
 	struct nouveau_device *device = ctx->device;
 	struct nouveau_gpuobj *obj = ctx->data;
 	int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset;
 	int offset, i;
 
-	vs_nr    = nv40_graph_vs_count(ctx->device);
+	vs_nr    = nv40_gr_vs_count(ctx->device);
 	vs_nr_b0 = 363;
 	vs_nr_b1 = device->chipset == 0x40 ? 128 : 64;
 	if (device->chipset == 0x40) {
@@ -570,11 +570,11 @@ nv40_graph_construct_shader(struct nouveau_grctx *ctx)
 	} else {
 		b0_offset = 0x1d40/4; /* 2200 */
 		b1_offset = 0x3f40/4; /* 0b00 : 0a40 */
-		vs_len = nv44_graph_class(device) ? 0x4980/4 : 0x4a40/4;
+		vs_len = nv44_gr_class(device) ? 0x4980/4 : 0x4a40/4;
 	}
 
 	cp_lsr(ctx, vs_len * vs_nr + 0x300/4);
-	cp_out(ctx, nv44_graph_class(device) ? 0x800029 : 0x800041);
+	cp_out(ctx, nv44_gr_class(device) ? 0x800029 : 0x800041);
 
 	offset = ctx->ctxvals_pos;
 	ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len));
@@ -629,23 +629,23 @@ nv40_grctx_generate(struct nouveau_grctx *ctx)
 	/* general PGRAPH state */
 	cp_name(ctx, cp_swap_state);
 	cp_pos (ctx, 0x00020/4);
-	nv40_graph_construct_general(ctx);
+	nv40_gr_construct_general(ctx);
 	cp_wait(ctx, STATUS, IDLE);
 
 	/* 3D state, block 1 */
 	cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit);
-	nv40_graph_construct_state3d(ctx);
+	nv40_gr_construct_state3d(ctx);
 	cp_wait(ctx, STATUS, IDLE);
 
 	/* 3D state, block 2 */
-	nv40_graph_construct_state3d_2(ctx);
+	nv40_gr_construct_state3d_2(ctx);
 
 	/* Some other block of "random" state */
-	nv40_graph_construct_state3d_3(ctx);
+	nv40_gr_construct_state3d_3(ctx);
 
 	/* Per-vertex shader state */
 	cp_pos (ctx, ctx->ctxvals_pos);
-	nv40_graph_construct_shader(ctx);
+	nv40_gr_construct_shader(ctx);
 
 	/* pre-exit state updates */
 	cp_name(ctx, cp_prepare_exit);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h

+#ifndef __NVKM_GRCTX_NVC0_H__
+#define __NVKM_GRCTX_NVC0_H__
+
+#include "nvc0.h"
+
+struct nvc0_grctx {
+	struct nvc0_gr_priv *priv;
+	struct nvc0_gr_data *data;
+	struct nvc0_gr_mmio *mmio;
+	int buffer_nr;
+	u64 buffer[4];
+	u64 addr;
+};
+
+int  nvc0_grctx_mmio_data(struct nvc0_grctx *, u32 size, u32 align, u32 access);
+void nvc0_grctx_mmio_item(struct nvc0_grctx *, u32 addr, u32 data, int s, int);
+
+#define mmio_vram(a,b,c,d) nvc0_grctx_mmio_data((a), (b), (c), (d))
+#define mmio_refn(a,b,c,d,e) nvc0_grctx_mmio_item((a), (b), (c), (d), (e))
+#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1)
+#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c),  0, -1)
+
+struct nvc0_grctx_oclass {
+	struct nouveau_oclass base;
+	/* main context generation function */
+	void  (*main)(struct nvc0_gr_priv *, struct nvc0_grctx *);
+	/* context-specific modify-on-first-load list generation function */
+	void  (*unkn)(struct nvc0_gr_priv *);
+	/* mmio context data */
+	const struct nvc0_gr_pack *hub;
+	const struct nvc0_gr_pack *gpc;
+	const struct nvc0_gr_pack *zcull;
+	const struct nvc0_gr_pack *tpc;
+	const struct nvc0_gr_pack *ppc;
+	/* indirect context data, generated with icmds/mthds */
+	const struct nvc0_gr_pack *icmd;
+	const struct nvc0_gr_pack *mthd;
+	/* bundle circular buffer */
+	void (*bundle)(struct nvc0_grctx *);
+	u32 bundle_size;
+	u32 bundle_min_gpm_fifo_depth;
+	u32 bundle_token_limit;
+	/* pagepool */
+	void (*pagepool)(struct nvc0_grctx *);
+	u32 pagepool_size;
+	/* attribute(/alpha) circular buffer */
+	void (*attrib)(struct nvc0_grctx *);
+	u32 attrib_nr_max;
+	u32 attrib_nr;
+	u32 alpha_nr_max;
+	u32 alpha_nr;
+};
+
+static inline const struct nvc0_grctx_oclass *
+nvc0_grctx_impl(struct nvc0_gr_priv *priv)
+{
+	return (void *)nv_engine(priv)->cclass;
+}
+
+extern struct nouveau_oclass *nvc0_grctx_oclass;
+int  nvc0_grctx_generate(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_main(struct nvc0_gr_priv *, struct nvc0_grctx *);
+void nvc0_grctx_generate_bundle(struct nvc0_grctx *);
+void nvc0_grctx_generate_pagepool(struct nvc0_grctx *);
+void nvc0_grctx_generate_attrib(struct nvc0_grctx *);
+void nvc0_grctx_generate_unkn(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_tpcid(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_r406028(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_r4060a8(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_r418bb8(struct nvc0_gr_priv *);
+void nvc0_grctx_generate_r406800(struct nvc0_gr_priv *);
+
+extern struct nouveau_oclass *nvc1_grctx_oclass;
+void nvc1_grctx_generate_attrib(struct nvc0_grctx *);
+void nvc1_grctx_generate_unkn(struct nvc0_gr_priv *);
+
+extern struct nouveau_oclass *nvc4_grctx_oclass;
+extern struct nouveau_oclass *nvc8_grctx_oclass;
+
+extern struct nouveau_oclass *nvd7_grctx_oclass;
+void nvd7_grctx_generate_attrib(struct nvc0_grctx *);
+
+extern struct nouveau_oclass *nvd9_grctx_oclass;
+
+extern struct nouveau_oclass *nve4_grctx_oclass;
+extern struct nouveau_oclass *gk20a_grctx_oclass;
+void nve4_grctx_generate_main(struct nvc0_gr_priv *, struct nvc0_grctx *);
+void nve4_grctx_generate_bundle(struct nvc0_grctx *);
+void nve4_grctx_generate_pagepool(struct nvc0_grctx *);
+void nve4_grctx_generate_unkn(struct nvc0_gr_priv *);
+void nve4_grctx_generate_r418bb8(struct nvc0_gr_priv *);
+
+extern struct nouveau_oclass *nvf0_grctx_oclass;
+extern struct nouveau_oclass *gk110b_grctx_oclass;
+extern struct nouveau_oclass *nv108_grctx_oclass;
+extern struct nouveau_oclass *gm107_grctx_oclass;
+
+/* context init value lists */
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_icmd[];
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_mthd[];
+extern const struct nvc0_gr_init nvc0_grctx_init_902d_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_9039_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_90c0_0[];
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_hub[];
+extern const struct nvc0_gr_init nvc0_grctx_init_main_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_fe_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_pri_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_memfmt_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_rstr2d_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_scc_0[];
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_gpc[];
+extern const struct nvc0_gr_init nvc0_grctx_init_gpc_unk_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_prop_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_gpc_unk_1[];
+extern const struct nvc0_gr_init nvc0_grctx_init_zcull_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_crstr_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_gpm_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_gcc_0[];
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_zcull[];
+
+extern const struct nvc0_gr_pack nvc0_grctx_pack_tpc[];
+extern const struct nvc0_gr_init nvc0_grctx_init_pe_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_wwdx_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_mpc_0[];
+extern const struct nvc0_gr_init nvc0_grctx_init_tpccs_0[];
+
+extern const struct nvc0_gr_init nvc4_grctx_init_tex_0[];
+extern const struct nvc0_gr_init nvc4_grctx_init_l1c_0[];
+extern const struct nvc0_gr_init nvc4_grctx_init_sm_0[];
+
+extern const struct nvc0_gr_init nvc1_grctx_init_9097_0[];
+
+extern const struct nvc0_gr_init nvc1_grctx_init_gpm_0[];
+
+extern const struct nvc0_gr_init nvc1_grctx_init_pe_0[];
+extern const struct nvc0_gr_init nvc1_grctx_init_wwdx_0[];
+extern const struct nvc0_gr_init nvc1_grctx_init_tpccs_0[];
+
+extern const struct nvc0_gr_init nvc8_grctx_init_9197_0[];
+extern const struct nvc0_gr_init nvc8_grctx_init_9297_0[];
+
+extern const struct nvc0_gr_pack nvd9_grctx_pack_icmd[];
+
+extern const struct nvc0_gr_pack nvd9_grctx_pack_mthd[];
+
+extern const struct nvc0_gr_init nvd9_grctx_init_fe_0[];
+extern const struct nvc0_gr_init nvd9_grctx_init_be_0[];
+
+extern const struct nvc0_gr_init nvd9_grctx_init_prop_0[];
+extern const struct nvc0_gr_init nvd9_grctx_init_gpc_unk_1[];
+extern const struct nvc0_gr_init nvd9_grctx_init_crstr_0[];
+
+extern const struct nvc0_gr_init nvd9_grctx_init_sm_0[];
+
+extern const struct nvc0_gr_init nvd7_grctx_init_pe_0[];
+
+extern const struct nvc0_gr_init nvd7_grctx_init_wwdx_0[];
+
+extern const struct nvc0_gr_init nve4_grctx_init_memfmt_0[];
+extern const struct nvc0_gr_init nve4_grctx_init_ds_0[];
+extern const struct nvc0_gr_init nve4_grctx_init_scc_0[];
+
+extern const struct nvc0_gr_init nve4_grctx_init_gpm_0[];
+
+extern const struct nvc0_gr_init nve4_grctx_init_pes_0[];
+
+extern const struct nvc0_gr_pack nve4_grctx_pack_hub[];
+extern const struct nvc0_gr_pack nve4_grctx_pack_gpc[];
+extern const struct nvc0_gr_pack nve4_grctx_pack_tpc[];
+extern const struct nvc0_gr_pack nve4_grctx_pack_ppc[];
+extern const struct nvc0_gr_pack nve4_grctx_pack_icmd[];
+extern const struct nvc0_gr_init nve4_grctx_init_a097_0[];
+
+extern const struct nvc0_gr_pack nvf0_grctx_pack_icmd[];
+
+extern const struct nvc0_gr_pack nvf0_grctx_pack_mthd[];
+
+extern const struct nvc0_gr_pack nvf0_grctx_pack_hub[];
+extern const struct nvc0_gr_init nvf0_grctx_init_pri_0[];
+extern const struct nvc0_gr_init nvf0_grctx_init_cwd_0[];
+
+extern const struct nvc0_gr_pack nvf0_grctx_pack_gpc[];
+extern const struct nvc0_gr_init nvf0_grctx_init_gpc_unk_2[];
+
+extern const struct nvc0_gr_init nvf0_grctx_init_tex_0[];
+extern const struct nvc0_gr_init nvf0_grctx_init_mpc_0[];
+extern const struct nvc0_gr_init nvf0_grctx_init_l1c_0[];
+
+extern const struct nvc0_gr_pack nvf0_grctx_pack_ppc[];
+
+extern const struct nvc0_gr_init nv108_grctx_init_rstr2d_0[];
+
+extern const struct nvc0_gr_init nv108_grctx_init_prop_0[];
+extern const struct nvc0_gr_init nv108_grctx_init_crstr_0[];
+
+
+#endif

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc1.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc1_grctx_init_icmd_0[] = {
 	{ 0x001000,   1, 0x01, 0x00000004 },
 	{ 0x0000a9,   1, 0x01, 0x0000ffff },
@@ -267,13 +267,13 @@ nvc1_grctx_init_icmd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc1_grctx_pack_icmd[] = {
 	{ nvc1_grctx_init_icmd_0 },
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc1_grctx_init_9097_0[] = {
 	{ 0x000800,   8, 0x40, 0x00000000 },
 	{ 0x000804,   8, 0x40, 0x00000000 },
@@ -575,14 +575,14 @@ nvc1_grctx_init_9097_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc1_grctx_init_9197_0[] = {
 	{ 0x003400, 128, 0x04, 0x00000000 },
 	{ 0x0002e4,   1, 0x04, 0x0000b001 },
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc1_grctx_pack_mthd[] = {
 	{ nvc1_grctx_init_9097_0, 0x9097 },
 	{ nvc1_grctx_init_9197_0, 0x9197 },
@@ -592,7 +592,7 @@ nvc1_grctx_pack_mthd[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc1_grctx_init_ds_0[] = {
 	{ 0x405800,   1, 0x04, 0x0f8000bf },
 	{ 0x405830,   1, 0x04, 0x02180218 },
@@ -604,7 +604,7 @@ nvc1_grctx_init_ds_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc1_grctx_init_pd_0[] = {
 	{ 0x406020,   1, 0x04, 0x000103c1 },
 	{ 0x406028,   4, 0x04, 0x00000001 },
@@ -616,7 +616,7 @@ nvc1_grctx_init_pd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc1_grctx_init_be_0[] = {
 	{ 0x408800,   1, 0x04, 0x02802a3c },
 	{ 0x408804,   1, 0x04, 0x00000040 },
@@ -628,7 +628,7 @@ nvc1_grctx_init_be_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc1_grctx_pack_hub[] = {
 	{ nvc0_grctx_init_main_0 },
 	{ nvc0_grctx_init_fe_0 },
@@ -642,7 +642,7 @@ nvc1_grctx_pack_hub[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc1_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x0006860a },
 	{ 0x418808,   3, 0x04, 0x00000000 },
@@ -655,7 +655,7 @@ nvc1_grctx_init_setup_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc1_grctx_init_gpm_0[] = {
 	{ 0x418c08,   1, 0x04, 0x00000001 },
 	{ 0x418c10,   8, 0x04, 0x00000000 },
@@ -665,7 +665,7 @@ nvc1_grctx_init_gpm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc1_grctx_pack_gpc[] = {
 	{ nvc0_grctx_init_gpc_unk_0 },
 	{ nvc0_grctx_init_prop_0 },
@@ -678,7 +678,7 @@ nvc1_grctx_pack_gpc[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc1_grctx_init_pe_0[] = {
 	{ 0x419818,   1, 0x04, 0x00000000 },
 	{ 0x41983c,   1, 0x04, 0x00038bc7 },
@@ -688,7 +688,7 @@ nvc1_grctx_init_pe_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc1_grctx_init_wwdx_0[] = {
 	{ 0x419b00,   1, 0x04, 0x0a418820 },
 	{ 0x419b04,   1, 0x04, 0x062080e6 },
@@ -702,7 +702,7 @@ nvc1_grctx_init_wwdx_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc1_grctx_init_tpccs_0[] = {
 	{ 0x419d20,   1, 0x04, 0x12180000 },
 	{ 0x419d24,   1, 0x04, 0x00001fff },
@@ -710,7 +710,7 @@ nvc1_grctx_init_tpccs_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc1_grctx_pack_tpc[] = {
 	{ nvc1_grctx_init_pe_0 },
 	{ nvc4_grctx_init_tex_0 },
@@ -729,7 +729,7 @@ nvc1_grctx_pack_tpc[] = {
 void
 nvc1_grctx_generate_attrib(struct nvc0_grctx *info)
 {
-	struct nvc0_graph_priv *priv = info->priv;
+	struct nvc0_gr_priv *priv = info->priv;
 	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
 	const u32  alpha = impl->alpha_nr;
 	const u32   beta = impl->attrib_nr;
@@ -764,7 +764,7 @@ nvc1_grctx_generate_attrib(struct nvc0_grctx *info)
 }
 
 void
-nvc1_grctx_generate_unkn(struct nvc0_graph_priv *priv)
+nvc1_grctx_generate_unkn(struct nvc0_gr_priv *priv)
 {
 	nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
 	nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
@@ -778,12 +778,12 @@ struct nouveau_oclass *
 nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xc1),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nvc0_grctx_generate_main,
 	.unkn  = nvc1_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc4.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc4_grctx_init_tex_0[] = {
 	{ 0x419a00,   1, 0x04, 0x000001f0 },
 	{ 0x419a04,   1, 0x04, 0x00000001 },
@@ -42,7 +42,7 @@ nvc4_grctx_init_tex_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc4_grctx_init_l1c_0[] = {
 	{ 0x419cb0,   1, 0x04, 0x00020048 },
 	{ 0x419ce8,   1, 0x04, 0x00000000 },
@@ -50,7 +50,7 @@ nvc4_grctx_init_l1c_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc4_grctx_init_sm_0[] = {
 	{ 0x419e04,   3, 0x04, 0x00000000 },
 	{ 0x419e10,   1, 0x04, 0x00000002 },
@@ -64,7 +64,7 @@ nvc4_grctx_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc4_grctx_pack_tpc[] = {
 	{ nvc0_grctx_init_pe_0 },
 	{ nvc4_grctx_init_tex_0 },
@@ -84,12 +84,12 @@ struct nouveau_oclass *
 nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xc3),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nvc0_grctx_generate_main,
 	.unkn  = nvc0_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvc8.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc8_grctx_init_icmd_0[] = {
 	{ 0x001000,   1, 0x01, 0x00000004 },
 	{ 0x0000a9,   1, 0x01, 0x0000ffff },
@@ -268,19 +268,19 @@ nvc8_grctx_init_icmd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc8_grctx_pack_icmd[] = {
 	{ nvc8_grctx_init_icmd_0 },
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc8_grctx_init_9197_0[] = {
 	{ 0x0002e4,   1, 0x04, 0x0000b001 },
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvc8_grctx_init_9297_0[] = {
 	{ 0x003400, 128, 0x04, 0x00000000 },
 	{ 0x00036c,   2, 0x04, 0x00000000 },
@@ -290,7 +290,7 @@ nvc8_grctx_init_9297_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc8_grctx_pack_mthd[] = {
 	{ nvc1_grctx_init_9097_0, 0x9097 },
 	{ nvc8_grctx_init_9197_0, 0x9197 },
@@ -301,7 +301,7 @@ nvc8_grctx_pack_mthd[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvc8_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x0006860a },
 	{ 0x418808,   3, 0x04, 0x00000000 },
@@ -314,7 +314,7 @@ nvc8_grctx_init_setup_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvc8_grctx_pack_gpc[] = {
 	{ nvc0_grctx_init_gpc_unk_0 },
 	{ nvc0_grctx_init_prop_0 },
@@ -335,12 +335,12 @@ struct nouveau_oclass *
 nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xc8),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nvc0_grctx_generate_main,
 	.unkn  = nvc0_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd7.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd7_grctx_init_ds_0[] = {
 	{ 0x405800,   1, 0x04, 0x0f8000bf },
 	{ 0x405830,   1, 0x04, 0x02180324 },
@@ -41,7 +41,7 @@ nvd7_grctx_init_ds_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd7_grctx_init_pd_0[] = {
 	{ 0x406020,   1, 0x04, 0x000103c1 },
 	{ 0x406028,   4, 0x04, 0x00000001 },
@@ -54,7 +54,7 @@ nvd7_grctx_init_pd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvd7_grctx_pack_hub[] = {
 	{ nvc0_grctx_init_main_0 },
 	{ nvd9_grctx_init_fe_0 },
@@ -68,7 +68,7 @@ nvd7_grctx_pack_hub[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd7_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x7006860a },
 	{ 0x418808,   3, 0x04, 0x00000000 },
@@ -81,7 +81,7 @@ nvd7_grctx_init_setup_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvd7_grctx_pack_gpc[] = {
 	{ nvc0_grctx_init_gpc_unk_0 },
 	{ nvd9_grctx_init_prop_0 },
@@ -94,7 +94,7 @@ nvd7_grctx_pack_gpc[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd7_grctx_init_pe_0[] = {
 	{ 0x419848,   1, 0x04, 0x00000000 },
 	{ 0x419864,   1, 0x04, 0x00000129 },
@@ -102,7 +102,7 @@ nvd7_grctx_init_pe_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd7_grctx_init_tex_0[] = {
 	{ 0x419a00,   1, 0x04, 0x000001f0 },
 	{ 0x419a04,   1, 0x04, 0x00000001 },
@@ -116,7 +116,7 @@ nvd7_grctx_init_tex_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd7_grctx_init_mpc_0[] = {
 	{ 0x419c00,   1, 0x04, 0x0000000a },
 	{ 0x419c04,   1, 0x04, 0x00000006 },
@@ -127,7 +127,7 @@ nvd7_grctx_init_mpc_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvd7_grctx_pack_tpc[] = {
 	{ nvd7_grctx_init_pe_0 },
 	{ nvd7_grctx_init_tex_0 },
@@ -137,13 +137,13 @@ nvd7_grctx_pack_tpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd7_grctx_init_pes_0[] = {
 	{ 0x41be24,   1, 0x04, 0x00000002 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd7_grctx_init_cbm_0[] = {
 	{ 0x41bec0,   1, 0x04, 0x12180000 },
 	{ 0x41bec4,   1, 0x04, 0x00003fff },
@@ -151,7 +151,7 @@ nvd7_grctx_init_cbm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd7_grctx_init_wwdx_0[] = {
 	{ 0x41bf00,   1, 0x04, 0x0a418820 },
 	{ 0x41bf04,   1, 0x04, 0x062080e6 },
@@ -165,7 +165,7 @@ nvd7_grctx_init_wwdx_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvd7_grctx_pack_ppc[] = {
 	{ nvd7_grctx_init_pes_0 },
 	{ nvd7_grctx_init_cbm_0 },
@@ -180,7 +180,7 @@ nvd7_grctx_pack_ppc[] = {
 void
 nvd7_grctx_generate_attrib(struct nvc0_grctx *info)
 {
-	struct nvc0_graph_priv *priv = info->priv;
+	struct nvc0_gr_priv *priv = info->priv;
 	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
 	const u32  alpha = impl->alpha_nr;
 	const u32   beta = impl->attrib_nr;
@@ -215,18 +215,18 @@ nvd7_grctx_generate_attrib(struct nvc0_grctx *info)
 }
 
 void
-nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+nvd7_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
 {
 	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
 	int i;
 
 	nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
 
-	nvc0_graph_mmio(priv, oclass->hub);
-	nvc0_graph_mmio(priv, oclass->gpc);
-	nvc0_graph_mmio(priv, oclass->zcull);
-	nvc0_graph_mmio(priv, oclass->tpc);
-	nvc0_graph_mmio(priv, oclass->ppc);
+	nvc0_gr_mmio(priv, oclass->hub);
+	nvc0_gr_mmio(priv, oclass->gpc);
+	nvc0_gr_mmio(priv, oclass->zcull);
+	nvc0_gr_mmio(priv, oclass->tpc);
+	nvc0_gr_mmio(priv, oclass->ppc);
 
 	nv_wr32(priv, 0x404154, 0x00000000);
 
@@ -244,9 +244,9 @@ nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
 	for (i = 0; i < 8; i++)
 		nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
 
-	nvc0_graph_icmd(priv, oclass->icmd);
+	nvc0_gr_icmd(priv, oclass->icmd);
 	nv_wr32(priv, 0x404154, 0x00000400);
-	nvc0_graph_mthd(priv, oclass->mthd);
+	nvc0_gr_mthd(priv, oclass->mthd);
 	nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
 }
 
@@ -254,12 +254,12 @@ struct nouveau_oclass *
 nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xd7),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nvd7_grctx_generate_main,
 	.unkn  = nve4_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvd9.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd9_grctx_init_icmd_0[] = {
 	{ 0x001000,   1, 0x01, 0x00000004 },
 	{ 0x0000a9,   1, 0x01, 0x0000ffff },
@@ -270,13 +270,13 @@ nvd9_grctx_init_icmd_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvd9_grctx_pack_icmd[] = {
 	{ nvd9_grctx_init_icmd_0 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd9_grctx_init_90c0_0[] = {
 	{ 0x002700,   8, 0x20, 0x00000000 },
 	{ 0x002704,   8, 0x20, 0x00000000 },
@@ -299,7 +299,7 @@ nvd9_grctx_init_90c0_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvd9_grctx_pack_mthd[] = {
 	{ nvc1_grctx_init_9097_0, 0x9097 },
 	{ nvc8_grctx_init_9197_0, 0x9197 },
@@ -310,7 +310,7 @@ nvd9_grctx_pack_mthd[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd9_grctx_init_fe_0[] = {
 	{ 0x404004,  10, 0x04, 0x00000000 },
 	{ 0x404044,   1, 0x04, 0x00000000 },
@@ -331,7 +331,7 @@ nvd9_grctx_init_fe_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd9_grctx_init_ds_0[] = {
 	{ 0x405800,   1, 0x04, 0x0f8000bf },
 	{ 0x405830,   1, 0x04, 0x02180218 },
@@ -344,7 +344,7 @@ nvd9_grctx_init_ds_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd9_grctx_init_pd_0[] = {
 	{ 0x406020,   1, 0x04, 0x000103c1 },
 	{ 0x406028,   4, 0x04, 0x00000001 },
@@ -356,7 +356,7 @@ nvd9_grctx_init_pd_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd9_grctx_init_be_0[] = {
 	{ 0x408800,   1, 0x04, 0x02802a3c },
 	{ 0x408804,   1, 0x04, 0x00000040 },
@@ -368,7 +368,7 @@ nvd9_grctx_init_be_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvd9_grctx_pack_hub[] = {
 	{ nvc0_grctx_init_main_0 },
 	{ nvd9_grctx_init_fe_0 },
@@ -382,7 +382,7 @@ nvd9_grctx_pack_hub[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd9_grctx_init_prop_0[] = {
 	{ 0x418400,   1, 0x04, 0x38004e00 },
 	{ 0x418404,   1, 0x04, 0x71e0ffff },
@@ -395,7 +395,7 @@ nvd9_grctx_init_prop_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd9_grctx_init_gpc_unk_1[] = {
 	{ 0x418600,   1, 0x04, 0x0000001f },
 	{ 0x418684,   1, 0x04, 0x0000000f },
@@ -405,7 +405,7 @@ nvd9_grctx_init_gpc_unk_1[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd9_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x7006860a },
 	{ 0x418808,   3, 0x04, 0x00000000 },
@@ -418,7 +418,7 @@ nvd9_grctx_init_setup_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd9_grctx_init_crstr_0[] = {
 	{ 0x418b00,   1, 0x04, 0x00000006 },
 	{ 0x418b08,   1, 0x04, 0x0a418820 },
@@ -431,7 +431,7 @@ nvd9_grctx_init_crstr_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvd9_grctx_pack_gpc[] = {
 	{ nvc0_grctx_init_gpc_unk_0 },
 	{ nvd9_grctx_init_prop_0 },
@@ -444,7 +444,7 @@ nvd9_grctx_pack_gpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd9_grctx_init_tex_0[] = {
 	{ 0x419a00,   1, 0x04, 0x000001f0 },
 	{ 0x419a04,   1, 0x04, 0x00000001 },
@@ -458,7 +458,7 @@ nvd9_grctx_init_tex_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvd9_grctx_init_mpc_0[] = {
 	{ 0x419c00,   1, 0x04, 0x0000000a },
 	{ 0x419c04,   1, 0x04, 0x00000006 },
@@ -469,7 +469,7 @@ nvd9_grctx_init_mpc_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvd9_grctx_init_sm_0[] = {
 	{ 0x419e04,   3, 0x04, 0x00000000 },
 	{ 0x419e10,   1, 0x04, 0x00000002 },
@@ -483,7 +483,7 @@ nvd9_grctx_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvd9_grctx_pack_tpc[] = {
 	{ nvc1_grctx_init_pe_0 },
 	{ nvd9_grctx_init_tex_0 },
@@ -503,12 +503,12 @@ struct nouveau_oclass *
 nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xd9),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nvc0_grctx_generate_main,
 	.unkn  = nvc1_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnve4.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_icmd_0[] = {
 	{ 0x001000,   1, 0x01, 0x00000004 },
 	{ 0x000039,   3, 0x01, 0x00000000 },
@@ -272,13 +272,13 @@ nve4_grctx_init_icmd_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nve4_grctx_pack_icmd[] = {
 	{ nve4_grctx_init_icmd_0 },
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nve4_grctx_init_a097_0[] = {
 	{ 0x000800,   8, 0x40, 0x00000000 },
 	{ 0x000804,   8, 0x40, 0x00000000 },
@@ -578,14 +578,14 @@ nve4_grctx_init_a097_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nve4_grctx_pack_mthd[] = {
 	{ nve4_grctx_init_a097_0, 0xa097 },
 	{ nvc0_grctx_init_902d_0, 0x902d },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_fe_0[] = {
 	{ 0x404010,   5, 0x04, 0x00000000 },
 	{ 0x404024,   1, 0x04, 0x0000e000 },
@@ -606,7 +606,7 @@ nve4_grctx_init_fe_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nve4_grctx_init_memfmt_0[] = {
 	{ 0x404604,   1, 0x04, 0x00000014 },
 	{ 0x404608,   1, 0x04, 0x00000000 },
@@ -632,7 +632,7 @@ nve4_grctx_init_memfmt_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nve4_grctx_init_ds_0[] = {
 	{ 0x405800,   1, 0x04, 0x0f8000bf },
 	{ 0x405830,   1, 0x04, 0x02180648 },
@@ -645,14 +645,14 @@ nve4_grctx_init_ds_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_cwd_0[] = {
 	{ 0x405b00,   1, 0x04, 0x00000000 },
 	{ 0x405b10,   1, 0x04, 0x00001000 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_pd_0[] = {
 	{ 0x406020,   1, 0x04, 0x004103c1 },
 	{ 0x406028,   4, 0x04, 0x00000001 },
@@ -667,13 +667,13 @@ nve4_grctx_init_pd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_sked_0[] = {
 	{ 0x407040,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nve4_grctx_init_scc_0[] = {
 	{ 0x408000,   2, 0x04, 0x00000000 },
 	{ 0x408008,   1, 0x04, 0x00000030 },
@@ -684,7 +684,7 @@ nve4_grctx_init_scc_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_be_0[] = {
 	{ 0x408800,   1, 0x04, 0x02802a3c },
 	{ 0x408804,   1, 0x04, 0x00000040 },
@@ -697,7 +697,7 @@ nve4_grctx_init_be_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nve4_grctx_pack_hub[] = {
 	{ nvc0_grctx_init_main_0 },
 	{ nve4_grctx_init_fe_0 },
@@ -713,7 +713,7 @@ nve4_grctx_pack_hub[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x7006860a },
 	{ 0x418808,   3, 0x04, 0x00000000 },
@@ -726,7 +726,7 @@ nve4_grctx_init_setup_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nve4_grctx_init_gpm_0[] = {
 	{ 0x418c08,   1, 0x04, 0x00000001 },
 	{ 0x418c10,   8, 0x04, 0x00000000 },
@@ -737,7 +737,7 @@ nve4_grctx_init_gpm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nve4_grctx_pack_gpc[] = {
 	{ nvc0_grctx_init_gpc_unk_0 },
 	{ nvd9_grctx_init_prop_0 },
@@ -750,7 +750,7 @@ nve4_grctx_pack_gpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_tex_0[] = {
 	{ 0x419a00,   1, 0x04, 0x000000f0 },
 	{ 0x419a04,   1, 0x04, 0x00000001 },
@@ -765,7 +765,7 @@ nve4_grctx_init_tex_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_mpc_0[] = {
 	{ 0x419c00,   1, 0x04, 0x0000000a },
 	{ 0x419c04,   1, 0x04, 0x80000006 },
@@ -776,14 +776,14 @@ nve4_grctx_init_mpc_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_l1c_0[] = {
 	{ 0x419ce8,   1, 0x04, 0x00000000 },
 	{ 0x419cf4,   1, 0x04, 0x00003203 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_sm_0[] = {
 	{ 0x419e04,   3, 0x04, 0x00000000 },
 	{ 0x419e10,   1, 0x04, 0x00000402 },
@@ -802,7 +802,7 @@ nve4_grctx_init_sm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nve4_grctx_pack_tpc[] = {
 	{ nvd7_grctx_init_pe_0 },
 	{ nve4_grctx_init_tex_0 },
@@ -812,13 +812,13 @@ nve4_grctx_pack_tpc[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nve4_grctx_init_pes_0[] = {
 	{ 0x41be24,   1, 0x04, 0x00000006 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nve4_grctx_init_cbm_0[] = {
 	{ 0x41bec0,   1, 0x04, 0x12180000 },
 	{ 0x41bec4,   1, 0x04, 0x00037f7f },
@@ -826,7 +826,7 @@ nve4_grctx_init_cbm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nve4_grctx_pack_ppc[] = {
 	{ nve4_grctx_init_pes_0 },
 	{ nve4_grctx_init_cbm_0 },
@@ -870,7 +870,7 @@ nve4_grctx_generate_pagepool(struct nvc0_grctx *info)
 }
 
 void
-nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv)
+nve4_grctx_generate_unkn(struct nvc0_gr_priv *priv)
 {
 	nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
 	nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
@@ -881,7 +881,7 @@ nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv)
 }
 
 void
-nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
+nve4_grctx_generate_r418bb8(struct nvc0_gr_priv *priv)
 {
 	u32 data[6] = {}, data2[2] = {};
 	u8  tpcnr[GPC_MAX];
@@ -939,18 +939,18 @@ nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
 }
 
 void
-nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+nve4_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
 {
 	struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
 	int i;
 
 	nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
 
-	nvc0_graph_mmio(priv, oclass->hub);
-	nvc0_graph_mmio(priv, oclass->gpc);
-	nvc0_graph_mmio(priv, oclass->zcull);
-	nvc0_graph_mmio(priv, oclass->tpc);
-	nvc0_graph_mmio(priv, oclass->ppc);
+	nvc0_gr_mmio(priv, oclass->hub);
+	nvc0_gr_mmio(priv, oclass->gpc);
+	nvc0_gr_mmio(priv, oclass->zcull);
+	nvc0_gr_mmio(priv, oclass->tpc);
+	nvc0_gr_mmio(priv, oclass->ppc);
 
 	nv_wr32(priv, 0x404154, 0x00000000);
 
@@ -977,9 +977,9 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
 	}
 	nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
 
-	nvc0_graph_icmd(priv, oclass->icmd);
+	nvc0_gr_icmd(priv, oclass->icmd);
 	nv_wr32(priv, 0x404154, 0x00000400);
-	nvc0_graph_mthd(priv, oclass->mthd);
+	nvc0_gr_mthd(priv, oclass->mthd);
 	nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
 
 	nv_mask(priv, 0x418800, 0x00200000, 0x00200000);
@@ -990,12 +990,12 @@ struct nouveau_oclass *
 nve4_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xe4),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nve4_grctx_generate_main,
 	.unkn  = nve4_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/ctxnvf0.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c

@@ -28,7 +28,7 @@
  * PGRAPH context register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_icmd_0[] = {
 	{ 0x001000,   1, 0x01, 0x00000004 },
 	{ 0x000039,   3, 0x01, 0x00000000 },
@@ -279,13 +279,13 @@ nvf0_grctx_init_icmd_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvf0_grctx_pack_icmd[] = {
 	{ nvf0_grctx_init_icmd_0 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_a197_0[] = {
 	{ 0x000800,   8, 0x40, 0x00000000 },
 	{ 0x000804,   8, 0x40, 0x00000000 },
@@ -587,14 +587,14 @@ nvf0_grctx_init_a197_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvf0_grctx_pack_mthd[] = {
 	{ nvf0_grctx_init_a197_0, 0xa197 },
 	{ nvc0_grctx_init_902d_0, 0x902d },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_fe_0[] = {
 	{ 0x404004,   8, 0x04, 0x00000000 },
 	{ 0x404024,   1, 0x04, 0x0000e000 },
@@ -620,7 +620,7 @@ nvf0_grctx_init_fe_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvf0_grctx_init_pri_0[] = {
 	{ 0x404404,  12, 0x04, 0x00000000 },
 	{ 0x404438,   1, 0x04, 0x00000000 },
@@ -632,7 +632,7 @@ nvf0_grctx_init_pri_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvf0_grctx_init_cwd_0[] = {
 	{ 0x405b00,   1, 0x04, 0x00000000 },
 	{ 0x405b10,   1, 0x04, 0x00001000 },
@@ -640,7 +640,7 @@ nvf0_grctx_init_cwd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_pd_0[] = {
 	{ 0x406020,   1, 0x04, 0x034103c1 },
 	{ 0x406028,   4, 0x04, 0x00000001 },
@@ -655,7 +655,7 @@ nvf0_grctx_init_pd_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_be_0[] = {
 	{ 0x408800,   1, 0x04, 0x12802a3c },
 	{ 0x408804,   1, 0x04, 0x00000040 },
@@ -668,7 +668,7 @@ nvf0_grctx_init_be_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvf0_grctx_pack_hub[] = {
 	{ nvc0_grctx_init_main_0 },
 	{ nvf0_grctx_init_fe_0 },
@@ -683,7 +683,7 @@ nvf0_grctx_pack_hub[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_setup_0[] = {
 	{ 0x418800,   1, 0x04, 0x7006860a },
 	{ 0x418808,   1, 0x04, 0x00000000 },
@@ -698,13 +698,13 @@ nvf0_grctx_init_setup_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvf0_grctx_init_gpc_unk_2[] = {
 	{ 0x418d24,   1, 0x04, 0x00000000 },
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvf0_grctx_pack_gpc[] = {
 	{ nvc0_grctx_init_gpc_unk_0 },
 	{ nvd9_grctx_init_prop_0 },
@@ -718,7 +718,7 @@ nvf0_grctx_pack_gpc[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvf0_grctx_init_tex_0[] = {
 	{ 0x419a00,   1, 0x04, 0x000000f0 },
 	{ 0x419a04,   1, 0x04, 0x00000001 },
@@ -733,7 +733,7 @@ nvf0_grctx_init_tex_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvf0_grctx_init_mpc_0[] = {
 	{ 0x419c00,   1, 0x04, 0x0000001a },
 	{ 0x419c04,   1, 0x04, 0x80000006 },
@@ -744,14 +744,14 @@ nvf0_grctx_init_mpc_0[] = {
 	{}
 };
 
-const struct nvc0_graph_init
+const struct nvc0_gr_init
 nvf0_grctx_init_l1c_0[] = {
 	{ 0x419ce8,   1, 0x04, 0x00000000 },
 	{ 0x419cf4,   1, 0x04, 0x00000203 },
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_sm_0[] = {
 	{ 0x419e04,   1, 0x04, 0x00000000 },
 	{ 0x419e08,   1, 0x04, 0x0000001d },
@@ -779,7 +779,7 @@ nvf0_grctx_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
+static const struct nvc0_gr_pack
 nvf0_grctx_pack_tpc[] = {
 	{ nvd7_grctx_init_pe_0 },
 	{ nvf0_grctx_init_tex_0 },
@@ -789,7 +789,7 @@ nvf0_grctx_pack_tpc[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
+static const struct nvc0_gr_init
 nvf0_grctx_init_cbm_0[] = {
 	{ 0x41bec0,   1, 0x04, 0x10000000 },
 	{ 0x41bec4,   1, 0x04, 0x00037f7f },
@@ -797,7 +797,7 @@ nvf0_grctx_init_cbm_0[] = {
 	{}
 };
 
-const struct nvc0_graph_pack
+const struct nvc0_gr_pack
 nvf0_grctx_pack_ppc[] = {
 	{ nve4_grctx_init_pes_0 },
 	{ nvf0_grctx_init_cbm_0 },
@@ -813,12 +813,12 @@ struct nouveau_oclass *
 nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) {
 	.base.handle = NV_ENGCTX(GR, 0xf0),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_context_ctor,
-		.dtor = nvc0_graph_context_dtor,
-		.init = _nouveau_graph_context_init,
-		.fini = _nouveau_graph_context_fini,
-		.rd32 = _nouveau_graph_context_rd32,
-		.wr32 = _nouveau_graph_context_wr32,
+		.ctor = nvc0_gr_context_ctor,
+		.dtor = nvc0_gr_context_dtor,
+		.init = _nouveau_gr_context_init,
+		.fini = _nouveau_gr_context_fini,
+		.rd32 = _nouveau_gr_context_rd32,
+		.wr32 = _nouveau_gr_context_wr32,
 	},
 	.main  = nve4_grctx_generate_main,
 	.unkn  = nve4_grctx_generate_unkn,

drivers/gpu/drm/nouveau/nvkm/engine/graph/gk110b.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c

@@ -29,8 +29,8 @@
  * PGRAPH register lists
  ******************************************************************************/
 
-static const struct nvc0_graph_init
-gk110b_graph_init_l1c_0[] = {
+static const struct nvc0_gr_init
+gk110b_gr_init_l1c_0[] = {
 	{ 0x419c98,   1, 0x04, 0x00000000 },
 	{ 0x419ca8,   1, 0x04, 0x00000000 },
 	{ 0x419cb0,   1, 0x04, 0x09000000 },
@@ -44,8 +44,8 @@ gk110b_graph_init_l1c_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_init
-gk110b_graph_init_sm_0[] = {
+static const struct nvc0_gr_init
+gk110b_gr_init_sm_0[] = {
 	{ 0x419e00,   1, 0x04, 0x00000080 },
 	{ 0x419ea0,   1, 0x04, 0x00000000 },
 	{ 0x419ee4,   1, 0x04, 0x00000000 },
@@ -61,37 +61,37 @@ gk110b_graph_init_sm_0[] = {
 	{}
 };
 
-static const struct nvc0_graph_pack
-gk110b_graph_pack_mmio[] = {
-	{ nve4_graph_init_main_0 },
-	{ nvf0_graph_init_fe_0 },
-	{ nvc0_graph_init_pri_0 },
-	{ nvc0_graph_init_rstr2d_0 },
-	{ nvd9_graph_init_pd_0 },
-	{ nvf0_graph_init_ds_0 },
-	{ nvc0_graph_init_scc_0 },
-	{ nvf0_graph_init_sked_0 },
-	{ nvf0_graph_init_cwd_0 },
-	{ nvd9_graph_init_prop_0 },
-	{ nvc1_graph_init_gpc_unk_0 },
-	{ nvc0_graph_init_setup_0 },
-	{ nvc0_graph_init_crstr_0 },
-	{ nvc1_graph_init_setup_1 },
-	{ nvc0_graph_init_zcull_0 },
-	{ nvd9_graph_init_gpm_0 },
-	{ nvf0_graph_init_gpc_unk_1 },
-	{ nvc0_graph_init_gcc_0 },
-	{ nve4_graph_init_tpccs_0 },
-	{ nvf0_graph_init_tex_0 },
-	{ nve4_graph_init_pe_0 },
-	{ gk110b_graph_init_l1c_0 },
-	{ nvc0_graph_init_mpc_0 },
-	{ gk110b_graph_init_sm_0 },
-	{ nvd7_graph_init_pes_0 },
-	{ nvd7_graph_init_wwdx_0 },
-	{ nvd7_graph_init_cbm_0 },
-	{ nve4_graph_init_be_0 },
-	{ nvc0_graph_init_fe_1 },
+static const struct nvc0_gr_pack
+gk110b_gr_pack_mmio[] = {
+	{ nve4_gr_init_main_0 },
+	{ nvf0_gr_init_fe_0 },
+	{ nvc0_gr_init_pri_0 },
+	{ nvc0_gr_init_rstr2d_0 },
+	{ nvd9_gr_init_pd_0 },
+	{ nvf0_gr_init_ds_0 },
+	{ nvc0_gr_init_scc_0 },
+	{ nvf0_gr_init_sked_0 },
+	{ nvf0_gr_init_cwd_0 },
+	{ nvd9_gr_init_prop_0 },
+	{ nvc1_gr_init_gpc_unk_0 },
+	{ nvc0_gr_init_setup_0 },
+	{ nvc0_gr_init_crstr_0 },
+	{ nvc1_gr_init_setup_1 },
+	{ nvc0_gr_init_zcull_0 },
+	{ nvd9_gr_init_gpm_0 },
+	{ nvf0_gr_init_gpc_unk_1 },
+	{ nvc0_gr_init_gcc_0 },
+	{ nve4_gr_init_tpccs_0 },
+	{ nvf0_gr_init_tex_0 },
+	{ nve4_gr_init_pe_0 },
+	{ gk110b_gr_init_l1c_0 },
+	{ nvc0_gr_init_mpc_0 },
+	{ gk110b_gr_init_sm_0 },
+	{ nvd7_gr_init_pes_0 },
+	{ nvd7_gr_init_wwdx_0 },
+	{ nvd7_gr_init_cbm_0 },
+	{ nve4_gr_init_be_0 },
+	{ nvc0_gr_init_fe_1 },
 	{}
 };
 
@@ -100,18 +100,18 @@ gk110b_graph_pack_mmio[] = {
  ******************************************************************************/
 
 struct nouveau_oclass *
-gk110b_graph_oclass = &(struct nvc0_graph_oclass) {
+gk110b_gr_oclass = &(struct nvc0_gr_oclass) {
 	.base.handle = NV_ENGINE(GR, 0xf1),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nve4_graph_init,
-		.fini = nvf0_graph_fini,
+		.ctor = nvc0_gr_ctor,
+		.dtor = nvc0_gr_dtor,
+		.init = nve4_gr_init,
+		.fini = nvf0_gr_fini,
 	},
 	.cclass = &gk110b_grctx_oclass,
-	.sclass =  nvf0_graph_sclass,
-	.mmio = gk110b_graph_pack_mmio,
-	.fecs.ucode = &nvf0_graph_fecs_ucode,
-	.gpccs.ucode = &nvf0_graph_gpccs_ucode,
+	.sclass =  nvf0_gr_sclass,
+	.mmio = gk110b_gr_pack_mmio,
+	.fecs.ucode = &nvf0_gr_fecs_ucode,
+	.gpccs.ucode = &nvf0_gr_gpccs_ucode,
 	.ppc_nr = 2,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/graph/gk20a.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c

@@ -24,25 +24,25 @@
 #include "ctxnvc0.h"
 
 static struct nouveau_oclass
-gk20a_graph_sclass[] = {
+gk20a_gr_sclass[] = {
 	{ 0x902d, &nouveau_object_ofuncs },
 	{ 0xa040, &nouveau_object_ofuncs },
-	{ KEPLER_C, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds },
-	{ KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds },
+	{ KEPLER_C, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
+	{ KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
 	{}
 };
 
 struct nouveau_oclass *
-gk20a_graph_oclass = &(struct nvc0_graph_oclass) {
+gk20a_gr_oclass = &(struct nvc0_gr_oclass) {
 	.base.handle = NV_ENGINE(GR, 0xea),
 	.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_graph_ctor,
-		.dtor = nvc0_graph_dtor,
-		.init = nve4_graph_init,
-		.fini = _nouveau_graph_fini,
+		.ctor = nvc0_gr_ctor,
+		.dtor = nvc0_gr_dtor,
+		.init = nve4_gr_init,
+		.fini = _nouveau_gr_fini,
 	},
 	.cclass = &gk20a_grctx_oclass,
-	.sclass = gk20a_graph_sclass,
-	.mmio = nve4_graph_pack_mmio,
+	.sclass = gk20a_gr_sclass,
+	.mmio = nve4_gr_pack_mmio,
 	.ppc_nr = 1,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h

+#ifndef __NV20_GR_H__
+#define __NV20_GR_H__
+
+#include <core/enum.h>
+
+#include <engine/gr.h>
+#include <engine/fifo.h>
+
+struct nv20_gr_priv {
+	struct nouveau_gr base;
+	struct nouveau_gpuobj *ctxtab;
+};
+
+struct nv20_gr_chan {
+	struct nouveau_gr_chan base;
+	int chid;
+};
+
+extern struct nouveau_oclass nv25_gr_sclass[];
+int  nv20_gr_context_init(struct nouveau_object *);
+int  nv20_gr_context_fini(struct nouveau_object *, bool);
+
+void nv20_gr_tile_prog(struct nouveau_engine *, int);
+void nv20_gr_intr(struct nouveau_subdev *);
+
+void nv20_gr_dtor(struct nouveau_object *);
+int  nv20_gr_init(struct nouveau_object *);
+
+int  nv30_gr_init(struct nouveau_object *);
+
+#endif

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv40.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h

-#ifndef __NV40_GRAPH_H__
-#define __NV40_GRAPH_H__
+#ifndef __NV40_GR_H__
+#define __NV40_GR_H__
 
 #include <core/device.h>
 #include <core/gpuobj.h>
@@ -8,7 +8,7 @@
  * helpful to determine a number of other hardware features
  */
 static inline int
-nv44_graph_class(void *priv)
+nv44_gr_class(void *priv)
 {
 	struct nouveau_device *device = nv_device(priv);
 

drivers/gpu/drm/nouveau/nvkm/engine/graph/nv50.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h

-#ifndef __NV50_GRAPH_H__
-#define __NV50_GRAPH_H__
+#ifndef __NV50_GR_H__
+#define __NV50_GR_H__
 
 int  nv50_grctx_init(struct nouveau_device *, u32 *size);
 void nv50_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);

drivers/gpu/drm/nouveau/nvkm/engine/graph/regs.h → drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h

-#ifndef __NOUVEAU_GRAPH_REGS_H__
-#define __NOUVEAU_GRAPH_REGS_H__
+#ifndef __NOUVEAU_GR_REGS_H__
+#define __NOUVEAU_GR_REGS_H__
 
 #define NV04_PGRAPH_DEBUG_0                                0x00400080
 #define NV04_PGRAPH_DEBUG_1                                0x00400084

drivers/gpu/drm/nouveau/nvkm/engine/graph/Kbuild

-nvkm-y += nvkm/engine/graph/ctxnv40.o
-nvkm-y += nvkm/engine/graph/ctxnv50.o
-nvkm-y += nvkm/engine/graph/ctxnvc0.o
-nvkm-y += nvkm/engine/graph/ctxnvc1.o
-nvkm-y += nvkm/engine/graph/ctxnvc4.o
-nvkm-y += nvkm/engine/graph/ctxnvc8.o
-nvkm-y += nvkm/engine/graph/ctxnvd7.o
-nvkm-y += nvkm/engine/graph/ctxnvd9.o
-nvkm-y += nvkm/engine/graph/ctxnve4.o
-nvkm-y += nvkm/engine/graph/ctxgk20a.o
-nvkm-y += nvkm/engine/graph/ctxnvf0.o
-nvkm-y += nvkm/engine/graph/ctxgk110b.o
-nvkm-y += nvkm/engine/graph/ctxnv108.o
-nvkm-y += nvkm/engine/graph/ctxgm107.o
-nvkm-y += nvkm/engine/graph/nv04.o
-nvkm-y += nvkm/engine/graph/nv10.o
-nvkm-y += nvkm/engine/graph/nv20.o
-nvkm-y += nvkm/engine/graph/nv25.o
-nvkm-y += nvkm/engine/graph/nv2a.o
-nvkm-y += nvkm/engine/graph/nv30.o
-nvkm-y += nvkm/engine/graph/nv34.o
-nvkm-y += nvkm/engine/graph/nv35.o
-nvkm-y += nvkm/engine/graph/nv40.o
-nvkm-y += nvkm/engine/graph/nv50.o
-nvkm-y += nvkm/engine/graph/nvc0.o
-nvkm-y += nvkm/engine/graph/nvc1.o
-nvkm-y += nvkm/engine/graph/nvc4.o
-nvkm-y += nvkm/engine/graph/nvc8.o
-nvkm-y += nvkm/engine/graph/nvd7.o
-nvkm-y += nvkm/engine/graph/nvd9.o
-nvkm-y += nvkm/engine/graph/nve4.o
-nvkm-y += nvkm/engine/graph/gk20a.o
-nvkm-y += nvkm/engine/graph/nvf0.o
-nvkm-y += nvkm/engine/graph/gk110b.o
-nvkm-y += nvkm/engine/graph/nv108.o
-nvkm-y += nvkm/engine/graph/gm107.o