Commit bb9c03d8 authored by David S. Miller's avatar David S. Miller
parents 4de57826 abf52f86
...@@ -171,7 +171,7 @@ Where the supported parameter are: ...@@ -171,7 +171,7 @@ Where the supported parameter are:
led led
Can be used to turn on experimental LED code. Can be used to turn on experimental LED code.
0 = Off, 1 = On. Default is 0. 0 = Off, 1 = On. Default is 1.
mode mode
Can be used to set the default mode of the adapter. Can be used to set the default mode of the adapter.
......
...@@ -2978,20 +2978,14 @@ F: drivers/net/ixgb/ ...@@ -2978,20 +2978,14 @@ F: drivers/net/ixgb/
F: drivers/net/ixgbe/ F: drivers/net/ixgbe/
INTEL PRO/WIRELESS 2100 NETWORK CONNECTION SUPPORT INTEL PRO/WIRELESS 2100 NETWORK CONNECTION SUPPORT
M: Reinette Chatre <reinette.chatre@intel.com>
M: Intel Linux Wireless <ilw@linux.intel.com>
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
W: http://ipw2100.sourceforge.net S: Orphan
S: Odd Fixes
F: Documentation/networking/README.ipw2100 F: Documentation/networking/README.ipw2100
F: drivers/net/wireless/ipw2x00/ipw2100.* F: drivers/net/wireless/ipw2x00/ipw2100.*
INTEL PRO/WIRELESS 2915ABG NETWORK CONNECTION SUPPORT INTEL PRO/WIRELESS 2915ABG NETWORK CONNECTION SUPPORT
M: Reinette Chatre <reinette.chatre@intel.com>
M: Intel Linux Wireless <ilw@linux.intel.com>
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
W: http://ipw2200.sourceforge.net S: Orphan
S: Odd Fixes
F: Documentation/networking/README.ipw2200 F: Documentation/networking/README.ipw2200
F: drivers/net/wireless/ipw2x00/ipw2200.* F: drivers/net/wireless/ipw2x00/ipw2200.*
......
...@@ -566,7 +566,7 @@ enum ath5k_pkt_type { ...@@ -566,7 +566,7 @@ enum ath5k_pkt_type {
) )
/* /*
* DMA size definitions (2^n+2) * DMA size definitions (2^(n+2))
*/ */
enum ath5k_dmasize { enum ath5k_dmasize {
AR5K_DMASIZE_4B = 0, AR5K_DMASIZE_4B = 0,
...@@ -1127,15 +1127,10 @@ struct ath5k_hw { ...@@ -1127,15 +1127,10 @@ struct ath5k_hw {
/* /*
* Function pointers * Function pointers
*/ */
int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
u32 size, unsigned int flags);
int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
unsigned int, unsigned int, int, enum ath5k_pkt_type, unsigned int, unsigned int, int, enum ath5k_pkt_type,
unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
unsigned int, unsigned int, unsigned int, unsigned int); unsigned int, unsigned int, unsigned int, unsigned int);
int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
unsigned int, unsigned int, unsigned int, unsigned int,
unsigned int, unsigned int);
int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
struct ath5k_tx_status *); struct ath5k_tx_status *);
int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
...@@ -1236,6 +1231,11 @@ int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time); ...@@ -1236,6 +1231,11 @@ int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
/* Hardware Descriptor Functions */ /* Hardware Descriptor Functions */
int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
u32 size, unsigned int flags);
int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3);
/* GPIO Functions */ /* GPIO Functions */
void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state); void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
......
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...@@ -278,6 +278,7 @@ static ssize_t write_file_reset(struct file *file, ...@@ -278,6 +278,7 @@ static ssize_t write_file_reset(struct file *file,
size_t count, loff_t *ppos) size_t count, loff_t *ppos)
{ {
struct ath5k_softc *sc = file->private_data; struct ath5k_softc *sc = file->private_data;
ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "debug file triggered reset\n");
tasklet_schedule(&sc->restq); tasklet_schedule(&sc->restq);
return count; return count;
} }
...@@ -924,7 +925,7 @@ ath5k_debug_printrxbuf(struct ath5k_buf *bf, int done, ...@@ -924,7 +925,7 @@ ath5k_debug_printrxbuf(struct ath5k_buf *bf, int done,
ds, (unsigned long long)bf->daddr, ds, (unsigned long long)bf->daddr,
ds->ds_link, ds->ds_data, ds->ds_link, ds->ds_data,
rd->rx_ctl.rx_control_0, rd->rx_ctl.rx_control_1, rd->rx_ctl.rx_control_0, rd->rx_ctl.rx_control_1,
rd->u.rx_stat.rx_status_0, rd->u.rx_stat.rx_status_0, rd->rx_stat.rx_status_0, rd->rx_stat.rx_status_1,
!done ? ' ' : (rs->rs_status == 0) ? '*' : '!'); !done ? ' ' : (rs->rs_status == 0) ? '*' : '!');
} }
...@@ -939,7 +940,7 @@ ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah) ...@@ -939,7 +940,7 @@ ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah)
if (likely(!(sc->debug.level & ATH5K_DEBUG_RESET))) if (likely(!(sc->debug.level & ATH5K_DEBUG_RESET)))
return; return;
printk(KERN_DEBUG "rx queue %x, link %p\n", printk(KERN_DEBUG "rxdp %x, rxlink %p\n",
ath5k_hw_get_rxdp(ah), sc->rxlink); ath5k_hw_get_rxdp(ah), sc->rxlink);
spin_lock_bh(&sc->rxbuflock); spin_lock_bh(&sc->rxbuflock);
......
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...@@ -32,7 +32,8 @@ ath9k_hw-y:= \ ...@@ -32,7 +32,8 @@ ath9k_hw-y:= \
mac.o \ mac.o \
ar9002_mac.o \ ar9002_mac.o \
ar9003_mac.o \ ar9003_mac.o \
ar9003_eeprom.o ar9003_eeprom.o \
ar9003_paprd.o
obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o
......
This diff is collapsed.
...@@ -23,23 +23,55 @@ ...@@ -23,23 +23,55 @@
#define BEACON_RSSI(ahp) (ahp->stats.avgbrssi) #define BEACON_RSSI(ahp) (ahp->stats.avgbrssi)
#define ATH9K_ANI_OFDM_TRIG_HIGH 500 /* units are errors per second */
#define ATH9K_ANI_OFDM_TRIG_LOW 200 #define ATH9K_ANI_OFDM_TRIG_HIGH_OLD 500
#define ATH9K_ANI_CCK_TRIG_HIGH 200 #define ATH9K_ANI_OFDM_TRIG_HIGH_NEW 1000
#define ATH9K_ANI_CCK_TRIG_LOW 100
/* units are errors per second */
#define ATH9K_ANI_OFDM_TRIG_LOW_OLD 200
#define ATH9K_ANI_OFDM_TRIG_LOW_NEW 400
/* units are errors per second */
#define ATH9K_ANI_CCK_TRIG_HIGH_OLD 200
#define ATH9K_ANI_CCK_TRIG_HIGH_NEW 600
/* units are errors per second */
#define ATH9K_ANI_CCK_TRIG_LOW_OLD 100
#define ATH9K_ANI_CCK_TRIG_LOW_NEW 300
#define ATH9K_ANI_NOISE_IMMUNE_LVL 4 #define ATH9K_ANI_NOISE_IMMUNE_LVL 4
#define ATH9K_ANI_USE_OFDM_WEAK_SIG true #define ATH9K_ANI_USE_OFDM_WEAK_SIG true
#define ATH9K_ANI_CCK_WEAK_SIG_THR false #define ATH9K_ANI_CCK_WEAK_SIG_THR false
#define ATH9K_ANI_SPUR_IMMUNE_LVL 7
#define ATH9K_ANI_FIRSTEP_LVL 0 #define ATH9K_ANI_SPUR_IMMUNE_LVL_OLD 7
#define ATH9K_ANI_SPUR_IMMUNE_LVL_NEW 3
#define ATH9K_ANI_FIRSTEP_LVL_OLD 0
#define ATH9K_ANI_FIRSTEP_LVL_NEW 2
#define ATH9K_ANI_RSSI_THR_HIGH 40 #define ATH9K_ANI_RSSI_THR_HIGH 40
#define ATH9K_ANI_RSSI_THR_LOW 7 #define ATH9K_ANI_RSSI_THR_LOW 7
#define ATH9K_ANI_PERIOD 100
#define ATH9K_ANI_PERIOD_OLD 100
#define ATH9K_ANI_PERIOD_NEW 1000
/* in ms */
#define ATH9K_ANI_POLLINTERVAL_OLD 100
#define ATH9K_ANI_POLLINTERVAL_NEW 1000
#define HAL_NOISE_IMMUNE_MAX 4 #define HAL_NOISE_IMMUNE_MAX 4
#define HAL_SPUR_IMMUNE_MAX 7 #define HAL_SPUR_IMMUNE_MAX 7
#define HAL_FIRST_STEP_MAX 2 #define HAL_FIRST_STEP_MAX 2
#define ATH9K_SIG_FIRSTEP_SETTING_MIN 0
#define ATH9K_SIG_FIRSTEP_SETTING_MAX 20
#define ATH9K_SIG_SPUR_IMM_SETTING_MIN 0
#define ATH9K_SIG_SPUR_IMM_SETTING_MAX 22
#define ATH9K_ANI_ENABLE_MRC_CCK true
/* values here are relative to the INI */
enum ath9k_ani_cmd { enum ath9k_ani_cmd {
ATH9K_ANI_PRESENT = 0x1, ATH9K_ANI_PRESENT = 0x1,
ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2, ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
...@@ -49,7 +81,8 @@ enum ath9k_ani_cmd { ...@@ -49,7 +81,8 @@ enum ath9k_ani_cmd {
ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20, ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
ATH9K_ANI_MODE = 0x40, ATH9K_ANI_MODE = 0x40,
ATH9K_ANI_PHYERR_RESET = 0x80, ATH9K_ANI_PHYERR_RESET = 0x80,
ATH9K_ANI_ALL = 0xff ATH9K_ANI_MRC_CCK = 0x100,
ATH9K_ANI_ALL = 0xfff
}; };
struct ath9k_mib_stats { struct ath9k_mib_stats {
...@@ -60,9 +93,31 @@ struct ath9k_mib_stats { ...@@ -60,9 +93,31 @@ struct ath9k_mib_stats {
u32 beacons; u32 beacons;
}; };
/* INI default values for ANI registers */
struct ath9k_ani_default {
u16 m1ThreshLow;
u16 m2ThreshLow;
u16 m1Thresh;
u16 m2Thresh;
u16 m2CountThr;
u16 m2CountThrLow;
u16 m1ThreshLowExt;
u16 m2ThreshLowExt;
u16 m1ThreshExt;
u16 m2ThreshExt;
u16 firstep;
u16 firstepLow;
u16 cycpwrThr1;
u16 cycpwrThr1Ext;
};
struct ar5416AniState { struct ar5416AniState {
struct ath9k_channel *c; struct ath9k_channel *c;
u8 noiseImmunityLevel; u8 noiseImmunityLevel;
u8 ofdmNoiseImmunityLevel;
u8 cckNoiseImmunityLevel;
bool ofdmsTurn;
u8 mrcCCKOff;
u8 spurImmunityLevel; u8 spurImmunityLevel;
u8 firstepLevel; u8 firstepLevel;
u8 ofdmWeakSigDetectOff; u8 ofdmWeakSigDetectOff;
...@@ -85,6 +140,7 @@ struct ar5416AniState { ...@@ -85,6 +140,7 @@ struct ar5416AniState {
int16_t pktRssi[2]; int16_t pktRssi[2];
int16_t ofdmErrRssi[2]; int16_t ofdmErrRssi[2];
int16_t cckErrRssi[2]; int16_t cckErrRssi[2];
struct ath9k_ani_default iniDef;
}; };
struct ar5416Stats { struct ar5416Stats {
...@@ -108,15 +164,13 @@ struct ar5416Stats { ...@@ -108,15 +164,13 @@ struct ar5416Stats {
}; };
#define ah_mibStats stats.ast_mibstats #define ah_mibStats stats.ast_mibstats
void ath9k_ani_reset(struct ath_hw *ah);
void ath9k_hw_ani_monitor(struct ath_hw *ah,
struct ath9k_channel *chan);
void ath9k_enable_mib_counters(struct ath_hw *ah); void ath9k_enable_mib_counters(struct ath_hw *ah);
void ath9k_hw_disable_mib_counters(struct ath_hw *ah); void ath9k_hw_disable_mib_counters(struct ath_hw *ah);
u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt, u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt,
u32 *rxf_pcnt, u32 *txf_pcnt); u32 *rxf_pcnt, u32 *txf_pcnt);
void ath9k_hw_procmibevent(struct ath_hw *ah);
void ath9k_hw_ani_setup(struct ath_hw *ah); void ath9k_hw_ani_setup(struct ath_hw *ah);
void ath9k_hw_ani_init(struct ath_hw *ah); void ath9k_hw_ani_init(struct ath_hw *ah);
int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
struct ath9k_channel *chan);
#endif /* ANI_H */ #endif /* ANI_H */
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...@@ -20,6 +20,10 @@ ...@@ -20,6 +20,10 @@
#include "ar9002_initvals.h" #include "ar9002_initvals.h"
#include "ar9002_phy.h" #include "ar9002_phy.h"
int modparam_force_new_ani;
module_param_named(force_new_ani, modparam_force_new_ani, int, 0444);
MODULE_PARM_DESC(nohwcrypt, "Force new ANI for AR5008, AR9001, AR9002");
/* General hardware code for the A5008/AR9001/AR9002 hadware families */ /* General hardware code for the A5008/AR9001/AR9002 hadware families */
static bool ar9002_hw_macversion_supported(u32 macversion) static bool ar9002_hw_macversion_supported(u32 macversion)
...@@ -636,4 +640,9 @@ void ar9002_hw_attach_ops(struct ath_hw *ah) ...@@ -636,4 +640,9 @@ void ar9002_hw_attach_ops(struct ath_hw *ah)
ar9002_hw_attach_calib_ops(ah); ar9002_hw_attach_calib_ops(ah);
ar9002_hw_attach_mac_ops(ah); ar9002_hw_attach_mac_ops(ah);
if (modparam_force_new_ani)
ath9k_hw_attach_ani_ops_new(ah);
else
ath9k_hw_attach_ani_ops_old(ah);
} }
...@@ -114,6 +114,10 @@ ...@@ -114,6 +114,10 @@
#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
#define AR_PHY_FIND_SIG_FIRPWR_S 18 #define AR_PHY_FIND_SIG_FIRPWR_S 18
#define AR_PHY_FIND_SIG_LOW 0x9840
#define AR_PHY_FIND_SIG_FIRSTEP_LOW 0x00000FC0L
#define AR_PHY_FIND_SIG_FIRSTEP_LOW_S 6
#define AR_PHY_AGC_CTL1 0x985C #define AR_PHY_AGC_CTL1 0x985C
#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80 #define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7 #define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
...@@ -325,6 +329,9 @@ ...@@ -325,6 +329,9 @@
#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9 #define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
#define AR_PHY_EXT_CCA_THRESH62 0x007F0000 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000
#define AR_PHY_EXT_CCA_THRESH62_S 16 #define AR_PHY_EXT_CCA_THRESH62_S 16
#define AR_PHY_EXT_TIMING5_CYCPWR_THR1 0x0000FE00L
#define AR_PHY_EXT_TIMING5_CYCPWR_THR1_S 9
#define AR_PHY_EXT_MINCCA_PWR 0xFF800000 #define AR_PHY_EXT_MINCCA_PWR 0xFF800000
#define AR_PHY_EXT_MINCCA_PWR_S 23 #define AR_PHY_EXT_MINCCA_PWR_S 23
#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000 #define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
......
...@@ -67,6 +67,7 @@ static const struct ar9300_eeprom ar9300_default = { ...@@ -67,6 +67,7 @@ static const struct ar9300_eeprom ar9300_default = {
* bit2 - enable fastClock - enabled * bit2 - enable fastClock - enabled
* bit3 - enable doubling - enabled * bit3 - enable doubling - enabled
* bit4 - enable internal regulator - disabled * bit4 - enable internal regulator - disabled
* bit5 - enable pa predistortion - disabled
*/ */
.miscConfiguration = 0, /* bit0 - turn down drivestrength */ .miscConfiguration = 0, /* bit0 - turn down drivestrength */
.eepromWriteEnableGpio = 3, .eepromWriteEnableGpio = 3,
...@@ -129,9 +130,11 @@ static const struct ar9300_eeprom ar9300_default = { ...@@ -129,9 +130,11 @@ static const struct ar9300_eeprom ar9300_default = {
.txEndToRxOn = 0x2, .txEndToRxOn = 0x2,
.txFrameToXpaOn = 0xe, .txFrameToXpaOn = 0xe,
.thresh62 = 28, .thresh62 = 28,
.futureModal = { /* [32] */ .papdRateMaskHt20 = LE32(0x80c080),
.papdRateMaskHt40 = LE32(0x80c080),
.futureModal = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 0, 0, 0, 0, 0, 0, 0, 0
}, },
}, },
.calFreqPier2G = { .calFreqPier2G = {
...@@ -326,9 +329,11 @@ static const struct ar9300_eeprom ar9300_default = { ...@@ -326,9 +329,11 @@ static const struct ar9300_eeprom ar9300_default = {
.txEndToRxOn = 0x2, .txEndToRxOn = 0x2,
.txFrameToXpaOn = 0xe, .txFrameToXpaOn = 0xe,
.thresh62 = 28, .thresh62 = 28,
.papdRateMaskHt20 = LE32(0xf0e0e0),
.papdRateMaskHt40 = LE32(0xf0e0e0),
.futureModal = { .futureModal = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 0, 0, 0, 0, 0, 0, 0, 0
}, },
}, },
.calFreqPier5G = { .calFreqPier5G = {
...@@ -644,6 +649,8 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, ...@@ -644,6 +649,8 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
return (pBase->featureEnable & 0x10) >> 4; return (pBase->featureEnable & 0x10) >> 4;
case EEP_SWREG: case EEP_SWREG:
return le32_to_cpu(pBase->swreg); return le32_to_cpu(pBase->swreg);
case EEP_PAPRD:
return !!(pBase->featureEnable & BIT(5));
default: default:
return 0; return 0;
} }
......
...@@ -234,7 +234,9 @@ struct ar9300_modal_eep_header { ...@@ -234,7 +234,9 @@ struct ar9300_modal_eep_header {
u8 txEndToRxOn; u8 txEndToRxOn;
u8 txFrameToXpaOn; u8 txFrameToXpaOn;
u8 thresh62; u8 thresh62;
u8 futureModal[32]; __le32 papdRateMaskHt20;
__le32 papdRateMaskHt40;
u8 futureModal[24];
} __packed; } __packed;
struct ar9300_cal_data_per_freq_op_loop { struct ar9300_cal_data_per_freq_op_loop {
......
...@@ -313,4 +313,6 @@ void ar9003_hw_attach_ops(struct ath_hw *ah) ...@@ -313,4 +313,6 @@ void ar9003_hw_attach_ops(struct ath_hw *ah)
ar9003_hw_attach_phy_ops(ah); ar9003_hw_attach_phy_ops(ah);
ar9003_hw_attach_calib_ops(ah); ar9003_hw_attach_calib_ops(ah);
ar9003_hw_attach_mac_ops(ah); ar9003_hw_attach_mac_ops(ah);
ath9k_hw_attach_ani_ops_new(ah);
} }
...@@ -470,6 +470,14 @@ static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds, ...@@ -470,6 +470,14 @@ static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
ads->ctl11 &= ~AR_VirtMoreFrag; ads->ctl11 &= ~AR_VirtMoreFrag;
} }
void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains)
{
struct ar9003_txc *ads = ds;
ads->ctl12 |= SM(chains, AR_PAPRDChainMask);
}
EXPORT_SYMBOL(ar9003_hw_set_paprd_txdesc);
void ar9003_hw_attach_mac_ops(struct ath_hw *hw) void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
{ {
struct ath_hw_ops *ops = ath9k_hw_ops(hw); struct ath_hw_ops *ops = ath9k_hw_ops(hw);
......
...@@ -40,6 +40,10 @@ ...@@ -40,6 +40,10 @@
#define AR_Not_Sounding 0x20000000 #define AR_Not_Sounding 0x20000000
/* ctl 12 */
#define AR_PAPRDChainMask 0x00000e00
#define AR_PAPRDChainMask_S 9
#define MAP_ISR_S2_CST 6 #define MAP_ISR_S2_CST 6
#define MAP_ISR_S2_GTT 6 #define MAP_ISR_S2_GTT 6
#define MAP_ISR_S2_TIM 3 #define MAP_ISR_S2_TIM 3
......
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...@@ -20,6 +20,7 @@ ...@@ -20,6 +20,7 @@
#include <linux/etherdevice.h> #include <linux/etherdevice.h>
#include <linux/device.h> #include <linux/device.h>
#include <linux/leds.h> #include <linux/leds.h>
#include <linux/completion.h>
#include "debug.h" #include "debug.h"
#include "common.h" #include "common.h"
...@@ -194,6 +195,7 @@ enum ATH_AGGR_STATUS { ...@@ -194,6 +195,7 @@ enum ATH_AGGR_STATUS {
#define ATH_TXFIFO_DEPTH 8 #define ATH_TXFIFO_DEPTH 8
struct ath_txq { struct ath_txq {
int axq_class;
u32 axq_qnum; u32 axq_qnum;
u32 *axq_link; u32 *axq_link;
struct list_head axq_q; struct list_head axq_q;
...@@ -206,7 +208,6 @@ struct ath_txq { ...@@ -206,7 +208,6 @@ struct ath_txq {
struct list_head txq_fifo_pending; struct list_head txq_fifo_pending;
u8 txq_headidx; u8 txq_headidx;
u8 txq_tailidx; u8 txq_tailidx;
int pending_frames;
}; };
struct ath_atx_ac { struct ath_atx_ac {
...@@ -224,6 +225,7 @@ struct ath_buf_state { ...@@ -224,6 +225,7 @@ struct ath_buf_state {
int bfs_tidno; int bfs_tidno;
int bfs_retries; int bfs_retries;
u8 bf_type; u8 bf_type;
u8 bfs_paprd;
u32 bfs_keyix; u32 bfs_keyix;
enum ath9k_key_type bfs_keytype; enum ath9k_key_type bfs_keytype;
}; };
...@@ -244,7 +246,6 @@ struct ath_buf { ...@@ -244,7 +246,6 @@ struct ath_buf {
struct ath_buf_state bf_state; struct ath_buf_state bf_state;
dma_addr_t bf_dmacontext; dma_addr_t bf_dmacontext;
struct ath_wiphy *aphy; struct ath_wiphy *aphy;
struct ath_txq *txq;
}; };
struct ath_atx_tid { struct ath_atx_tid {
...@@ -281,6 +282,7 @@ struct ath_tx_control { ...@@ -281,6 +282,7 @@ struct ath_tx_control {
struct ath_txq *txq; struct ath_txq *txq;
int if_id; int if_id;
enum ath9k_internal_frame_type frame_type; enum ath9k_internal_frame_type frame_type;
u8 paprd;
}; };
#define ATH_TX_ERROR 0x01 #define ATH_TX_ERROR 0x01
...@@ -290,11 +292,12 @@ struct ath_tx_control { ...@@ -290,11 +292,12 @@ struct ath_tx_control {
struct ath_tx { struct ath_tx {
u16 seq_no; u16 seq_no;
u32 txqsetup; u32 txqsetup;
int hwq_map[ATH9K_WME_AC_VO+1]; int hwq_map[WME_NUM_AC];
spinlock_t txbuflock; spinlock_t txbuflock;
struct list_head txbuf; struct list_head txbuf;
struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
struct ath_descdma txdma; struct ath_descdma txdma;
int pending_frames[WME_NUM_AC];
}; };
struct ath_rx_edma { struct ath_rx_edma {
...@@ -417,10 +420,12 @@ int ath_beaconq_config(struct ath_softc *sc); ...@@ -417,10 +420,12 @@ int ath_beaconq_config(struct ath_softc *sc);
#define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
#define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
#define ATH_ANI_POLLINTERVAL 100 /* 100 ms */ #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
#define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
void ath_paprd_calibrate(struct work_struct *work);
void ath_ani_calibrate(unsigned long data); void ath_ani_calibrate(unsigned long data);
/**********/ /**********/
...@@ -552,6 +557,9 @@ struct ath_softc { ...@@ -552,6 +557,9 @@ struct ath_softc {
spinlock_t sc_serial_rw; spinlock_t sc_serial_rw;
spinlock_t sc_pm_lock; spinlock_t sc_pm_lock;
struct mutex mutex; struct mutex mutex;
struct work_struct paprd_work;
struct completion paprd_complete;
int paprd_txok;
u32 intrstatus; u32 intrstatus;
u32 sc_flags; /* SC_OP_* */ u32 sc_flags; /* SC_OP_* */
...@@ -610,7 +618,6 @@ struct ath_wiphy { ...@@ -610,7 +618,6 @@ struct ath_wiphy {
void ath9k_tasklet(unsigned long data); void ath9k_tasklet(unsigned long data);
int ath_reset(struct ath_softc *sc, bool retry_tx); int ath_reset(struct ath_softc *sc, bool retry_tx);
int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
int ath_cabq_update(struct ath_softc *); int ath_cabq_update(struct ath_softc *);
...@@ -626,8 +633,6 @@ irqreturn_t ath_isr(int irq, void *dev); ...@@ -626,8 +633,6 @@ irqreturn_t ath_isr(int irq, void *dev);
int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
const struct ath_bus_ops *bus_ops); const struct ath_bus_ops *bus_ops);
void ath9k_deinit_device(struct ath_softc *sc); void ath9k_deinit_device(struct ath_softc *sc);
const char *ath_mac_bb_name(u32 mac_bb_version);
const char *ath_rf_name(u16 rf_version);
void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
struct ath9k_channel *ichan); struct ath9k_channel *ichan);
...@@ -678,8 +683,6 @@ void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle); ...@@ -678,8 +683,6 @@ void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle);
void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue); void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue);
void ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue); void ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue);
int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
void ath_start_rfkill_poll(struct ath_softc *sc); void ath_start_rfkill_poll(struct ath_softc *sc);
extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
......
...@@ -38,8 +38,7 @@ int ath_beaconq_config(struct ath_softc *sc) ...@@ -38,8 +38,7 @@ int ath_beaconq_config(struct ath_softc *sc)
qi.tqi_cwmax = 0; qi.tqi_cwmax = 0;
} else { } else {
/* Adhoc mode; important thing is to use 2x cwmin. */ /* Adhoc mode; important thing is to use 2x cwmin. */
qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, qnum = sc->tx.hwq_map[WME_AC_BE];
ATH9K_WME_AC_BE);
ath9k_hw_get_txq_props(ah, qnum, &qi_be); ath9k_hw_get_txq_props(ah, qnum, &qi_be);
qi.tqi_aifs = qi_be.tqi_aifs; qi.tqi_aifs = qi_be.tqi_aifs;
qi.tqi_cwmin = 4*qi_be.tqi_cwmin; qi.tqi_cwmin = 4*qi_be.tqi_cwmin;
......
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...@@ -263,7 +263,8 @@ enum eeprom_param { ...@@ -263,7 +263,8 @@ enum eeprom_param {
EEP_PWR_TABLE_OFFSET, EEP_PWR_TABLE_OFFSET,
EEP_DRIVE_STRENGTH, EEP_DRIVE_STRENGTH,
EEP_INTERNAL_REGULATOR, EEP_INTERNAL_REGULATOR,
EEP_SWREG EEP_SWREG,
EEP_PAPRD,
}; };
enum ar5416_rates { enum ar5416_rates {
......
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