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Commit bda8f04d authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'imx-dt64-4.14' of... 

Merge tag 'imx-dt64-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64

Pull "Freescale arm64 device tree updates for 4.14" from Shawn Guo:
 - Correct the typo in fsl-ls1088a-rdb board name.
 - A series from Horia Geantă to consolidate aliases node and enable
   crypto support for ls208xa and ls1088a.
 - Enable USB host support for ls1012a.
 - Enable cpuidle support for ls1088a and ls208xa.

* tag 'imx-dt64-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: ls1088: Correction in Board name from "L1088A" to "LS1088A"
  arm64: dts: ls208xa: add cpu idle support
  arm64: dts: ls1088a: add cpu idle support
  arm64: dts: freescale: ls1088a: add crypto node
  arm64: dts: freescale: ls208xa: add crypto node
  arm64: dts: freescale: ls208xa: share aliases node
  arm64: dts: ls1012a: add USB host controller nodes
parents 3004a512 f83de4f0
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Showing with 168 additions and 26 deletions
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View file @ bda8f04d
...@@ -444,6 +444,15 @@ edma0: edma@2c00000 { ...@@ -444,6 +444,15 @@ edma0: edma@2c00000 {
<&clockgen 4 3>; <&clockgen 4 3>;
}; };
usb0: usb3@2f00000 {
compatible = "snps,dwc3";
reg = <0x0 0x2f00000 0x0 0x10000>;
interrupts = <0 60 0x4>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
sata: sata@3200000 { sata: sata@3200000 {
compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci"; compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>, reg = <0x0 0x3200000 0x0 0x10000>,
...@@ -454,5 +463,13 @@ sata: sata@3200000 { ...@@ -454,5 +463,13 @@ sata: sata@3200000 {
dma-coherent; dma-coherent;
status = "disabled"; status = "disabled";
}; };
usb1: usb2@8600000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x8600000 0x0 0x1000>;
interrupts = <0 139 0x4>;
dr_mode = "host";
phy_type = "ulpi";
};
}; };
}; };
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
View file @ bda8f04d
...@@ -49,7 +49,7 @@ ...@@ -49,7 +49,7 @@
#include "fsl-ls1088a.dtsi" #include "fsl-ls1088a.dtsi"
/ { / {
model = "L1088A RDB Board"; model = "LS1088A RDB Board";
compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
}; };
......
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View file @ bda8f04d
...@@ -52,6 +52,10 @@ / { ...@@ -52,6 +52,10 @@ / {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
aliases {
crypto = &crypto;
};
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -62,6 +66,7 @@ cpu0: cpu@0 { ...@@ -62,6 +66,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53"; compatible = "arm,cortex-a53";
reg = <0x0>; reg = <0x0>;
clocks = <&clockgen 1 0>; clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -70,6 +75,7 @@ cpu1: cpu@1 { ...@@ -70,6 +75,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53"; compatible = "arm,cortex-a53";
reg = <0x1>; reg = <0x1>;
clocks = <&clockgen 1 0>; clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PH20>;
}; };
cpu2: cpu@2 { cpu2: cpu@2 {
...@@ -77,6 +83,7 @@ cpu2: cpu@2 { ...@@ -77,6 +83,7 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53"; compatible = "arm,cortex-a53";
reg = <0x2>; reg = <0x2>;
clocks = <&clockgen 1 0>; clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PH20>;
}; };
cpu3: cpu@3 { cpu3: cpu@3 {
...@@ -84,6 +91,7 @@ cpu3: cpu@3 { ...@@ -84,6 +91,7 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53"; compatible = "arm,cortex-a53";
reg = <0x3>; reg = <0x3>;
clocks = <&clockgen 1 0>; clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PH20>;
}; };
cpu4: cpu@100 { cpu4: cpu@100 {
...@@ -91,6 +99,7 @@ cpu4: cpu@100 { ...@@ -91,6 +99,7 @@ cpu4: cpu@100 {
compatible = "arm,cortex-a53"; compatible = "arm,cortex-a53";
reg = <0x100>; reg = <0x100>;
clocks = <&clockgen 1 1>; clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PH20>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -99,6 +108,7 @@ cpu5: cpu@101 { ...@@ -99,6 +108,7 @@ cpu5: cpu@101 {
compatible = "arm,cortex-a53"; compatible = "arm,cortex-a53";
reg = <0x101>; reg = <0x101>;
clocks = <&clockgen 1 1>; clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PH20>;
}; };
cpu6: cpu@102 { cpu6: cpu@102 {
...@@ -106,6 +116,7 @@ cpu6: cpu@102 { ...@@ -106,6 +116,7 @@ cpu6: cpu@102 {
compatible = "arm,cortex-a53"; compatible = "arm,cortex-a53";
reg = <0x102>; reg = <0x102>;
clocks = <&clockgen 1 1>; clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PH20>;
}; };
cpu7: cpu@103 { cpu7: cpu@103 {
...@@ -113,6 +124,16 @@ cpu7: cpu@103 { ...@@ -113,6 +124,16 @@ cpu7: cpu@103 {
compatible = "arm,cortex-a53"; compatible = "arm,cortex-a53";
reg = <0x103>; reg = <0x103>;
clocks = <&clockgen 1 1>; clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PH20>;
};
CPU_PH20: cpu-ph20 {
compatible = "arm,idle-state";
idle-state-name = "PH20";
arm,psci-suspend-param = <0x00010000>;
entry-latency-us = <1000>;
exit-latency-us = <1000>;
min-residency-us = <3000>;
}; };
}; };
...@@ -136,6 +157,11 @@ timer { ...@@ -136,6 +157,11 @@ timer {
<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
}; };
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
sysclk: sysclk { sysclk: sysclk {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
...@@ -369,6 +395,45 @@ sata: sata@3200000 { ...@@ -369,6 +395,45 @@ sata: sata@3200000 {
dma-coherent; dma-coherent;
status = "disabled"; status = "disabled";
}; };
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <8>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x8000000 0x100000>;
reg = <0x00 0x8000000 0x0 0x100000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
};
};
}; };
}; };
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
View file @ bda8f04d
...@@ -55,11 +55,6 @@ / { ...@@ -55,11 +55,6 @@ / {
model = "Freescale Layerscape 2080a QDS Board"; model = "Freescale Layerscape 2080a QDS Board";
compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
aliases {
serial0 = &serial0;
serial1 = &serial1;
};
chosen { chosen {
stdout-path = "serial0:115200n8"; stdout-path = "serial0:115200n8";
}; };
......
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
View file @ bda8f04d
...@@ -55,11 +55,6 @@ / { ...@@ -55,11 +55,6 @@ / {
model = "Freescale Layerscape 2080a RDB Board"; model = "Freescale Layerscape 2080a RDB Board";
compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
aliases {
serial0 = &serial0;
serial1 = &serial1;
};
chosen { chosen {
stdout-path = "serial1:115200n8"; stdout-path = "serial1:115200n8";
}; };
......
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
View file @ bda8f04d
...@@ -52,11 +52,6 @@ / { ...@@ -52,11 +52,6 @@ / {
model = "Freescale Layerscape 2080a software Simulator model"; model = "Freescale Layerscape 2080a software Simulator model";
compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
aliases {
serial0 = &serial0;
serial1 = &serial1;
};
ethernet@2210000 { ethernet@2210000 {
compatible = "smsc,lan91c111"; compatible = "smsc,lan91c111";
reg = <0x0 0x2210000 0x0 0x100>; reg = <0x0 0x2210000 0x0 0x100>;
......
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View file @ bda8f04d
...@@ -53,6 +53,7 @@ cpu0: cpu@0 { ...@@ -53,6 +53,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x0>; reg = <0x0>;
clocks = <&clockgen 1 0>; clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>; next-level-cache = <&cluster0_l2>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -62,6 +63,7 @@ cpu1: cpu@1 { ...@@ -62,6 +63,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x1>; reg = <0x1>;
clocks = <&clockgen 1 0>; clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>; next-level-cache = <&cluster0_l2>;
}; };
...@@ -70,6 +72,7 @@ cpu2: cpu@100 { ...@@ -70,6 +72,7 @@ cpu2: cpu@100 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x100>; reg = <0x100>;
clocks = <&clockgen 1 1>; clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>; next-level-cache = <&cluster1_l2>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -79,6 +82,7 @@ cpu3: cpu@101 { ...@@ -79,6 +82,7 @@ cpu3: cpu@101 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x101>; reg = <0x101>;
clocks = <&clockgen 1 1>; clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>; next-level-cache = <&cluster1_l2>;
}; };
...@@ -87,6 +91,7 @@ cpu4: cpu@200 { ...@@ -87,6 +91,7 @@ cpu4: cpu@200 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x200>; reg = <0x200>;
clocks = <&clockgen 1 2>; clocks = <&clockgen 1 2>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster2_l2>; next-level-cache = <&cluster2_l2>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -96,6 +101,7 @@ cpu5: cpu@201 { ...@@ -96,6 +101,7 @@ cpu5: cpu@201 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x201>; reg = <0x201>;
clocks = <&clockgen 1 2>; clocks = <&clockgen 1 2>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster2_l2>; next-level-cache = <&cluster2_l2>;
}; };
...@@ -105,6 +111,7 @@ cpu6: cpu@300 { ...@@ -105,6 +111,7 @@ cpu6: cpu@300 {
reg = <0x300>; reg = <0x300>;
clocks = <&clockgen 1 3>; clocks = <&clockgen 1 3>;
next-level-cache = <&cluster3_l2>; next-level-cache = <&cluster3_l2>;
cpu-idle-states = <&CPU_PW20>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -113,6 +120,7 @@ cpu7: cpu@301 { ...@@ -113,6 +120,7 @@ cpu7: cpu@301 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x301>; reg = <0x301>;
clocks = <&clockgen 1 3>; clocks = <&clockgen 1 3>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster3_l2>; next-level-cache = <&cluster3_l2>;
}; };
...@@ -131,6 +139,15 @@ cluster2_l2: l2-cache2 { ...@@ -131,6 +139,15 @@ cluster2_l2: l2-cache2 {
cluster3_l2: l2-cache3 { cluster3_l2: l2-cache3 {
compatible = "cache"; compatible = "cache";
}; };
CPU_PW20: cpu-pw20 {
compatible = "arm,idle-state";
idle-state-name = "PW20";
arm,psci-suspend-param = <0x00010000>;
entry-latency-us = <2000>;
exit-latency-us = <2000>;
min-residency-us = <6000>;
};
}; };
&pcie1 { &pcie1 {
......
arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
View file @ bda8f04d
...@@ -54,11 +54,6 @@ / { ...@@ -54,11 +54,6 @@ / {
model = "Freescale Layerscape 2088A QDS Board"; model = "Freescale Layerscape 2088A QDS Board";
compatible = "fsl,ls2088a-qds", "fsl,ls2088a"; compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
aliases {
serial0 = &serial0;
serial1 = &serial1;
};
chosen { chosen {
stdout-path = "serial0:115200n8"; stdout-path = "serial0:115200n8";
}; };
......
arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
View file @ bda8f04d
...@@ -54,11 +54,6 @@ / { ...@@ -54,11 +54,6 @@ / {
model = "Freescale Layerscape 2088A RDB Board"; model = "Freescale Layerscape 2088A RDB Board";
compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
aliases {
serial0 = &serial0;
serial1 = &serial1;
};
chosen { chosen {
stdout-path = "serial1:115200n8"; stdout-path = "serial1:115200n8";
}; };
......
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
View file @ bda8f04d
...@@ -53,6 +53,7 @@ cpu0: cpu@0 { ...@@ -53,6 +53,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a72"; compatible = "arm,cortex-a72";
reg = <0x0>; reg = <0x0>;
clocks = <&clockgen 1 0>; clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>; next-level-cache = <&cluster0_l2>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -62,6 +63,7 @@ cpu1: cpu@1 { ...@@ -62,6 +63,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a72"; compatible = "arm,cortex-a72";
reg = <0x1>; reg = <0x1>;
clocks = <&clockgen 1 0>; clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>; next-level-cache = <&cluster0_l2>;
}; };
...@@ -70,6 +72,7 @@ cpu2: cpu@100 { ...@@ -70,6 +72,7 @@ cpu2: cpu@100 {
compatible = "arm,cortex-a72"; compatible = "arm,cortex-a72";
reg = <0x100>; reg = <0x100>;
clocks = <&clockgen 1 1>; clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>; next-level-cache = <&cluster1_l2>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -79,6 +82,7 @@ cpu3: cpu@101 { ...@@ -79,6 +82,7 @@ cpu3: cpu@101 {
compatible = "arm,cortex-a72"; compatible = "arm,cortex-a72";
reg = <0x101>; reg = <0x101>;
clocks = <&clockgen 1 1>; clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>; next-level-cache = <&cluster1_l2>;
}; };
...@@ -88,6 +92,7 @@ cpu4: cpu@200 { ...@@ -88,6 +92,7 @@ cpu4: cpu@200 {
reg = <0x200>; reg = <0x200>;
clocks = <&clockgen 1 2>; clocks = <&clockgen 1 2>;
next-level-cache = <&cluster2_l2>; next-level-cache = <&cluster2_l2>;
cpu-idle-states = <&CPU_PW20>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -96,6 +101,7 @@ cpu5: cpu@201 { ...@@ -96,6 +101,7 @@ cpu5: cpu@201 {
compatible = "arm,cortex-a72"; compatible = "arm,cortex-a72";
reg = <0x201>; reg = <0x201>;
clocks = <&clockgen 1 2>; clocks = <&clockgen 1 2>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster2_l2>; next-level-cache = <&cluster2_l2>;
}; };
...@@ -104,6 +110,7 @@ cpu6: cpu@300 { ...@@ -104,6 +110,7 @@ cpu6: cpu@300 {
compatible = "arm,cortex-a72"; compatible = "arm,cortex-a72";
reg = <0x300>; reg = <0x300>;
clocks = <&clockgen 1 3>; clocks = <&clockgen 1 3>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster3_l2>; next-level-cache = <&cluster3_l2>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -113,6 +120,7 @@ cpu7: cpu@301 { ...@@ -113,6 +120,7 @@ cpu7: cpu@301 {
compatible = "arm,cortex-a72"; compatible = "arm,cortex-a72";
reg = <0x301>; reg = <0x301>;
clocks = <&clockgen 1 3>; clocks = <&clockgen 1 3>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster3_l2>; next-level-cache = <&cluster3_l2>;
}; };
...@@ -131,6 +139,15 @@ cluster2_l2: l2-cache2 { ...@@ -131,6 +139,15 @@ cluster2_l2: l2-cache2 {
cluster3_l2: l2-cache3 { cluster3_l2: l2-cache3 {
compatible = "cache"; compatible = "cache";
}; };
CPU_PW20: cpu-pw20 {
compatible = "arm,idle-state";
idle-state-name = "PW20";
arm,psci-suspend-param = <0x00010000>;
entry-latency-us = <2000>;
exit-latency-us = <2000>;
min-residency-us = <6000>;
};
}; };
&pcie1 { &pcie1 {
......
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View file @ bda8f04d
...@@ -46,6 +46,7 @@ ...@@ -46,6 +46,7 @@
*/ */
#include <dt-bindings/thermal/thermal.h> #include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ { / {
compatible = "fsl,ls2080a"; compatible = "fsl,ls2080a";
...@@ -53,6 +54,12 @@ / { ...@@ -53,6 +54,12 @@ / {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
aliases {
crypto = &crypto;
serial0 = &serial0;
serial1 = &serial1;
};
cpu: cpus { cpu: cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -118,6 +125,11 @@ pmu { ...@@ -118,6 +125,11 @@ pmu {
interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
}; };
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
soc { soc {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <2>; #address-cells = <2>;
...@@ -301,6 +313,45 @@ cluster4_core1_watchdog: wdt@c310000 { ...@@ -301,6 +313,45 @@ cluster4_core1_watchdog: wdt@c310000 {
clock-names = "apb_pclk", "wdog_clk"; clock-names = "apb_pclk", "wdog_clk";
}; };
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <8>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x8000000 0x100000>;
reg = <0x00 0x8000000 0x0 0x100000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
};
};
fsl_mc: fsl-mc@80c000000 { fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc"; compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
......
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