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Commit bede7d2d authored by Bjorn Andersson's avatar Bjorn Andersson Committed by Andy Gross
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arm64: dts: qcom: sdm845: Increase address and size cells for soc 

The busses on SDM845 provides 36 address bits, extend the address and
size cells to make it possible to describe this in "ranges" and
"dma-ranges".

While touching all reg properties, addresses are padded to 8 digits.
Tested-by: default avatarDouglas Anderson <dianders@chromium.org>
Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent 5b6f186f
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Showing with 150 additions and 150 deletions
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file @ bede7d2d
......@@ -352,14 +352,14 @@ psci {
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0 0xffffffff>;
compatible = "simple-bus";
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sdm845";
reg = <0x100000 0x1f0000>;
reg = <0 0x00100000 0 0x1f0000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
......@@ -367,7 +367,7 @@ gcc: clock-controller@100000 {
qfprom@784000 {
compatible = "qcom,qfprom";
reg = <0x784000 0x8ff>;
reg = <0 0x00784000 0 0x8ff>;
#address-cells = <1>;
#size-cells = <1>;
......@@ -384,25 +384,25 @@ qusb2s_hstx_trim: hstx-trim-secondary@1eb {
rng: rng@793000 {
compatible = "qcom,prng-ee";
reg = <0x00793000 0x1000>;
reg = <0 0x00793000 0 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x8c0000 0x6000>;
reg = <0 0x008c0000 0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
i2c0: i2c@880000 {
compatible = "qcom,geni-i2c";
reg = <0x880000 0x4000>;
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
......@@ -415,7 +415,7 @@ i2c0: i2c@880000 {
spi0: spi@880000 {
compatible = "qcom,geni-spi";
reg = <0x880000 0x4000>;
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
......@@ -428,7 +428,7 @@ spi0: spi@880000 {
uart0: serial@880000 {
compatible = "qcom,geni-uart";
reg = <0x880000 0x4000>;
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
......@@ -439,7 +439,7 @@ uart0: serial@880000 {
i2c1: i2c@884000 {
compatible = "qcom,geni-i2c";
reg = <0x884000 0x4000>;
reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
......@@ -452,7 +452,7 @@ i2c1: i2c@884000 {
spi1: spi@884000 {
compatible = "qcom,geni-spi";
reg = <0x884000 0x4000>;
reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
......@@ -465,7 +465,7 @@ spi1: spi@884000 {
uart1: serial@884000 {
compatible = "qcom,geni-uart";
reg = <0x884000 0x4000>;
reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
......@@ -476,7 +476,7 @@ uart1: serial@884000 {
i2c2: i2c@888000 {
compatible = "qcom,geni-i2c";
reg = <0x888000 0x4000>;
reg = <0 0x00888000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
......@@ -489,7 +489,7 @@ i2c2: i2c@888000 {
spi2: spi@888000 {
compatible = "qcom,geni-spi";
reg = <0x888000 0x4000>;
reg = <0 0x00888000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
......@@ -502,7 +502,7 @@ spi2: spi@888000 {
uart2: serial@888000 {
compatible = "qcom,geni-uart";
reg = <0x888000 0x4000>;
reg = <0 0x00888000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
......@@ -513,7 +513,7 @@ uart2: serial@888000 {
i2c3: i2c@88c000 {
compatible = "qcom,geni-i2c";
reg = <0x88c000 0x4000>;
reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
......@@ -526,7 +526,7 @@ i2c3: i2c@88c000 {
spi3: spi@88c000 {
compatible = "qcom,geni-spi";
reg = <0x88c000 0x4000>;
reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
......@@ -539,7 +539,7 @@ spi3: spi@88c000 {
uart3: serial@88c000 {
compatible = "qcom,geni-uart";
reg = <0x88c000 0x4000>;
reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
......@@ -550,7 +550,7 @@ uart3: serial@88c000 {
i2c4: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0x890000 0x4000>;
reg = <0 0x00890000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
......@@ -563,7 +563,7 @@ i2c4: i2c@890000 {
spi4: spi@890000 {
compatible = "qcom,geni-spi";
reg = <0x890000 0x4000>;
reg = <0 0x00890000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
......@@ -576,7 +576,7 @@ spi4: spi@890000 {
uart4: serial@890000 {
compatible = "qcom,geni-uart";
reg = <0x890000 0x4000>;
reg = <0 0x00890000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
......@@ -587,7 +587,7 @@ uart4: serial@890000 {
i2c5: i2c@894000 {
compatible = "qcom,geni-i2c";
reg = <0x894000 0x4000>;
reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
......@@ -600,7 +600,7 @@ i2c5: i2c@894000 {
spi5: spi@894000 {
compatible = "qcom,geni-spi";
reg = <0x894000 0x4000>;
reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
......@@ -613,7 +613,7 @@ spi5: spi@894000 {
uart5: serial@894000 {
compatible = "qcom,geni-uart";
reg = <0x894000 0x4000>;
reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
......@@ -624,7 +624,7 @@ uart5: serial@894000 {
i2c6: i2c@898000 {
compatible = "qcom,geni-i2c";
reg = <0x898000 0x4000>;
reg = <0 0x00898000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
pinctrl-names = "default";
......@@ -637,7 +637,7 @@ i2c6: i2c@898000 {
spi6: spi@898000 {
compatible = "qcom,geni-spi";
reg = <0x898000 0x4000>;
reg = <0 0x00898000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
pinctrl-names = "default";
......@@ -650,7 +650,7 @@ spi6: spi@898000 {
uart6: serial@898000 {
compatible = "qcom,geni-uart";
reg = <0x898000 0x4000>;
reg = <0 0x00898000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
pinctrl-names = "default";
......@@ -661,7 +661,7 @@ uart6: serial@898000 {
i2c7: i2c@89c000 {
compatible = "qcom,geni-i2c";
reg = <0x89c000 0x4000>;
reg = <0 0x0089c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
pinctrl-names = "default";
......@@ -674,7 +674,7 @@ i2c7: i2c@89c000 {
spi7: spi@89c000 {
compatible = "qcom,geni-spi";
reg = <0x89c000 0x4000>;
reg = <0 0x0089c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
pinctrl-names = "default";
......@@ -687,7 +687,7 @@ spi7: spi@89c000 {
uart7: serial@89c000 {
compatible = "qcom,geni-uart";
reg = <0x89c000 0x4000>;
reg = <0 0x0089c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
pinctrl-names = "default";
......@@ -699,18 +699,18 @@ uart7: serial@89c000 {
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0xac0000 0x6000>;
reg = <0 0x00ac0000 0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
i2c8: i2c@a80000 {
compatible = "qcom,geni-i2c";
reg = <0xa80000 0x4000>;
reg = <0 0x00a80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
......@@ -723,7 +723,7 @@ i2c8: i2c@a80000 {
spi8: spi@a80000 {
compatible = "qcom,geni-spi";
reg = <0xa80000 0x4000>;
reg = <0 0x00a80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
......@@ -736,7 +736,7 @@ spi8: spi@a80000 {
uart8: serial@a80000 {
compatible = "qcom,geni-uart";
reg = <0xa80000 0x4000>;
reg = <0 0x00a80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
......@@ -747,7 +747,7 @@ uart8: serial@a80000 {
i2c9: i2c@a84000 {
compatible = "qcom,geni-i2c";
reg = <0xa84000 0x4000>;
reg = <0 0x00a84000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
......@@ -760,7 +760,7 @@ i2c9: i2c@a84000 {
spi9: spi@a84000 {
compatible = "qcom,geni-spi";
reg = <0xa84000 0x4000>;
reg = <0 0x00a84000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
......@@ -773,7 +773,7 @@ spi9: spi@a84000 {
uart9: serial@a84000 {
compatible = "qcom,geni-debug-uart";
reg = <0xa84000 0x4000>;
reg = <0 0x00a84000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
......@@ -784,7 +784,7 @@ uart9: serial@a84000 {
i2c10: i2c@a88000 {
compatible = "qcom,geni-i2c";
reg = <0xa88000 0x4000>;
reg = <0 0x00a88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
......@@ -797,7 +797,7 @@ i2c10: i2c@a88000 {
spi10: spi@a88000 {
compatible = "qcom,geni-spi";
reg = <0xa88000 0x4000>;
reg = <0 0x00a88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
......@@ -810,7 +810,7 @@ spi10: spi@a88000 {
uart10: serial@a88000 {
compatible = "qcom,geni-uart";
reg = <0xa88000 0x4000>;
reg = <0 0x00a88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
......@@ -821,7 +821,7 @@ uart10: serial@a88000 {
i2c11: i2c@a8c000 {
compatible = "qcom,geni-i2c";
reg = <0xa8c000 0x4000>;
reg = <0 0x00a8c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
......@@ -834,7 +834,7 @@ i2c11: i2c@a8c000 {
spi11: spi@a8c000 {
compatible = "qcom,geni-spi";
reg = <0xa8c000 0x4000>;
reg = <0 0x00a8c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
......@@ -847,7 +847,7 @@ spi11: spi@a8c000 {
uart11: serial@a8c000 {
compatible = "qcom,geni-uart";
reg = <0xa8c000 0x4000>;
reg = <0 0x00a8c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
......@@ -858,7 +858,7 @@ uart11: serial@a8c000 {
i2c12: i2c@a90000 {
compatible = "qcom,geni-i2c";
reg = <0xa90000 0x4000>;
reg = <0 0x00a90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
......@@ -871,7 +871,7 @@ i2c12: i2c@a90000 {
spi12: spi@a90000 {
compatible = "qcom,geni-spi";
reg = <0xa90000 0x4000>;
reg = <0 0x00a90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
......@@ -884,7 +884,7 @@ spi12: spi@a90000 {
uart12: serial@a90000 {
compatible = "qcom,geni-uart";
reg = <0xa90000 0x4000>;
reg = <0 0x00a90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
......@@ -895,7 +895,7 @@ uart12: serial@a90000 {
i2c13: i2c@a94000 {
compatible = "qcom,geni-i2c";
reg = <0xa94000 0x4000>;
reg = <0 0x00a94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
......@@ -908,7 +908,7 @@ i2c13: i2c@a94000 {
spi13: spi@a94000 {
compatible = "qcom,geni-spi";
reg = <0xa94000 0x4000>;
reg = <0 0x00a94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
......@@ -921,7 +921,7 @@ spi13: spi@a94000 {
uart13: serial@a94000 {
compatible = "qcom,geni-uart";
reg = <0xa94000 0x4000>;
reg = <0 0x00a94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
......@@ -932,7 +932,7 @@ uart13: serial@a94000 {
i2c14: i2c@a98000 {
compatible = "qcom,geni-i2c";
reg = <0xa98000 0x4000>;
reg = <0 0x00a98000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
pinctrl-names = "default";
......@@ -945,7 +945,7 @@ i2c14: i2c@a98000 {
spi14: spi@a98000 {
compatible = "qcom,geni-spi";
reg = <0xa98000 0x4000>;
reg = <0 0x00a98000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
pinctrl-names = "default";
......@@ -958,7 +958,7 @@ spi14: spi@a98000 {
uart14: serial@a98000 {
compatible = "qcom,geni-uart";
reg = <0xa98000 0x4000>;
reg = <0 0x00a98000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
pinctrl-names = "default";
......@@ -969,7 +969,7 @@ uart14: serial@a98000 {
i2c15: i2c@a9c000 {
compatible = "qcom,geni-i2c";
reg = <0xa9c000 0x4000>;
reg = <0 0x00a9c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
pinctrl-names = "default";
......@@ -982,7 +982,7 @@ i2c15: i2c@a9c000 {
spi15: spi@a9c000 {
compatible = "qcom,geni-spi";
reg = <0xa9c000 0x4000>;
reg = <0 0x00a9c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
pinctrl-names = "default";
......@@ -995,7 +995,7 @@ spi15: spi@a9c000 {
uart15: serial@a9c000 {
compatible = "qcom,geni-uart";
reg = <0xa9c000 0x4000>;
reg = <0 0x00a9c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
pinctrl-names = "default";
......@@ -1008,7 +1008,7 @@ uart15: serial@a9c000 {
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0x1d84000 0x2500>;
reg = <0 0x01d84000 0 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
......@@ -1050,9 +1050,9 @@ ufs_mem_hc: ufshc@1d84000 {
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sdm845-qmp-ufs-phy";
reg = <0x1d87000 0x18c>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0x01d87000 0 0x18c>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clock-names = "ref",
"ref_aux";
......@@ -1062,23 +1062,23 @@ ufs_mem_phy: phy@1d87000 {
status = "disabled";
ufs_mem_phy_lanes: lanes@1d87400 {
reg = <0x1d87400 0x108>,
<0x1d87600 0x1e0>,
<0x1d87c00 0x1dc>,
<0x1d87800 0x108>,
<0x1d87a00 0x1e0>;
reg = <0 0x01d87400 0 0x108>,
<0 0x01d87600 0 0x1e0>,
<0 0x01d87c00 0 0x1dc>,
<0 0x01d87800 0 0x108>,
<0 0x01d87a00 0 0x1e0>;
#phy-cells = <0>;
};
};
tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon";
reg = <0x1f40000 0x40000>;
reg = <0 0x01f40000 0 0x40000>;
};
tlmm: pinctrl@3400000 {
compatible = "qcom,sdm845-pinctrl";
reg = <0x03400000 0xc00000>;
reg = <0 0x03400000 0 0xc00000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
......@@ -1475,7 +1475,7 @@ pinmux {
gpucc: clock-controller@5090000 {
compatible = "qcom,sdm845-gpucc";
reg = <0x05090000 0x9000>;
reg = <0 0x05090000 0 0x9000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
......@@ -1485,7 +1485,7 @@ gpucc: clock-controller@5090000 {
sdhc_2: sdhci@8804000 {
compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
reg = <0x8804000 0x1000>;
reg = <0 0x08804000 0 0x1000>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1500,7 +1500,7 @@ sdhc_2: sdhci@8804000 {
qspi: spi@88df000 {
compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
reg = <0x88df000 0x600>;
reg = <0 0x088df000 0 0x600>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1512,7 +1512,7 @@ qspi: spi@88df000 {
usb_1_hsphy: phy@88e2000 {
compatible = "qcom,sdm845-qusb2-phy";
reg = <0x88e2000 0x400>;
reg = <0 0x088e2000 0 0x400>;
status = "disabled";
#phy-cells = <0>;
......@@ -1527,7 +1527,7 @@ usb_1_hsphy: phy@88e2000 {
usb_2_hsphy: phy@88e3000 {
compatible = "qcom,sdm845-qusb2-phy";
reg = <0x88e3000 0x400>;
reg = <0 0x088e3000 0 0x400>;
status = "disabled";
#phy-cells = <0>;
......@@ -1542,13 +1542,13 @@ usb_2_hsphy: phy@88e3000 {
usb_1_qmpphy: phy@88e9000 {
compatible = "qcom,sdm845-qmp-usb3-phy";
reg = <0x88e9000 0x18c>,
<0x88e8000 0x10>;
reg = <0 0x088e9000 0 0x18c>,
<0 0x088e8000 0 0x10>;
reg-names = "reg-base", "dp_com";
status = "disabled";
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
......@@ -1562,12 +1562,12 @@ usb_1_qmpphy: phy@88e9000 {
reset-names = "phy", "common";
usb_1_ssphy: lanes@88e9200 {
reg = <0x88e9200 0x128>,
<0x88e9400 0x200>,
<0x88e9c00 0x218>,
<0x88e9600 0x128>,
<0x88e9800 0x200>,
<0x88e9a00 0x100>;
reg = <0 0x088e9200 0 0x128>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x218>,
<0 0x088e9600 0 0x128>,
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x100>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
......@@ -1577,11 +1577,11 @@ usb_1_ssphy: lanes@88e9200 {
usb_2_qmpphy: phy@88eb000 {
compatible = "qcom,sdm845-qmp-usb3-uni-phy";
reg = <0x88eb000 0x18c>;
reg = <0 0x088eb000 0 0x18c>;
status = "disabled";
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
......@@ -1595,10 +1595,10 @@ usb_2_qmpphy: phy@88eb000 {
reset-names = "phy", "common";
usb_2_ssphy: lane@88eb200 {
reg = <0x88eb200 0x128>,
<0x88eb400 0x1fc>,
<0x88eb800 0x218>,
<0x88eb600 0x70>;
reg = <0 0x088eb200 0 0x128>,
<0 0x088eb400 0 0x1fc>,
<0 0x088eb800 0 0x218>,
<0 0x088eb600 0 0x70>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "pipe0";
......@@ -1608,10 +1608,10 @@ usb_2_ssphy: lane@88eb200 {
usb_1: usb@a6f8800 {
compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
reg = <0xa6f8800 0x400>;
reg = <0 0x0a6f8800 0 0x400>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
......@@ -1639,7 +1639,7 @@ usb_1: usb@a6f8800 {
usb_1_dwc3: dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0xa600000 0xcd00>;
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
......@@ -1650,10 +1650,10 @@ usb_1_dwc3: dwc3@a600000 {
usb_2: usb@a8f8800 {
compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
reg = <0xa8f8800 0x400>;
reg = <0 0x0a8f8800 0 0x400>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
......@@ -1681,7 +1681,7 @@ usb_2: usb@a8f8800 {
usb_2_dwc3: dwc3@a800000 {
compatible = "snps,dwc3";
reg = <0xa800000 0xcd00>;
reg = <0 0x0a800000 0 0xcd00>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
......@@ -1692,7 +1692,7 @@ usb_2_dwc3: dwc3@a800000 {
videocc: clock-controller@ab00000 {
compatible = "qcom,sdm845-videocc";
reg = <0x0ab00000 0x10000>;
reg = <0 0x0ab00000 0 0x10000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
......@@ -1700,7 +1700,7 @@ videocc: clock-controller@ab00000 {
mdss: mdss@ae00000 {
compatible = "qcom,sdm845-mdss";
reg = <0x0ae00000 0x1000>;
reg = <0 0x0ae00000 0 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc MDSS_GDSC>;
......@@ -1722,14 +1722,14 @@ mdss: mdss@ae00000 {
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
mdss_mdp: mdp@ae01000 {
compatible = "qcom,sdm845-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb0000 0 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
......@@ -1770,7 +1770,7 @@ dpu_intf2_out: endpoint {
dsi0: dsi@ae94000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0xae94000 0x400>;
reg = <0 0x0ae94000 0 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
......@@ -1818,9 +1818,9 @@ dsi0_out: endpoint {
dsi0_phy: dsi-phy@ae94400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0xae94400 0x200>,
<0xae94600 0x280>,
<0xae94a00 0x1e0>;
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
<0 0x0ae94a00 0 0x1e0>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
......@@ -1836,7 +1836,7 @@ dsi0_phy: dsi-phy@ae94400 {
dsi1: dsi@ae96000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0xae96000 0x400>;
reg = <0 0x0ae96000 0 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
......@@ -1884,9 +1884,9 @@ dsi1_out: endpoint {
dsi1_phy: dsi-phy@ae96400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0xae96400 0x200>,
<0xae96600 0x280>,
<0xae96a00 0x10e>;
reg = <0 0x0ae96400 0 0x200>,
<0 0x0ae96600 0 0x280>,
<0 0x0ae96a00 0 0x10e>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
......@@ -1903,7 +1903,7 @@ dsi1_phy: dsi-phy@ae96400 {
dispcc: clock-controller@af00000 {
compatible = "qcom,sdm845-dispcc";
reg = <0xaf00000 0x10000>;
reg = <0 0x0af00000 0 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
......@@ -1911,39 +1911,39 @@ dispcc: clock-controller@af00000 {
pdc_reset: reset-controller@b2e0000 {
compatible = "qcom,sdm845-pdc-global";
reg = <0x0b2e0000 0x20000>;
reg = <0 0x0b2e0000 0 0x20000>;
#reset-cells = <1>;
};
tsens0: thermal-sensor@c263000 {
compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
reg = <0xc263000 0x1ff>, /* TM */
<0xc222000 0x1ff>; /* SROT */
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x1ff>; /* SROT */
#qcom,sensors = <13>;
#thermal-sensor-cells = <1>;
};
tsens1: thermal-sensor@c265000 {
compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
reg = <0xc265000 0x1ff>, /* TM */
<0xc223000 0x1ff>; /* SROT */
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x1ff>; /* SROT */
#qcom,sensors = <8>;
#thermal-sensor-cells = <1>;
};
aoss_reset: reset-controller@c2a0000 {
compatible = "qcom,sdm845-aoss-cc";
reg = <0xc2a0000 0x31000>;
reg = <0 0x0c2a0000 0 0x31000>;
#reset-cells = <1>;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0x1100>,
<0xc600000 0x2000000>,
<0xe600000 0x100000>,
<0xe700000 0xa0000>,
<0xc40a000 0x26000>;
reg = <0 0x0c440000 0 0x1100>,
<0 0x0c600000 0 0x2000000>,
<0 0x0e600000 0 0x100000>,
<0 0x0e700000 0 0xa0000>,
<0 0x0c40a000 0 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1958,7 +1958,7 @@ spmi_bus: spmi@c440000 {
apps_smmu: iommu@15000000 {
compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
reg = <0x15000000 0x80000>;
reg = <0 0x15000000 0 0x80000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
......@@ -2038,16 +2038,16 @@ lpasscc: clock-controller@17014000 {
apss_shared: mailbox@17990000 {
compatible = "qcom,sdm845-apss-shared";
reg = <0x17990000 0x1000>;
reg = <0 0x17990000 0 0x1000>;
#mbox-cells = <1>;
};
apps_rsc: rsc@179c0000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x179c0000 0x10000>,
<0x179d0000 0x10000>,
<0x179e0000 0x10000>;
reg = <0 0x179c0000 0 0x10000>,
<0 0x179d0000 0 0x10000>,
<0 0x179e0000 0 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
......@@ -2117,85 +2117,85 @@ rpmhpd_opp_turbo_l1: opp10 {
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x17a00000 0x10000>, /* GICD */
<0x17a60000 0x100000>; /* GICR * 8 */
reg = <0 0x17a00000 0 0x10000>, /* GICD */
<0 0x17a60000 0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic-its@17a40000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x17a40000 0x20000>;
reg = <0 0x17a40000 0 0x20000>;
status = "disabled";
};
};
timer@17c90000 {
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17c90000 0x1000>;
reg = <0 0x17c90000 0 0x1000>;
frame@17ca0000 {
frame-number = <0>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17ca0000 0x1000>,
<0x17cb0000 0x1000>;
reg = <0 0x17ca0000 0 0x1000>,
<0 0x17cb0000 0 0x1000>;
};
frame@17cc0000 {
frame-number = <1>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17cc0000 0x1000>;
reg = <0 0x17cc0000 0 0x1000>;
status = "disabled";
};
frame@17cd0000 {
frame-number = <2>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17cd0000 0x1000>;
reg = <0 0x17cd0000 0 0x1000>;
status = "disabled";
};
frame@17ce0000 {
frame-number = <3>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17ce0000 0x1000>;
reg = <0 0x17ce0000 0 0x1000>;
status = "disabled";
};
frame@17cf0000 {
frame-number = <4>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17cf0000 0x1000>;
reg = <0 0x17cf0000 0 0x1000>;
status = "disabled";
};
frame@17d00000 {
frame-number = <5>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17d00000 0x1000>;
reg = <0 0x17d00000 0 0x1000>;
status = "disabled";
};
frame@17d10000 {
frame-number = <6>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17d10000 0x1000>;
reg = <0 0x17d10000 0 0x1000>;
status = "disabled";
};
};
cpufreq_hw: cpufreq@17d43000 {
compatible = "qcom,cpufreq-hw";
reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
......@@ -2207,7 +2207,7 @@ cpufreq_hw: cpufreq@17d43000 {
wifi: wifi@18800000 {
compatible = "qcom,wcn3990-wifi";
status = "disabled";
reg = <0x18800000 0x800000>;
reg = <0 0x18800000 0 0x800000>;
reg-names = "membase";
memory-region = <&wlan_msa_mem>;
interrupts =
......
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