Commit bfbacdae authored by Michael Strauss's avatar Michael Strauss Committed by Alex Deucher

drm/amd/display: Fix rn audio playback and video playback speed

[WHY]
dprefclk is improperly read due to incorrect units used.
Causes an audio clock to be improperly set, making audio
non-functional and videos play back too fast

[HOW]
Scale dprefclk value from MHz to KHz (multiply by 1000)
to ensure that dprefclk_khz is in correct units
Signed-off-by: default avatarMichael Strauss <michael.strauss@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: default avatarRoman Li <Roman.Li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1952a21c
...@@ -377,7 +377,7 @@ void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s) ...@@ -377,7 +377,7 @@ void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
rn_dump_clk_registers(&sb, clk_mgr_base, &log_info); rn_dump_clk_registers(&sb, clk_mgr_base, &log_info);
s->dprefclk_khz = sb.dprefclk; s->dprefclk_khz = sb.dprefclk * 1000;
} }
void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base) void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
...@@ -633,16 +633,15 @@ void rn_clk_mgr_construct( ...@@ -633,16 +633,15 @@ void rn_clk_mgr_construct(
clk_mgr->dentist_vco_freq_khz = 3600000; clk_mgr->dentist_vco_freq_khz = 3600000;
rn_dump_clk_registers(&s, &clk_mgr->base, &log_info); rn_dump_clk_registers(&s, &clk_mgr->base, &log_info);
clk_mgr->base.dprefclk_khz = s.dprefclk; /* Convert dprefclk units from MHz to KHz */
/* Value already divided by 10, some resolution lost */
if (clk_mgr->base.dprefclk_khz != 600000) { clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;
clk_mgr->base.dprefclk_khz = 600000;
ASSERT(1); //TODO: Renoir follow up.
}
/* in case we don't get a value from the register, use default */ /* in case we don't get a value from the register, use default */
if (clk_mgr->base.dprefclk_khz == 0) if (clk_mgr->base.dprefclk_khz == 0) {
ASSERT(clk_mgr->base.dprefclk_khz == 600000);
clk_mgr->base.dprefclk_khz = 600000; clk_mgr->base.dprefclk_khz = 600000;
}
} }
dce_clock_read_ss_info(clk_mgr); dce_clock_read_ss_info(clk_mgr);
......
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