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Commit c0c3350c authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'mvebu-dt-fixes-3.13' of git://git.infradead.org/linux-mvebu into fixes 

From Jason Cooper, mvebu DT fixes for v3.13:
 - mvebu
    - PCIe fixes now that we have test devices with more ports.
    - fix access to coherency registers

* tag 'mvebu-dt-fixes-3.13' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: re-enable PCIe on Armada 370 DB
  ARM: mvebu: use the virtual CPU registers to access coherency registers
  ARM: mvebu: fix second and third PCIe unit of Armada XP mv78260
  ARM: mvebu: second PCIe unit of Armada XP mv78230 is only x1 capable
parents b8be3a22 96039f73
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Showing with 112 additions and 51 deletions
arch/arm/boot/dts/armada-370-db.dts
View file @ c0c3350c
...@@ -99,22 +99,22 @@ spi-flash@0 { ...@@ -99,22 +99,22 @@ spi-flash@0 {
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
}; };
}; };
};
pcie-controller { pcie-controller {
status = "okay";
/*
* The two PCIe units are accessible through
* both standard PCIe slots and mini-PCIe
* slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay"; status = "okay";
/*
* The two PCIe units are accessible through
* both standard PCIe slots and mini-PCIe
* slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-370-xp.dtsi
View file @ c0c3350c
...@@ -118,7 +118,7 @@ mpic: interrupt-controller@20000 { ...@@ -118,7 +118,7 @@ mpic: interrupt-controller@20000 {
coherency-fabric@20200 { coherency-fabric@20200 {
compatible = "marvell,coherency-fabric"; compatible = "marvell,coherency-fabric";
reg = <0x20200 0xb0>, <0x21810 0x1c>; reg = <0x20200 0xb0>, <0x21010 0x1c>;
}; };
serial@12000 { serial@12000 {
......
arch/arm/boot/dts/armada-xp-mv78230.dtsi
View file @ c0c3350c
...@@ -47,7 +47,7 @@ soc { ...@@ -47,7 +47,7 @@ soc {
/* /*
* MV78230 has 2 PCIe units Gen2.0: One unit can be * MV78230 has 2 PCIe units Gen2.0: One unit can be
* configured as x4 or quad x1 lanes. One unit is * configured as x4 or quad x1 lanes. One unit is
* x4/x1. * x1 only.
*/ */
pcie-controller { pcie-controller {
compatible = "marvell,armada-xp-pcie"; compatible = "marvell,armada-xp-pcie";
...@@ -62,10 +62,10 @@ pcie-controller { ...@@ -62,10 +62,10 @@ pcie-controller {
ranges = ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
...@@ -74,8 +74,8 @@ pcie-controller { ...@@ -74,8 +74,8 @@ pcie-controller {
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
pcie@1,0 { pcie@1,0 {
device_type = "pci"; device_type = "pci";
...@@ -145,20 +145,20 @@ pcie@4,0 { ...@@ -145,20 +145,20 @@ pcie@4,0 {
status = "disabled"; status = "disabled";
}; };
pcie@9,0 { pcie@5,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x4800 0 0 0 0>; reg = <0x2800 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>; 0x81000000 0 0 0x81000000 0x5 0 1 0>;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>; interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <2>; marvell,pcie-port = <1>;
marvell,pcie-lane = <0>; marvell,pcie-lane = <0>;
clocks = <&gateclk 26>; clocks = <&gateclk 9>;
status = "disabled"; status = "disabled";
}; };
}; };
......
arch/arm/boot/dts/armada-xp-mv78260.dtsi
View file @ c0c3350c
...@@ -48,7 +48,7 @@ soc { ...@@ -48,7 +48,7 @@ soc {
/* /*
* MV78260 has 3 PCIe units Gen2.0: Two units can be * MV78260 has 3 PCIe units Gen2.0: Two units can be
* configured as x4 or quad x1 lanes. One unit is * configured as x4 or quad x1 lanes. One unit is
* x4/x1. * x4 only.
*/ */
pcie-controller { pcie-controller {
compatible = "marvell,armada-xp-pcie"; compatible = "marvell,armada-xp-pcie";
...@@ -68,7 +68,9 @@ pcie-controller { ...@@ -68,7 +68,9 @@ pcie-controller {
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
...@@ -77,10 +79,18 @@ pcie-controller { ...@@ -77,10 +79,18 @@ pcie-controller {
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
pcie@1,0 { pcie@1,0 {
device_type = "pci"; device_type = "pci";
...@@ -106,8 +116,8 @@ pcie@2,0 { ...@@ -106,8 +116,8 @@ pcie@2,0 {
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>; 0x81000000 0 0 0x81000000 0x2 0 1 0>;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>; interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>; marvell,pcie-port = <0>;
...@@ -150,37 +160,88 @@ pcie@4,0 { ...@@ -150,37 +160,88 @@ pcie@4,0 {
status = "disabled"; status = "disabled";
}; };
pcie@9,0 { pcie@5,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x4800 0 0 0 0>; reg = <0x2800 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>; 0x81000000 0 0 0x81000000 0x5 0 1 0>;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>; interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <2>; marvell,pcie-port = <1>;
marvell,pcie-lane = <0>; marvell,pcie-lane = <0>;
clocks = <&gateclk 26>; clocks = <&gateclk 9>;
status = "disabled"; status = "disabled";
}; };
pcie@10,0 { pcie@6,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x82000 0 0x2000>; assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
reg = <0x5000 0 0 0 0>; reg = <0x3000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0xa 0 1 0>; 0x81000000 0 0 0x81000000 0x6 0 1 0>;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>; interrupt-map = <0 0 0 0 &mpic 63>;
marvell,pcie-port = <3>; marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 10>;
status = "disabled";
};
pcie@7,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
reg = <0x3800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 64>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 11>;
status = "disabled";
};
pcie@8,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
reg = <0x4000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 65>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 12>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>; marvell,pcie-lane = <0>;
clocks = <&gateclk 27>; clocks = <&gateclk 26>;
status = "disabled"; status = "disabled";
}; };
}; };
......
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