Commit c0d64cf9 authored by Paul Mackerras's avatar Paul Mackerras Committed by Michael Ellerman

powerpc: Use feature bit for RTC presence rather than timebase presence

All PowerPC CPUs other than the original PPC601 have a timebase
register rather than the "real-time clock" (RTC) register that the
PPC601 (and the original POWER and POWER2 CPUs) had.  Currently
we have a CPU feature bit to indicate the presence of the timebase,
but it makes more sense to use a bit to indicate the unusual
situation rather than the common situation.  This therefore defines
a CPU_FTR_USE_RTC bit in place of the CPU_FTR_USE_TB bit, and
arranges for it to be set on PPC601 systems.
Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 7928b2cb
This diff is collapsed.
...@@ -46,7 +46,7 @@ struct div_result { ...@@ -46,7 +46,7 @@ struct div_result {
/* Accessor functions for the timebase (RTC on 601) registers. */ /* Accessor functions for the timebase (RTC on 601) registers. */
/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */ /* If one day CONFIG_POWER is added just define __USE_RTC as 1 */
#ifdef CONFIG_6xx #ifdef CONFIG_6xx
#define __USE_RTC() (!cpu_has_feature(CPU_FTR_USE_TB)) #define __USE_RTC() (cpu_has_feature(CPU_FTR_USE_RTC))
#else #else
#define __USE_RTC() 0 #define __USE_RTC() 0
#endif #endif
......
...@@ -54,8 +54,7 @@ struct dt_cpu_feature { ...@@ -54,8 +54,7 @@ struct dt_cpu_feature {
}; };
#define CPU_FTRS_BASE \ #define CPU_FTRS_BASE \
(CPU_FTR_USE_TB | \ (CPU_FTR_LWSYNC | \
CPU_FTR_LWSYNC | \
CPU_FTR_FPU_UNAVAILABLE |\ CPU_FTR_FPU_UNAVAILABLE |\
CPU_FTR_NODSISRALIGN |\ CPU_FTR_NODSISRALIGN |\
CPU_FTR_NOEXECUTE |\ CPU_FTR_NOEXECUTE |\
......
...@@ -99,26 +99,28 @@ static struct vdso_patch_def vdso_patches[] = { ...@@ -99,26 +99,28 @@ static struct vdso_patch_def vdso_patches[] = {
CPU_FTR_COHERENT_ICACHE, CPU_FTR_COHERENT_ICACHE, CPU_FTR_COHERENT_ICACHE, CPU_FTR_COHERENT_ICACHE,
"__kernel_sync_dicache", "__kernel_sync_dicache_p5" "__kernel_sync_dicache", "__kernel_sync_dicache_p5"
}, },
#ifdef CONFIG_PPC32
{ {
CPU_FTR_USE_TB, 0, CPU_FTR_USE_RTC, CPU_FTR_USE_RTC,
"__kernel_gettimeofday", NULL "__kernel_gettimeofday", NULL
}, },
{ {
CPU_FTR_USE_TB, 0, CPU_FTR_USE_RTC, CPU_FTR_USE_RTC,
"__kernel_clock_gettime", NULL "__kernel_clock_gettime", NULL
}, },
{ {
CPU_FTR_USE_TB, 0, CPU_FTR_USE_RTC, CPU_FTR_USE_RTC,
"__kernel_clock_getres", NULL "__kernel_clock_getres", NULL
}, },
{ {
CPU_FTR_USE_TB, 0, CPU_FTR_USE_RTC, CPU_FTR_USE_RTC,
"__kernel_get_tbfreq", NULL "__kernel_get_tbfreq", NULL
}, },
{ {
CPU_FTR_USE_TB, 0, CPU_FTR_USE_RTC, CPU_FTR_USE_RTC,
"__kernel_time", NULL "__kernel_time", NULL
}, },
#endif
}; };
/* /*
......
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