Commit c3b1feb0 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS fixes from Ralf Baechle:
 "This is the first round of MIPS fixes for 4.6:

   - Fix spelling mistakes all over arch/mips
   - Provide __bswapsi2 so XZ kernel compression will build with older GCC
   - ATH79 clock fixes.
   - Fix clock-rated copy-paste erros in ATH79 DTS.
   - Fix gisb-arb compatible string for 7435 BMIPS
   - Enable NAND and UBIFS support in CI20.
   - Fix BUG() assertion caused by inapropriate smp_processor_id() use.
   - Fix exception handling issues for the sake of debuggers
   - Fix the last remaining instance of irq_to_gpio in the db1xxx_ss PCMCIA code
   - Fix MSA unaligned load failures
   - Panic if kernel is configured for a not TLB-supported page size
   - Bail out on unsupported relocs in modules.
   - Partial fix for Qemu breakage after recent IPI rewrite
   - Wire up the preadv2 and pwrite2 syscalls
   - Fix the ar724x clock calculation"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: traps.c: Verify the ISA for microMIPS RDHWR emulation
  MIPS: BMIPS: Fix gisb-arb compatible string for 7435
  MIPS: Bail on unsupported module relocs
  MIPS: dts: qca: ar9132_tl_wr1043nd_v1.dts: use "ref" for reference clock name
  MIPS: ath79: Fix the ar913x reference clock rate
  MIPS: ath79: Fix the ar724x clock calculation
  dt-bindings: clock: qca,ath79-pll: fix copy-paste typos
  MIPS: traps: Correct the SIGTRAP debug ABI in `do_watch' and `do_trap_or_bp'
  FIRMWARE: Broadcom: Fix grammar of warning messages in bcm47xx_sprom.c.
  MIPS: ci20: Enable NAND and UBIFS support in defconfig.
  MIPS: Fix misspellings in comments.
  MIPS: tlb-r4k: panic if the MMU doesn't support PAGE_SIZE
  MIPS: zboot: Remove copied source files on clean
  MIPS: zboot: Fix the build with XZ compression on older GCC versions
  MIPS: Wire up preadv2 and pwrite2 syscalls.
  MIPS: cpu_name_string: Use raw_smp_processor_id().
  pcmcia: db1xxx_ss: fix last irq_to_gpio user
  MIPS: Fix MSA ld unaligned failure cases
  MIPS: Fix broken malta qemu
parents 93e2aeac 3d50a7fb
...@@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller ...@@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
Required Properties: Required Properties:
- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following - compatible: has to be "qca,<soctype>-pll" and one of the following
fallbacks: fallbacks:
- "qca,ar7100-pll" - "qca,ar7100-pll"
- "qca,ar7240-pll" - "qca,ar7240-pll"
...@@ -21,8 +21,8 @@ Optional properties: ...@@ -21,8 +21,8 @@ Optional properties:
Example: Example:
memory-controller@18050000 { pll-controller@18050000 {
compatible = "qca,ar9132-ppl", "qca,ar9130-pll"; compatible = "qca,ar9132-pll", "qca,ar9130-pll";
reg = <0x18050000 0x20>; reg = <0x18050000 0x20>;
clock-names = "ref"; clock-names = "ref";
......
...@@ -261,7 +261,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, ...@@ -261,7 +261,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
au1x_dma_chan_t *cp; au1x_dma_chan_t *cp;
/* /*
* We do the intialization on the first channel allocation. * We do the initialization on the first channel allocation.
* We have to wait because of the interrupt handler initialization * We have to wait because of the interrupt handler initialization
* which can't be done successfully during board set up. * which can't be done successfully during board set up.
*/ */
...@@ -964,7 +964,7 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) ...@@ -964,7 +964,7 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
dp->dscr_source1 = dscr->dscr_source1; dp->dscr_source1 = dscr->dscr_source1;
dp->dscr_cmd1 = dscr->dscr_cmd1; dp->dscr_cmd1 = dscr->dscr_cmd1;
nbytes = dscr->dscr_cmd1; nbytes = dscr->dscr_cmd1;
/* Allow the caller to specifiy if an interrupt is generated */ /* Allow the caller to specify if an interrupt is generated */
dp->dscr_cmd0 &= ~DSCR_CMD0_IE; dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V; dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
ctp->chan_ptr->ddma_dbell = 0; ctp->chan_ptr->ddma_dbell = 0;
......
...@@ -503,15 +503,15 @@ int __init db1000_dev_setup(void) ...@@ -503,15 +503,15 @@ int __init db1000_dev_setup(void)
if (board == BCSR_WHOAMI_DB1500) { if (board == BCSR_WHOAMI_DB1500) {
c0 = AU1500_GPIO2_INT; c0 = AU1500_GPIO2_INT;
c1 = AU1500_GPIO5_INT; c1 = AU1500_GPIO5_INT;
d0 = AU1500_GPIO0_INT; d0 = 0; /* GPIO number, NOT irq! */
d1 = AU1500_GPIO3_INT; d1 = 3; /* GPIO number, NOT irq! */
s0 = AU1500_GPIO1_INT; s0 = AU1500_GPIO1_INT;
s1 = AU1500_GPIO4_INT; s1 = AU1500_GPIO4_INT;
} else if (board == BCSR_WHOAMI_DB1100) { } else if (board == BCSR_WHOAMI_DB1100) {
c0 = AU1100_GPIO2_INT; c0 = AU1100_GPIO2_INT;
c1 = AU1100_GPIO5_INT; c1 = AU1100_GPIO5_INT;
d0 = AU1100_GPIO0_INT; d0 = 0; /* GPIO number, NOT irq! */
d1 = AU1100_GPIO3_INT; d1 = 3; /* GPIO number, NOT irq! */
s0 = AU1100_GPIO1_INT; s0 = AU1100_GPIO1_INT;
s1 = AU1100_GPIO4_INT; s1 = AU1100_GPIO4_INT;
...@@ -545,15 +545,15 @@ int __init db1000_dev_setup(void) ...@@ -545,15 +545,15 @@ int __init db1000_dev_setup(void)
} else if (board == BCSR_WHOAMI_DB1000) { } else if (board == BCSR_WHOAMI_DB1000) {
c0 = AU1000_GPIO2_INT; c0 = AU1000_GPIO2_INT;
c1 = AU1000_GPIO5_INT; c1 = AU1000_GPIO5_INT;
d0 = AU1000_GPIO0_INT; d0 = 0; /* GPIO number, NOT irq! */
d1 = AU1000_GPIO3_INT; d1 = 3; /* GPIO number, NOT irq! */
s0 = AU1000_GPIO1_INT; s0 = AU1000_GPIO1_INT;
s1 = AU1000_GPIO4_INT; s1 = AU1000_GPIO4_INT;
platform_add_devices(db1000_devs, ARRAY_SIZE(db1000_devs)); platform_add_devices(db1000_devs, ARRAY_SIZE(db1000_devs));
} else if ((board == BCSR_WHOAMI_PB1500) || } else if ((board == BCSR_WHOAMI_PB1500) ||
(board == BCSR_WHOAMI_PB1500R2)) { (board == BCSR_WHOAMI_PB1500R2)) {
c0 = AU1500_GPIO203_INT; c0 = AU1500_GPIO203_INT;
d0 = AU1500_GPIO201_INT; d0 = 1; /* GPIO number, NOT irq! */
s0 = AU1500_GPIO202_INT; s0 = AU1500_GPIO202_INT;
twosocks = 0; twosocks = 0;
flashsize = 64; flashsize = 64;
...@@ -566,7 +566,7 @@ int __init db1000_dev_setup(void) ...@@ -566,7 +566,7 @@ int __init db1000_dev_setup(void)
*/ */
} else if (board == BCSR_WHOAMI_PB1100) { } else if (board == BCSR_WHOAMI_PB1100) {
c0 = AU1100_GPIO11_INT; c0 = AU1100_GPIO11_INT;
d0 = AU1100_GPIO9_INT; d0 = 9; /* GPIO number, NOT irq! */
s0 = AU1100_GPIO10_INT; s0 = AU1100_GPIO10_INT;
twosocks = 0; twosocks = 0;
flashsize = 64; flashsize = 64;
...@@ -583,7 +583,6 @@ int __init db1000_dev_setup(void) ...@@ -583,7 +583,6 @@ int __init db1000_dev_setup(void)
} else } else
return 0; /* unknown board, no further dev setup to do */ return 0; /* unknown board, no further dev setup to do */
irq_set_irq_type(d0, IRQ_TYPE_EDGE_BOTH);
irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW);
...@@ -597,7 +596,6 @@ int __init db1000_dev_setup(void) ...@@ -597,7 +596,6 @@ int __init db1000_dev_setup(void)
c0, d0, /*s0*/0, 0, 0); c0, d0, /*s0*/0, 0, 0);
if (twosocks) { if (twosocks) {
irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH);
irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW);
......
...@@ -514,7 +514,7 @@ static void __init db1550_devices(void) ...@@ -514,7 +514,7 @@ static void __init db1550_devices(void)
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
AU1000_PCMCIA_IO_PHYS_ADDR, AU1000_PCMCIA_IO_PHYS_ADDR,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
AU1550_GPIO3_INT, AU1550_GPIO0_INT, AU1550_GPIO3_INT, 0,
/*AU1550_GPIO21_INT*/0, 0, 0); /*AU1550_GPIO21_INT*/0, 0, 0);
db1x_register_pcmcia_socket( db1x_register_pcmcia_socket(
...@@ -524,7 +524,7 @@ static void __init db1550_devices(void) ...@@ -524,7 +524,7 @@ static void __init db1550_devices(void)
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
AU1550_GPIO5_INT, AU1550_GPIO1_INT, AU1550_GPIO5_INT, 1,
/*AU1550_GPIO22_INT*/0, 0, 1); /*AU1550_GPIO22_INT*/0, 0, 1);
platform_device_register(&db1550_nand_dev); platform_device_register(&db1550_nand_dev);
......
...@@ -26,8 +26,7 @@ ...@@ -26,8 +26,7 @@
#include "common.h" #include "common.h"
#define AR71XX_BASE_FREQ 40000000 #define AR71XX_BASE_FREQ 40000000
#define AR724X_BASE_FREQ 5000000 #define AR724X_BASE_FREQ 40000000
#define AR913X_BASE_FREQ 5000000
static struct clk *clks[3]; static struct clk *clks[3];
static struct clk_onecell_data clk_data = { static struct clk_onecell_data clk_data = {
...@@ -103,8 +102,8 @@ static void __init ar724x_clocks_init(void) ...@@ -103,8 +102,8 @@ static void __init ar724x_clocks_init(void)
div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK); div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
freq = div * ref_rate; freq = div * ref_rate;
div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
freq *= div; freq /= div;
cpu_rate = freq; cpu_rate = freq;
...@@ -123,39 +122,6 @@ static void __init ar724x_clocks_init(void) ...@@ -123,39 +122,6 @@ static void __init ar724x_clocks_init(void)
clk_add_alias("uart", NULL, "ahb", NULL); clk_add_alias("uart", NULL, "ahb", NULL);
} }
static void __init ar913x_clocks_init(void)
{
unsigned long ref_rate;
unsigned long cpu_rate;
unsigned long ddr_rate;
unsigned long ahb_rate;
u32 pll;
u32 freq;
u32 div;
ref_rate = AR913X_BASE_FREQ;
pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
div = ((pll >> AR913X_PLL_FB_SHIFT) & AR913X_PLL_FB_MASK);
freq = div * ref_rate;
cpu_rate = freq;
div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;
ddr_rate = freq / div;
div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
ahb_rate = cpu_rate / div;
ath79_add_sys_clkdev("ref", ref_rate);
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
clk_add_alias("wdt", NULL, "ahb", NULL);
clk_add_alias("uart", NULL, "ahb", NULL);
}
static void __init ar933x_clocks_init(void) static void __init ar933x_clocks_init(void)
{ {
unsigned long ref_rate; unsigned long ref_rate;
...@@ -443,10 +409,8 @@ void __init ath79_clocks_init(void) ...@@ -443,10 +409,8 @@ void __init ath79_clocks_init(void)
{ {
if (soc_is_ar71xx()) if (soc_is_ar71xx())
ar71xx_clocks_init(); ar71xx_clocks_init();
else if (soc_is_ar724x()) else if (soc_is_ar724x() || soc_is_ar913x())
ar724x_clocks_init(); ar724x_clocks_init();
else if (soc_is_ar913x())
ar913x_clocks_init();
else if (soc_is_ar933x()) else if (soc_is_ar933x())
ar933x_clocks_init(); ar933x_clocks_init();
else if (soc_is_ar934x()) else if (soc_is_ar934x())
......
...@@ -714,11 +714,11 @@ void bcm47xx_sprom_register_fallbacks(void) ...@@ -714,11 +714,11 @@ void bcm47xx_sprom_register_fallbacks(void)
{ {
#if defined(CONFIG_BCM47XX_SSB) #if defined(CONFIG_BCM47XX_SSB)
if (ssb_arch_register_fallback_sprom(&bcm47xx_get_sprom_ssb)) if (ssb_arch_register_fallback_sprom(&bcm47xx_get_sprom_ssb))
pr_warn("Failed to registered ssb SPROM handler\n"); pr_warn("Failed to register ssb SPROM handler\n");
#endif #endif
#if defined(CONFIG_BCM47XX_BCMA) #if defined(CONFIG_BCM47XX_BCMA)
if (bcma_arch_register_fallback_sprom(&bcm47xx_get_sprom_bcma)) if (bcma_arch_register_fallback_sprom(&bcm47xx_get_sprom_bcma))
pr_warn("Failed to registered bcma SPROM handler\n"); pr_warn("Failed to register bcma SPROM handler\n");
#endif #endif
} }
...@@ -39,10 +39,11 @@ vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM) += $(obj)/uart-prom.o ...@@ -39,10 +39,11 @@ vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM) += $(obj)/uart-prom.o
vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o
endif endif
vmlinuzobjs-$(CONFIG_KERNEL_XZ) += $(obj)/ashldi3.o vmlinuzobjs-$(CONFIG_KERNEL_XZ) += $(obj)/ashldi3.o $(obj)/bswapsi.o
$(obj)/ashldi3.o: KBUILD_CFLAGS += -I$(srctree)/arch/mips/lib extra-y += ashldi3.c bswapsi.c
$(obj)/ashldi3.c: $(srctree)/arch/mips/lib/ashldi3.c $(obj)/ashldi3.o $(obj)/bswapsi.o: KBUILD_CFLAGS += -I$(srctree)/arch/mips/lib
$(obj)/ashldi3.c $(obj)/bswapsi.c: $(obj)/%.c: $(srctree)/arch/mips/lib/%.c
$(call cmd,shipped) $(call cmd,shipped)
targets := $(notdir $(vmlinuzobjs-y)) targets := $(notdir $(vmlinuzobjs-y))
......
...@@ -82,7 +82,7 @@ sun_l2_intc: sun_l2_intc@403000 { ...@@ -82,7 +82,7 @@ sun_l2_intc: sun_l2_intc@403000 {
}; };
gisb-arb@400000 { gisb-arb@400000 {
compatible = "brcm,bcm7400-gisb-arb"; compatible = "brcm,bcm7435-gisb-arb";
reg = <0x400000 0xdc>; reg = <0x400000 0xdc>;
native-endian; native-endian;
interrupt-parent = <&sun_l2_intc>; interrupt-parent = <&sun_l2_intc>;
......
...@@ -83,7 +83,7 @@ gpio: gpio@18040000 { ...@@ -83,7 +83,7 @@ gpio: gpio@18040000 {
}; };
pll: pll-controller@18050000 { pll: pll-controller@18050000 {
compatible = "qca,ar9132-ppl", compatible = "qca,ar9132-pll",
"qca,ar9130-pll"; "qca,ar9130-pll";
reg = <0x18050000 0x20>; reg = <0x18050000 0x20>;
......
...@@ -18,7 +18,7 @@ memory@0 { ...@@ -18,7 +18,7 @@ memory@0 {
reg = <0x0 0x2000000>; reg = <0x0 0x2000000>;
}; };
extosc: oscillator { extosc: ref {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <40000000>; clock-frequency = <40000000>;
......
...@@ -68,7 +68,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) ...@@ -68,7 +68,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
gmx_rx_int_en.s.pause_drp = 1; gmx_rx_int_en.s.pause_drp = 1;
/* Skipping gmx_rx_int_en.s.reserved_16_18 */ /* Skipping gmx_rx_int_en.s.reserved_16_18 */
/*gmx_rx_int_en.s.ifgerr = 1; */ /*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
...@@ -89,7 +89,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) ...@@ -89,7 +89,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
/*gmx_rx_int_en.s.phy_spd = 1; */ /*gmx_rx_int_en.s.phy_spd = 1; */
/*gmx_rx_int_en.s.phy_link = 1; */ /*gmx_rx_int_en.s.phy_link = 1; */
/*gmx_rx_int_en.s.ifgerr = 1; */ /*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
...@@ -112,7 +112,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) ...@@ -112,7 +112,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
/*gmx_rx_int_en.s.phy_spd = 1; */ /*gmx_rx_int_en.s.phy_spd = 1; */
/*gmx_rx_int_en.s.phy_link = 1; */ /*gmx_rx_int_en.s.phy_link = 1; */
/*gmx_rx_int_en.s.ifgerr = 1; */ /*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
...@@ -134,7 +134,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) ...@@ -134,7 +134,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
/*gmx_rx_int_en.s.phy_spd = 1; */ /*gmx_rx_int_en.s.phy_spd = 1; */
/*gmx_rx_int_en.s.phy_link = 1; */ /*gmx_rx_int_en.s.phy_link = 1; */
/*gmx_rx_int_en.s.ifgerr = 1; */ /*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
...@@ -156,7 +156,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) ...@@ -156,7 +156,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
/*gmx_rx_int_en.s.phy_spd = 1; */ /*gmx_rx_int_en.s.phy_spd = 1; */
/*gmx_rx_int_en.s.phy_link = 1; */ /*gmx_rx_int_en.s.phy_link = 1; */
/*gmx_rx_int_en.s.ifgerr = 1; */ /*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
...@@ -179,7 +179,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) ...@@ -179,7 +179,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
/*gmx_rx_int_en.s.phy_spd = 1; */ /*gmx_rx_int_en.s.phy_spd = 1; */
/*gmx_rx_int_en.s.phy_link = 1; */ /*gmx_rx_int_en.s.phy_link = 1; */
/*gmx_rx_int_en.s.ifgerr = 1; */ /*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
...@@ -209,7 +209,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) ...@@ -209,7 +209,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
gmx_rx_int_en.s.pause_drp = 1; gmx_rx_int_en.s.pause_drp = 1;
/* Skipping gmx_rx_int_en.s.reserved_16_18 */ /* Skipping gmx_rx_int_en.s.reserved_16_18 */
/*gmx_rx_int_en.s.ifgerr = 1; */ /*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
......
...@@ -189,7 +189,7 @@ void cvmx_pko_initialize_global(void) ...@@ -189,7 +189,7 @@ void cvmx_pko_initialize_global(void)
/* /*
* Set the size of the PKO command buffers to an odd number of * Set the size of the PKO command buffers to an odd number of
* 64bit words. This allows the normal two word send to stay * 64bit words. This allows the normal two word send to stay
* aligned and never span a comamnd word buffer. * aligned and never span a command word buffer.
*/ */
config.u64 = 0; config.u64 = 0;
config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL; config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
......
...@@ -331,7 +331,7 @@ static int octeon_update_boot_vector(unsigned int cpu) ...@@ -331,7 +331,7 @@ static int octeon_update_boot_vector(unsigned int cpu)
} }
if (!(avail_coremask & (1 << coreid))) { if (!(avail_coremask & (1 << coreid))) {
/* core not available, assume, that catched by simple-executive */ /* core not available, assume, that caught by simple-executive */
cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
cvmx_write_csr(CVMX_CIU_PP_RST, 0); cvmx_write_csr(CVMX_CIU_PP_RST, 0);
} }
......
...@@ -17,13 +17,12 @@ CONFIG_IKCONFIG=y ...@@ -17,13 +17,12 @@ CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14 CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y CONFIG_CGROUPS=y
CONFIG_MEMCG=y
CONFIG_CGROUP_SCHED=y
CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CPUSETS=y CONFIG_CPUSETS=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_CPUACCT=y
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_CGROUP_SCHED=y
CONFIG_NAMESPACES=y CONFIG_NAMESPACES=y
CONFIG_USER_NS=y CONFIG_USER_NS=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y
...@@ -52,6 +51,11 @@ CONFIG_DEVTMPFS=y ...@@ -52,6 +51,11 @@ CONFIG_DEVTMPFS=y
# CONFIG_ALLOW_DEV_COREDUMP is not set # CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_DMA_CMA=y CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32 CONFIG_CMA_SIZE_MBYTES=32
CONFIG_MTD=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_JZ4780=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set # CONFIG_NET_CADENCE is not set
...@@ -103,7 +107,7 @@ CONFIG_PROC_KCORE=y ...@@ -103,7 +107,7 @@ CONFIG_PROC_KCORE=y
# CONFIG_PROC_PAGE_MONITOR is not set # CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y CONFIG_CONFIGFS_FS=y
# CONFIG_MISC_FILESYSTEMS is not set CONFIG_UBIFS_FS=y
# CONFIG_NETWORK_FILESYSTEMS is not set # CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_NLS=y CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_437=y
......
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
* Written by Ralf Baechle and Andreas Busse, modified for DECstation * Written by Ralf Baechle and Andreas Busse, modified for DECstation
* support by Paul Antoine and Harald Koerfgen. * support by Paul Antoine and Harald Koerfgen.
* *
* completly rewritten: * completely rewritten:
* Copyright (C) 1998 Harald Koerfgen * Copyright (C) 1998 Harald Koerfgen
* *
* Rewritten extensively for controller-driven IRQ support * Rewritten extensively for controller-driven IRQ support
......
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
* PROM library functions for acquiring/using memory descriptors given to us * PROM library functions for acquiring/using memory descriptors given to us
* from the ARCS firmware. This is only used when CONFIG_ARC_MEMORY is set * from the ARCS firmware. This is only used when CONFIG_ARC_MEMORY is set
* because on some machines like SGI IP27 the ARC memory configuration data * because on some machines like SGI IP27 the ARC memory configuration data
* completly bogus and alternate easier to use mechanisms are available. * completely bogus and alternate easier to use mechanisms are available.
*/ */
#include <linux/init.h> #include <linux/init.h>
#include <linux/kernel.h> #include <linux/kernel.h>
......
...@@ -102,7 +102,7 @@ extern void cpu_probe(void); ...@@ -102,7 +102,7 @@ extern void cpu_probe(void);
extern void cpu_report(void); extern void cpu_report(void);
extern const char *__cpu_name[]; extern const char *__cpu_name[];
#define cpu_name_string() __cpu_name[smp_processor_id()] #define cpu_name_string() __cpu_name[raw_smp_processor_id()]
struct seq_file; struct seq_file;
struct notifier_block; struct notifier_block;
......
...@@ -141,7 +141,7 @@ ...@@ -141,7 +141,7 @@
.endm .endm
/* /*
* Do SMP slave processor setup necessary before we can savely execute C code. * Do SMP slave processor setup necessary before we can safely execute C code.
*/ */
.macro smp_slave_setup .macro smp_slave_setup
.endm .endm
......
...@@ -16,7 +16,7 @@ ...@@ -16,7 +16,7 @@
.endm .endm
/* /*
* Do SMP slave processor setup necessary before we can savely execute C code. * Do SMP slave processor setup necessary before we can safely execute C code.
*/ */
.macro smp_slave_setup .macro smp_slave_setup
.endm .endm
......
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
#define __ASM_MACH_IP27_IRQ_H #define __ASM_MACH_IP27_IRQ_H
/* /*
* A hardwired interrupt number is completly stupid for this system - a * A hardwired interrupt number is completely stupid for this system - a
* large configuration might have thousands if not tenthousands of * large configuration might have thousands if not tenthousands of
* interrupts. * interrupts.
*/ */
......
...@@ -81,7 +81,7 @@ ...@@ -81,7 +81,7 @@
.endm .endm
/* /*
* Do SMP slave processor setup necessary before we can savely execute C code. * Do SMP slave processor setup necessary before we can safely execute C code.
*/ */
.macro smp_slave_setup .macro smp_slave_setup
GET_NASID_ASM t1 GET_NASID_ASM t1
......
...@@ -27,7 +27,7 @@ enum jz_gpio_function { ...@@ -27,7 +27,7 @@ enum jz_gpio_function {
/* /*
Usually a driver for a SoC component has to request several gpio pins and Usually a driver for a SoC component has to request several gpio pins and
configure them as funcion pins. configure them as function pins.
jz_gpio_bulk_request can be used to ease this process. jz_gpio_bulk_request can be used to ease this process.
Usually one would do something like: Usually one would do something like:
......
...@@ -28,7 +28,7 @@ extern void __iomem *mips_cm_l2sync_base; ...@@ -28,7 +28,7 @@ extern void __iomem *mips_cm_l2sync_base;
* This function returns the physical base address of the Coherence Manager * This function returns the physical base address of the Coherence Manager
* global control block, or 0 if no Coherence Manager is present. It provides * global control block, or 0 if no Coherence Manager is present. It provides
* a default implementation which reads the CMGCRBase register where available, * a default implementation which reads the CMGCRBase register where available,
* and may be overriden by platforms which determine this address in a * and may be overridden by platforms which determine this address in a
* different way by defining a function with the same prototype except for the * different way by defining a function with the same prototype except for the
* name mips_cm_phys_base (without underscores). * name mips_cm_phys_base (without underscores).
*/ */
......
...@@ -79,7 +79,7 @@ struct r2_decoder_table { ...@@ -79,7 +79,7 @@ struct r2_decoder_table {
}; };
extern void do_trap_or_bp(struct pt_regs *regs, unsigned int code, extern void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
const char *str); const char *str);
#ifndef CONFIG_MIPSR2_TO_R6_EMULATOR #ifndef CONFIG_MIPSR2_TO_R6_EMULATOR
......
...@@ -33,7 +33,7 @@ ...@@ -33,7 +33,7 @@
/* Packet buffers */ /* Packet buffers */
#define CVMX_FPA_PACKET_POOL (0) #define CVMX_FPA_PACKET_POOL (0)
#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE #define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE
/* Work queue entrys */ /* Work queue entries */
#define CVMX_FPA_WQE_POOL (1) #define CVMX_FPA_WQE_POOL (1)
#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE #define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE
/* PKO queue command buffers */ /* PKO queue command buffers */
......
...@@ -189,7 +189,7 @@ static inline uint64_t cvmx_ptr_to_phys(void *ptr) ...@@ -189,7 +189,7 @@ static inline uint64_t cvmx_ptr_to_phys(void *ptr)
static inline void *cvmx_phys_to_ptr(uint64_t physical_address) static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
{ {
if (sizeof(void *) == 8) { if (sizeof(void *) == 8) {
/* Just set the top bit, avoiding any TLB uglyness */ /* Just set the top bit, avoiding any TLB ugliness */
return CASTPTR(void, return CASTPTR(void,
CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
physical_address)); physical_address));
......
...@@ -273,7 +273,7 @@ typedef struct bridge_err_cmdword_s { ...@@ -273,7 +273,7 @@ typedef struct bridge_err_cmdword_s {
sidn:4, /* Source ID */ sidn:4, /* Source ID */
pactyp:4, /* Packet type */ pactyp:4, /* Packet type */
tnum:5, /* Trans Number */ tnum:5, /* Trans Number */
coh:1, /* Coh Transacti */ coh:1, /* Coh Transaction */
ds:2, /* Data size */ ds:2, /* Data size */
gbr:1, /* GBR enable */ gbr:1, /* GBR enable */
vbpm:1, /* VBPM message */ vbpm:1, /* VBPM message */
......
...@@ -147,7 +147,7 @@ struct hpc3_ethregs { ...@@ -147,7 +147,7 @@ struct hpc3_ethregs {
#define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */ #define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */
#define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */ #define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */
#define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */ #define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */
#define HPC3_EPCFG_TST 0x1000 /* Diagnistic ram test feature bit */ #define HPC3_EPCFG_TST 0x1000 /* Diagnostic ram test feature bit */
u32 _unused2[0x1000/4 - 8]; /* padding */ u32 _unused2[0x1000/4 - 8]; /* padding */
......
...@@ -144,7 +144,7 @@ struct linux_tinfo { ...@@ -144,7 +144,7 @@ struct linux_tinfo {
struct linux_vdirent { struct linux_vdirent {
ULONG namelen; ULONG namelen;
unsigned char attr; unsigned char attr;
char fname[32]; /* XXX imperical, should be a define */ char fname[32]; /* XXX empirical, should be a define */
}; };
/* Other stuff for files. */ /* Other stuff for files. */
...@@ -179,7 +179,7 @@ struct linux_finfo { ...@@ -179,7 +179,7 @@ struct linux_finfo {
enum linux_devtypes dtype; enum linux_devtypes dtype;
unsigned long namelen; unsigned long namelen;
unsigned char attr; unsigned char attr;
char name[32]; /* XXX imperical, should be define */ char name[32]; /* XXX empirical, should be define */
}; };
/* This describes the vector containing function pointers to the ARC /* This describes the vector containing function pointers to the ARC
......
...@@ -355,7 +355,7 @@ struct ioc3_etxd { ...@@ -355,7 +355,7 @@ struct ioc3_etxd {
#define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */ #define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */
#define SSCR_RESET 0x80000000 /* reset DMA channels */ #define SSCR_RESET 0x80000000 /* reset DMA channels */
/* all producer/comsumer pointers are the same bitfield */ /* all producer/consumer pointers are the same bitfield */
#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */ #define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */
#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */ #define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */
#define PROD_CONS_PTR_OFF 3 #define PROD_CONS_PTR_OFF 3
......
...@@ -628,7 +628,7 @@ typedef union h1_icrbb_u { ...@@ -628,7 +628,7 @@ typedef union h1_icrbb_u {
/* /*
* Values for field imsgtype * Values for field imsgtype
*/ */
#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */ #define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Message from Xtalk */
#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */ #define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */
#define IIO_ICRB_IMSGT_SN0NET 2 /* Incoming message from SN0 net */ #define IIO_ICRB_IMSGT_SN0NET 2 /* Incoming message from SN0 net */
#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */ #define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */
......
...@@ -95,7 +95,7 @@ static inline bool eva_kernel_access(void) ...@@ -95,7 +95,7 @@ static inline bool eva_kernel_access(void)
} }
/* /*
* Is a address valid? This does a straighforward calculation rather * Is a address valid? This does a straightforward calculation rather
* than tests. * than tests.
* *
* Address valid if: * Address valid if:
......
...@@ -381,16 +381,18 @@ ...@@ -381,16 +381,18 @@
#define __NR_membarrier (__NR_Linux + 358) #define __NR_membarrier (__NR_Linux + 358)
#define __NR_mlock2 (__NR_Linux + 359) #define __NR_mlock2 (__NR_Linux + 359)
#define __NR_copy_file_range (__NR_Linux + 360) #define __NR_copy_file_range (__NR_Linux + 360)
#define __NR_preadv2 (__NR_Linux + 361)
#define __NR_pwritev2 (__NR_Linux + 362)
/* /*
* Offset of the last Linux o32 flavoured syscall * Offset of the last Linux o32 flavoured syscall
*/ */
#define __NR_Linux_syscalls 360 #define __NR_Linux_syscalls 362
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#define __NR_O32_Linux 4000 #define __NR_O32_Linux 4000
#define __NR_O32_Linux_syscalls 360 #define __NR_O32_Linux_syscalls 362
#if _MIPS_SIM == _MIPS_SIM_ABI64 #if _MIPS_SIM == _MIPS_SIM_ABI64
...@@ -719,16 +721,18 @@ ...@@ -719,16 +721,18 @@
#define __NR_membarrier (__NR_Linux + 318) #define __NR_membarrier (__NR_Linux + 318)
#define __NR_mlock2 (__NR_Linux + 319) #define __NR_mlock2 (__NR_Linux + 319)
#define __NR_copy_file_range (__NR_Linux + 320) #define __NR_copy_file_range (__NR_Linux + 320)
#define __NR_preadv2 (__NR_Linux + 321)
#define __NR_pwritev2 (__NR_Linux + 322)
/* /*
* Offset of the last Linux 64-bit flavoured syscall * Offset of the last Linux 64-bit flavoured syscall
*/ */
#define __NR_Linux_syscalls 320 #define __NR_Linux_syscalls 322
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
#define __NR_64_Linux 5000 #define __NR_64_Linux 5000
#define __NR_64_Linux_syscalls 320 #define __NR_64_Linux_syscalls 322
#if _MIPS_SIM == _MIPS_SIM_NABI32 #if _MIPS_SIM == _MIPS_SIM_NABI32
...@@ -1061,15 +1065,17 @@ ...@@ -1061,15 +1065,17 @@
#define __NR_membarrier (__NR_Linux + 322) #define __NR_membarrier (__NR_Linux + 322)
#define __NR_mlock2 (__NR_Linux + 323) #define __NR_mlock2 (__NR_Linux + 323)
#define __NR_copy_file_range (__NR_Linux + 324) #define __NR_copy_file_range (__NR_Linux + 324)
#define __NR_preadv2 (__NR_Linux + 325)
#define __NR_pwritev2 (__NR_Linux + 326)
/* /*
* Offset of the last N32 flavoured syscall * Offset of the last N32 flavoured syscall
*/ */
#define __NR_Linux_syscalls 324 #define __NR_Linux_syscalls 326
#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
#define __NR_N32_Linux 6000 #define __NR_N32_Linux 6000
#define __NR_N32_Linux_syscalls 324 #define __NR_N32_Linux_syscalls 326
#endif /* _UAPI_ASM_UNISTD_H */ #endif /* _UAPI_ASM_UNISTD_H */
...@@ -24,7 +24,7 @@ static char *cm2_tr[8] = { ...@@ -24,7 +24,7 @@ static char *cm2_tr[8] = {
"0x04", "cpc", "0x06", "0x07" "0x04", "cpc", "0x06", "0x07"
}; };
/* CM3 Tag ECC transation type */ /* CM3 Tag ECC transaction type */
static char *cm3_tr[16] = { static char *cm3_tr[16] = {
[0x0] = "ReqNoData", [0x0] = "ReqNoData",
[0x1] = "0x1", [0x1] = "0x1",
......
...@@ -940,42 +940,42 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) ...@@ -940,42 +940,42 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
switch (rt) { switch (rt) {
case tgei_op: case tgei_op:
if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst)) if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst))
do_trap_or_bp(regs, 0, "TGEI"); do_trap_or_bp(regs, 0, 0, "TGEI");
MIPS_R2_STATS(traps); MIPS_R2_STATS(traps);
break; break;
case tgeiu_op: case tgeiu_op:
if (regs->regs[rs] >= MIPSInst_UIMM(inst)) if (regs->regs[rs] >= MIPSInst_UIMM(inst))
do_trap_or_bp(regs, 0, "TGEIU"); do_trap_or_bp(regs, 0, 0, "TGEIU");
MIPS_R2_STATS(traps); MIPS_R2_STATS(traps);
break; break;
case tlti_op: case tlti_op:
if ((long)regs->regs[rs] < MIPSInst_SIMM(inst)) if ((long)regs->regs[rs] < MIPSInst_SIMM(inst))
do_trap_or_bp(regs, 0, "TLTI"); do_trap_or_bp(regs, 0, 0, "TLTI");
MIPS_R2_STATS(traps); MIPS_R2_STATS(traps);
break; break;
case tltiu_op: case tltiu_op:
if (regs->regs[rs] < MIPSInst_UIMM(inst)) if (regs->regs[rs] < MIPSInst_UIMM(inst))
do_trap_or_bp(regs, 0, "TLTIU"); do_trap_or_bp(regs, 0, 0, "TLTIU");
MIPS_R2_STATS(traps); MIPS_R2_STATS(traps);
break; break;
case teqi_op: case teqi_op:
if (regs->regs[rs] == MIPSInst_SIMM(inst)) if (regs->regs[rs] == MIPSInst_SIMM(inst))
do_trap_or_bp(regs, 0, "TEQI"); do_trap_or_bp(regs, 0, 0, "TEQI");
MIPS_R2_STATS(traps); MIPS_R2_STATS(traps);
break; break;
case tnei_op: case tnei_op:
if (regs->regs[rs] != MIPSInst_SIMM(inst)) if (regs->regs[rs] != MIPSInst_SIMM(inst))
do_trap_or_bp(regs, 0, "TNEI"); do_trap_or_bp(regs, 0, 0, "TNEI");
MIPS_R2_STATS(traps); MIPS_R2_STATS(traps);
......
...@@ -109,9 +109,10 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, ...@@ -109,9 +109,10 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
struct module *me) struct module *me)
{ {
Elf_Mips_Rela *rel = (void *) sechdrs[relsec].sh_addr; Elf_Mips_Rela *rel = (void *) sechdrs[relsec].sh_addr;
int (*handler)(struct module *me, u32 *location, Elf_Addr v);
Elf_Sym *sym; Elf_Sym *sym;
u32 *location; u32 *location;
unsigned int i; unsigned int i, type;
Elf_Addr v; Elf_Addr v;
int res; int res;
...@@ -134,9 +135,21 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, ...@@ -134,9 +135,21 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
return -ENOENT; return -ENOENT;
} }
v = sym->st_value + rel[i].r_addend; type = ELF_MIPS_R_TYPE(rel[i]);
if (type < ARRAY_SIZE(reloc_handlers_rela))
handler = reloc_handlers_rela[type];
else
handler = NULL;
res = reloc_handlers_rela[ELF_MIPS_R_TYPE(rel[i])](me, location, v); if (!handler) {
pr_err("%s: Unknown relocation type %u\n",
me->name, type);
return -EINVAL;
}
v = sym->st_value + rel[i].r_addend;
res = handler(me, location, v);
if (res) if (res)
return res; return res;
} }
......
...@@ -197,9 +197,10 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab, ...@@ -197,9 +197,10 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
struct module *me) struct module *me)
{ {
Elf_Mips_Rel *rel = (void *) sechdrs[relsec].sh_addr; Elf_Mips_Rel *rel = (void *) sechdrs[relsec].sh_addr;
int (*handler)(struct module *me, u32 *location, Elf_Addr v);
Elf_Sym *sym; Elf_Sym *sym;
u32 *location; u32 *location;
unsigned int i; unsigned int i, type;
Elf_Addr v; Elf_Addr v;
int res; int res;
...@@ -223,9 +224,21 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab, ...@@ -223,9 +224,21 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
return -ENOENT; return -ENOENT;
} }
v = sym->st_value; type = ELF_MIPS_R_TYPE(rel[i]);
if (type < ARRAY_SIZE(reloc_handlers_rel))
handler = reloc_handlers_rel[type];
else
handler = NULL;
res = reloc_handlers_rel[ELF_MIPS_R_TYPE(rel[i])](me, location, v); if (!handler) {
pr_err("%s: Unknown relocation type %u\n",
me->name, type);
return -EINVAL;
}
v = sym->st_value;
res = handler(me, location, v);
if (res) if (res)
return res; return res;
} }
......
...@@ -530,7 +530,7 @@ static void mipspmu_enable(struct pmu *pmu) ...@@ -530,7 +530,7 @@ static void mipspmu_enable(struct pmu *pmu)
/* /*
* MIPS performance counters can be per-TC. The control registers can * MIPS performance counters can be per-TC. The control registers can
* not be directly accessed accross CPUs. Hence if we want to do global * not be directly accessed across CPUs. Hence if we want to do global
* control, we need cross CPU calls. on_each_cpu() can help us, but we * control, we need cross CPU calls. on_each_cpu() can help us, but we
* can not make sure this function is called with interrupts enabled. So * can not make sure this function is called with interrupts enabled. So
* here we pause local counters and then grab a rwlock and leave the * here we pause local counters and then grab a rwlock and leave the
......
...@@ -472,7 +472,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) ...@@ -472,7 +472,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
/* /*
* Disable all but self interventions. The load from COHCTL is defined * Disable all but self interventions. The load from COHCTL is defined
* by the interAptiv & proAptiv SUMs as ensuring that the operation * by the interAptiv & proAptiv SUMs as ensuring that the operation
* resulting from the preceeding store is complete. * resulting from the preceding store is complete.
*/ */
uasm_i_addiu(&p, t0, zero, 1 << cpu_data[cpu].core); uasm_i_addiu(&p, t0, zero, 1 << cpu_data[cpu].core);
uasm_i_sw(&p, t0, 0, r_pcohctl); uasm_i_sw(&p, t0, 0, r_pcohctl);
......
...@@ -615,7 +615,7 @@ int mips_set_process_fp_mode(struct task_struct *task, unsigned int value) ...@@ -615,7 +615,7 @@ int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
* allows us to only worry about whether an FP mode switch is in * allows us to only worry about whether an FP mode switch is in
* progress when FP is first used in a tasks time slice. Pretty much all * progress when FP is first used in a tasks time slice. Pretty much all
* of the mode switch overhead can thus be confined to cases where mode * of the mode switch overhead can thus be confined to cases where mode
* switches are actually occuring. That is, to here. However for the * switches are actually occurring. That is, to here. However for the
* thread performing the mode switch it may take a while... * thread performing the mode switch it may take a while...
*/ */
if (num_online_cpus() > 1) { if (num_online_cpus() > 1) {
......
...@@ -596,3 +596,5 @@ EXPORT(sys_call_table) ...@@ -596,3 +596,5 @@ EXPORT(sys_call_table)
PTR sys_membarrier PTR sys_membarrier
PTR sys_mlock2 PTR sys_mlock2
PTR sys_copy_file_range /* 4360 */ PTR sys_copy_file_range /* 4360 */
PTR sys_preadv2
PTR sys_pwritev2
...@@ -434,4 +434,6 @@ EXPORT(sys_call_table) ...@@ -434,4 +434,6 @@ EXPORT(sys_call_table)
PTR sys_membarrier PTR sys_membarrier
PTR sys_mlock2 PTR sys_mlock2
PTR sys_copy_file_range /* 5320 */ PTR sys_copy_file_range /* 5320 */
PTR sys_preadv2
PTR sys_pwritev2
.size sys_call_table,.-sys_call_table .size sys_call_table,.-sys_call_table
...@@ -424,4 +424,6 @@ EXPORT(sysn32_call_table) ...@@ -424,4 +424,6 @@ EXPORT(sysn32_call_table)
PTR sys_membarrier PTR sys_membarrier
PTR sys_mlock2 PTR sys_mlock2
PTR sys_copy_file_range PTR sys_copy_file_range
PTR compat_sys_preadv2 /* 6325 */
PTR compat_sys_pwritev2
.size sysn32_call_table,.-sysn32_call_table .size sysn32_call_table,.-sysn32_call_table
...@@ -579,4 +579,6 @@ EXPORT(sys32_call_table) ...@@ -579,4 +579,6 @@ EXPORT(sys32_call_table)
PTR sys_membarrier PTR sys_membarrier
PTR sys_mlock2 PTR sys_mlock2
PTR sys_copy_file_range /* 4360 */ PTR sys_copy_file_range /* 4360 */
PTR compat_sys_preadv2
PTR compat_sys_pwritev2
.size sys32_call_table,.-sys32_call_table .size sys32_call_table,.-sys32_call_table
...@@ -243,6 +243,18 @@ static int __init mips_smp_ipi_init(void) ...@@ -243,6 +243,18 @@ static int __init mips_smp_ipi_init(void)
struct irq_domain *ipidomain; struct irq_domain *ipidomain;
struct device_node *node; struct device_node *node;
/*
* In some cases like qemu-malta, it is desired to try SMP with
* a single core. Qemu-malta has no GIC, so an attempt to set any IPIs
* would cause a BUG_ON() to be triggered since there's no ipidomain.
*
* Since for a single core system IPIs aren't required really, skip the
* initialisation which should generally keep any such configurations
* happy and only fail hard when trying to truely run SMP.
*/
if (cpumask_weight(cpu_possible_mask) == 1)
return 0;
node = of_irq_find_parent(of_root); node = of_irq_find_parent(of_root);
ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI); ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);
......
...@@ -56,6 +56,7 @@ ...@@ -56,6 +56,7 @@
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/ptrace.h> #include <asm/ptrace.h>
#include <asm/sections.h> #include <asm/sections.h>
#include <asm/siginfo.h>
#include <asm/tlbdebug.h> #include <asm/tlbdebug.h>
#include <asm/traps.h> #include <asm/traps.h>
#include <asm/uaccess.h> #include <asm/uaccess.h>
...@@ -871,7 +872,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) ...@@ -871,7 +872,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
exception_exit(prev_state); exception_exit(prev_state);
} }
void do_trap_or_bp(struct pt_regs *regs, unsigned int code, void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
const char *str) const char *str)
{ {
siginfo_t info = { 0 }; siginfo_t info = { 0 };
...@@ -928,8 +929,14 @@ void do_trap_or_bp(struct pt_regs *regs, unsigned int code, ...@@ -928,8 +929,14 @@ void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
default: default:
scnprintf(b, sizeof(b), "%s instruction in kernel code", str); scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
die_if_kernel(b, regs); die_if_kernel(b, regs);
if (si_code) {
info.si_signo = SIGTRAP;
info.si_code = si_code;
force_sig_info(SIGTRAP, &info, current);
} else {
force_sig(SIGTRAP, current); force_sig(SIGTRAP, current);
} }
}
} }
asmlinkage void do_bp(struct pt_regs *regs) asmlinkage void do_bp(struct pt_regs *regs)
...@@ -1012,7 +1019,7 @@ asmlinkage void do_bp(struct pt_regs *regs) ...@@ -1012,7 +1019,7 @@ asmlinkage void do_bp(struct pt_regs *regs)
break; break;
} }
do_trap_or_bp(regs, bcode, "Break"); do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
out: out:
set_fs(seg); set_fs(seg);
...@@ -1054,7 +1061,7 @@ asmlinkage void do_tr(struct pt_regs *regs) ...@@ -1054,7 +1061,7 @@ asmlinkage void do_tr(struct pt_regs *regs)
tcode = (opcode >> 6) & ((1 << 10) - 1); tcode = (opcode >> 6) & ((1 << 10) - 1);
} }
do_trap_or_bp(regs, tcode, "Trap"); do_trap_or_bp(regs, tcode, 0, "Trap");
out: out:
set_fs(seg); set_fs(seg);
...@@ -1115,19 +1122,7 @@ asmlinkage void do_ri(struct pt_regs *regs) ...@@ -1115,19 +1122,7 @@ asmlinkage void do_ri(struct pt_regs *regs)
if (unlikely(compute_return_epc(regs) < 0)) if (unlikely(compute_return_epc(regs) < 0))
goto out; goto out;
if (get_isa16_mode(regs->cp0_epc)) { if (!get_isa16_mode(regs->cp0_epc)) {
unsigned short mmop[2] = { 0 };
if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
status = SIGSEGV;
if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
status = SIGSEGV;
opcode = mmop[0];
opcode = (opcode << 16) | mmop[1];
if (status < 0)
status = simulate_rdhwr_mm(regs, opcode);
} else {
if (unlikely(get_user(opcode, epc) < 0)) if (unlikely(get_user(opcode, epc) < 0))
status = SIGSEGV; status = SIGSEGV;
...@@ -1142,6 +1137,18 @@ asmlinkage void do_ri(struct pt_regs *regs) ...@@ -1142,6 +1137,18 @@ asmlinkage void do_ri(struct pt_regs *regs)
if (status < 0) if (status < 0)
status = simulate_fp(regs, opcode, old_epc, old31); status = simulate_fp(regs, opcode, old_epc, old31);
} else if (cpu_has_mmips) {
unsigned short mmop[2] = { 0 };
if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
status = SIGSEGV;
if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
status = SIGSEGV;
opcode = mmop[0];
opcode = (opcode << 16) | mmop[1];
if (status < 0)
status = simulate_rdhwr_mm(regs, opcode);
} }
if (status < 0) if (status < 0)
...@@ -1492,6 +1499,7 @@ asmlinkage void do_mdmx(struct pt_regs *regs) ...@@ -1492,6 +1499,7 @@ asmlinkage void do_mdmx(struct pt_regs *regs)
*/ */
asmlinkage void do_watch(struct pt_regs *regs) asmlinkage void do_watch(struct pt_regs *regs)
{ {
siginfo_t info = { .si_signo = SIGTRAP, .si_code = TRAP_HWBKPT };
enum ctx_state prev_state; enum ctx_state prev_state;
u32 cause; u32 cause;
...@@ -1512,7 +1520,7 @@ asmlinkage void do_watch(struct pt_regs *regs) ...@@ -1512,7 +1520,7 @@ asmlinkage void do_watch(struct pt_regs *regs)
if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
mips_read_watch_registers(); mips_read_watch_registers();
local_irq_enable(); local_irq_enable();
force_sig(SIGTRAP, current); force_sig_info(SIGTRAP, &info, current);
} else { } else {
mips_clear_watch_registers(); mips_clear_watch_registers();
local_irq_enable(); local_irq_enable();
...@@ -2214,7 +2222,7 @@ void __init trap_init(void) ...@@ -2214,7 +2222,7 @@ void __init trap_init(void)
/* /*
* Copy the generic exception handlers to their final destination. * Copy the generic exception handlers to their final destination.
* This will be overriden later as suitable for a particular * This will be overridden later as suitable for a particular
* configuration. * configuration.
*/ */
set_handler(0x180, &except_vec3_generic, 0x80); set_handler(0x180, &except_vec3_generic, 0x80);
......
...@@ -885,7 +885,7 @@ static void emulate_load_store_insn(struct pt_regs *regs, ...@@ -885,7 +885,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
{ {
union mips_instruction insn; union mips_instruction insn;
unsigned long value; unsigned long value;
unsigned int res; unsigned int res, preempted;
unsigned long origpc; unsigned long origpc;
unsigned long orig31; unsigned long orig31;
void __user *fault_addr = NULL; void __user *fault_addr = NULL;
...@@ -1226,12 +1226,17 @@ static void emulate_load_store_insn(struct pt_regs *regs, ...@@ -1226,12 +1226,17 @@ static void emulate_load_store_insn(struct pt_regs *regs,
if (!access_ok(VERIFY_READ, addr, sizeof(*fpr))) if (!access_ok(VERIFY_READ, addr, sizeof(*fpr)))
goto sigbus; goto sigbus;
do {
/* /*
* Disable preemption to avoid a race between copying * If we have live MSA context keep track of
* state from userland, migrating to another CPU and * whether we get preempted in order to avoid
* updating the hardware vector register below. * the register context we load being clobbered
* by the live context as it's saved during
* preemption. If we don't have live context
* then it can't be saved to clobber the value
* we load.
*/ */
preempt_disable(); preempted = test_thread_flag(TIF_USEDMSA);
res = __copy_from_user_inatomic(fpr, addr, res = __copy_from_user_inatomic(fpr, addr,
sizeof(*fpr)); sizeof(*fpr));
...@@ -1239,14 +1244,18 @@ static void emulate_load_store_insn(struct pt_regs *regs, ...@@ -1239,14 +1244,18 @@ static void emulate_load_store_insn(struct pt_regs *regs,
goto fault; goto fault;
/* /*
* Update the hardware register if it is in use by the * Update the hardware register if it is in use
* task in this quantum, in order to avoid having to * by the task in this quantum, in order to
* save & restore the whole vector context. * avoid having to save & restore the whole
* vector context.
*/ */
if (test_thread_flag(TIF_USEDMSA)) preempt_disable();
if (test_thread_flag(TIF_USEDMSA)) {
write_msa_wr(wd, fpr, df); write_msa_wr(wd, fpr, df);
preempted = 0;
}
preempt_enable(); preempt_enable();
} while (preempted);
break; break;
case msa_st_op: case msa_st_op:
......
...@@ -632,7 +632,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) ...@@ -632,7 +632,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
kvm_debug("%s: vcpu %p, cpu: %d\n", __func__, vcpu, cpu); kvm_debug("%s: vcpu %p, cpu: %d\n", __func__, vcpu, cpu);
/* Alocate new kernel and user ASIDs if needed */ /* Allocate new kernel and user ASIDs if needed */
local_irq_save(flags); local_irq_save(flags);
......
...@@ -500,7 +500,7 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu) ...@@ -500,7 +500,7 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
kvm_write_c0_guest_config7(cop0, (MIPS_CONF7_WII) | (1 << 10)); kvm_write_c0_guest_config7(cop0, (MIPS_CONF7_WII) | (1 << 10));
/* /*
* Setup IntCtl defaults, compatibilty mode for timer interrupts (HW5) * Setup IntCtl defaults, compatibility mode for timer interrupts (HW5)
*/ */
kvm_write_c0_guest_intctl(cop0, 0xFC000000); kvm_write_c0_guest_intctl(cop0, 0xFC000000);
......
...@@ -97,7 +97,7 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm) ...@@ -97,7 +97,7 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm)
{ {
assert(xm); /* we don't gen exact zeros (probably should) */ assert(xm); /* we don't gen exact zeros (probably should) */
assert((xm >> (DP_FBITS + 1 + 3)) == 0); /* no execess */ assert((xm >> (DP_FBITS + 1 + 3)) == 0); /* no excess */
assert(xm & (DP_HIDDEN_BIT << 3)); assert(xm & (DP_HIDDEN_BIT << 3));
if (xe < DP_EMIN) { if (xe < DP_EMIN) {
...@@ -165,7 +165,7 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm) ...@@ -165,7 +165,7 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm)
/* strip grs bits */ /* strip grs bits */
xm >>= 3; xm >>= 3;
assert((xm >> (DP_FBITS + 1)) == 0); /* no execess */ assert((xm >> (DP_FBITS + 1)) == 0); /* no excess */
assert(xe >= DP_EMIN); assert(xe >= DP_EMIN);
if (xe > DP_EMAX) { if (xe > DP_EMAX) {
...@@ -198,7 +198,7 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm) ...@@ -198,7 +198,7 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm)
ieee754_setcx(IEEE754_UNDERFLOW); ieee754_setcx(IEEE754_UNDERFLOW);
return builddp(sn, DP_EMIN - 1 + DP_EBIAS, xm); return builddp(sn, DP_EMIN - 1 + DP_EBIAS, xm);
} else { } else {
assert((xm >> (DP_FBITS + 1)) == 0); /* no execess */ assert((xm >> (DP_FBITS + 1)) == 0); /* no excess */
assert(xm & DP_HIDDEN_BIT); assert(xm & DP_HIDDEN_BIT);
return builddp(sn, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT); return builddp(sn, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT);
......
...@@ -97,7 +97,7 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm) ...@@ -97,7 +97,7 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
{ {
assert(xm); /* we don't gen exact zeros (probably should) */ assert(xm); /* we don't gen exact zeros (probably should) */
assert((xm >> (SP_FBITS + 1 + 3)) == 0); /* no execess */ assert((xm >> (SP_FBITS + 1 + 3)) == 0); /* no excess */
assert(xm & (SP_HIDDEN_BIT << 3)); assert(xm & (SP_HIDDEN_BIT << 3));
if (xe < SP_EMIN) { if (xe < SP_EMIN) {
...@@ -163,7 +163,7 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm) ...@@ -163,7 +163,7 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
/* strip grs bits */ /* strip grs bits */
xm >>= 3; xm >>= 3;
assert((xm >> (SP_FBITS + 1)) == 0); /* no execess */ assert((xm >> (SP_FBITS + 1)) == 0); /* no excess */
assert(xe >= SP_EMIN); assert(xe >= SP_EMIN);
if (xe > SP_EMAX) { if (xe > SP_EMAX) {
...@@ -196,7 +196,7 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm) ...@@ -196,7 +196,7 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
ieee754_setcx(IEEE754_UNDERFLOW); ieee754_setcx(IEEE754_UNDERFLOW);
return buildsp(sn, SP_EMIN - 1 + SP_EBIAS, xm); return buildsp(sn, SP_EMIN - 1 + SP_EBIAS, xm);
} else { } else {
assert((xm >> (SP_FBITS + 1)) == 0); /* no execess */ assert((xm >> (SP_FBITS + 1)) == 0); /* no excess */
assert(xm & SP_HIDDEN_BIT); assert(xm & SP_HIDDEN_BIT);
return buildsp(sn, xe + SP_EBIAS, xm & ~SP_HIDDEN_BIT); return buildsp(sn, xe + SP_EBIAS, xm & ~SP_HIDDEN_BIT);
......
...@@ -158,7 +158,7 @@ static inline int __init indy_sc_probe(void) ...@@ -158,7 +158,7 @@ static inline int __init indy_sc_probe(void)
return 1; return 1;
} }
/* XXX Check with wje if the Indy caches can differenciate between /* XXX Check with wje if the Indy caches can differentiate between
writeback + invalidate and just invalidate. */ writeback + invalidate and just invalidate. */
static struct bcache_ops indy_sc_ops = { static struct bcache_ops indy_sc_ops = {
.bc_enable = indy_sc_enable, .bc_enable = indy_sc_enable,
......
...@@ -19,6 +19,7 @@ ...@@ -19,6 +19,7 @@
#include <asm/cpu.h> #include <asm/cpu.h>
#include <asm/cpu-type.h> #include <asm/cpu-type.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/hazards.h>
#include <asm/mmu_context.h> #include <asm/mmu_context.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/tlb.h> #include <asm/tlb.h>
...@@ -486,6 +487,10 @@ static void r4k_tlb_configure(void) ...@@ -486,6 +487,10 @@ static void r4k_tlb_configure(void)
* be set to fixed-size pages. * be set to fixed-size pages.
*/ */
write_c0_pagemask(PM_DEFAULT_MASK); write_c0_pagemask(PM_DEFAULT_MASK);
back_to_back_c0_hazard();
if (read_c0_pagemask() != PM_DEFAULT_MASK)
panic("MMU doesn't support PAGE_SIZE=0x%lx", PAGE_SIZE);
write_c0_wired(0); write_c0_wired(0);
if (current_cpu_type() == CPU_R10000 || if (current_cpu_type() == CPU_R10000 ||
current_cpu_type() == CPU_R12000 || current_cpu_type() == CPU_R12000 ||
......
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
* Copyright (C) 2011 MIPS Technologies, Inc. * Copyright (C) 2011 MIPS Technologies, Inc.
* *
* ... and the days got worse and worse and now you see * ... and the days got worse and worse and now you see
* I've gone completly out of my mind. * I've gone completely out of my mind.
* *
* They're coming to take me a away haha * They're coming to take me a away haha
* they're coming to take me a away hoho hihi haha * they're coming to take me a away hoho hihi haha
......
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
* Copyright (C) 2000 by Silicon Graphics, Inc. * Copyright (C) 2000 by Silicon Graphics, Inc.
* Copyright (C) 2004 by Christoph Hellwig * Copyright (C) 2004 by Christoph Hellwig
* *
* On SGI IP27 the ARC memory configuration data is completly bogus but * On SGI IP27 the ARC memory configuration data is completely bogus but
* alternate easier to use mechanisms are available. * alternate easier to use mechanisms are available.
*/ */
#include <linux/init.h> #include <linux/init.h>
......
...@@ -56,6 +56,7 @@ struct db1x_pcmcia_sock { ...@@ -56,6 +56,7 @@ struct db1x_pcmcia_sock {
int stschg_irq; /* card-status-change irq */ int stschg_irq; /* card-status-change irq */
int card_irq; /* card irq */ int card_irq; /* card irq */
int eject_irq; /* db1200/pb1200 have these */ int eject_irq; /* db1200/pb1200 have these */
int insert_gpio; /* db1000 carddetect gpio */
#define BOARD_TYPE_DEFAULT 0 /* most boards */ #define BOARD_TYPE_DEFAULT 0 /* most boards */
#define BOARD_TYPE_DB1200 1 /* IRQs aren't gpios */ #define BOARD_TYPE_DB1200 1 /* IRQs aren't gpios */
...@@ -83,7 +84,7 @@ static int db1200_card_inserted(struct db1x_pcmcia_sock *sock) ...@@ -83,7 +84,7 @@ static int db1200_card_inserted(struct db1x_pcmcia_sock *sock)
/* carddetect gpio: low-active */ /* carddetect gpio: low-active */
static int db1000_card_inserted(struct db1x_pcmcia_sock *sock) static int db1000_card_inserted(struct db1x_pcmcia_sock *sock)
{ {
return !gpio_get_value(irq_to_gpio(sock->insert_irq)); return !gpio_get_value(sock->insert_gpio);
} }
static int db1x_card_inserted(struct db1x_pcmcia_sock *sock) static int db1x_card_inserted(struct db1x_pcmcia_sock *sock)
...@@ -457,9 +458,15 @@ static int db1x_pcmcia_socket_probe(struct platform_device *pdev) ...@@ -457,9 +458,15 @@ static int db1x_pcmcia_socket_probe(struct platform_device *pdev)
r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "card"); r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "card");
sock->card_irq = r ? r->start : 0; sock->card_irq = r ? r->start : 0;
/* insert: irq which triggers on card insertion/ejection */ /* insert: irq which triggers on card insertion/ejection
* BIG FAT NOTE: on DB1000/1100/1500/1550 we pass a GPIO here!
*/
r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "insert"); r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "insert");
sock->insert_irq = r ? r->start : -1; sock->insert_irq = r ? r->start : -1;
if (sock->board_type == BOARD_TYPE_DEFAULT) {
sock->insert_gpio = r ? r->start : -1;
sock->insert_irq = r ? gpio_to_irq(r->start) : -1;
}
/* stschg: irq which trigger on card status change (optional) */ /* stschg: irq which trigger on card status change (optional) */
r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "stschg"); r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "stschg");
......
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