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Commit c680b77e authored by Lennert Buytenhek's avatar Lennert Buytenhek Committed by Russell King
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[ARM] 3830/1: iop3xx: board support file cleanup 

Revamp the iop3xx board support: move the support code for each iop
board type into its own file, start using platform serial and platform
physmap flash devices, switch to a per-board time tick rate, and get
rid of the ARCH_EP80219 and STEPD config options by doing the relevant
checks at run time.
Signed-off-by: default avatarLennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 7412b10f
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Showing with 911 additions and 944 deletions
arch/arm/configs/ep80219_defconfig
View file @ c680b77e
...@@ -93,7 +93,6 @@ CONFIG_ARCH_IOP32X=y ...@@ -93,7 +93,6 @@ CONFIG_ARCH_IOP32X=y
CONFIG_ARCH_IQ31244=y CONFIG_ARCH_IQ31244=y
# CONFIG_ARCH_IQ80331 is not set # CONFIG_ARCH_IQ80331 is not set
# CONFIG_MACH_IQ80332 is not set # CONFIG_MACH_IQ80332 is not set
CONFIG_ARCH_EP80219=y
# #
# IOP3xx Chipset Features # IOP3xx Chipset Features
...@@ -231,9 +230,9 @@ CONFIG_MTD_CFI_UTIL=y ...@@ -231,9 +230,9 @@ CONFIG_MTD_CFI_UTIL=y
# #
# CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_START=0xf0000000 CONFIG_MTD_PHYSMAP_START=0x0
CONFIG_MTD_PHYSMAP_LEN=0x00800000 CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2 CONFIG_MTD_PHYSMAP_BANKWIDTH=1
# CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_EDB7312 is not set # CONFIG_MTD_EDB7312 is not set
......
arch/arm/configs/iq31244_defconfig
View file @ c680b77e
...@@ -94,7 +94,6 @@ CONFIG_ARCH_IOP32X=y ...@@ -94,7 +94,6 @@ CONFIG_ARCH_IOP32X=y
CONFIG_ARCH_IQ31244=y CONFIG_ARCH_IQ31244=y
# CONFIG_ARCH_IQ80331 is not set # CONFIG_ARCH_IQ80331 is not set
# CONFIG_MACH_IQ80332 is not set # CONFIG_MACH_IQ80332 is not set
# CONFIG_ARCH_EP80219 is not set
# #
# IOP3xx Chipset Features # IOP3xx Chipset Features
...@@ -232,9 +231,9 @@ CONFIG_MTD_CFI_UTIL=y ...@@ -232,9 +231,9 @@ CONFIG_MTD_CFI_UTIL=y
# #
# CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_START=0xf0000000 CONFIG_MTD_PHYSMAP_START=0x0
CONFIG_MTD_PHYSMAP_LEN=0x00800000 CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2 CONFIG_MTD_PHYSMAP_BANKWIDTH=1
# CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_EDB7312 is not set # CONFIG_MTD_EDB7312 is not set
......
arch/arm/configs/iq80321_defconfig
View file @ c680b77e
...@@ -93,7 +93,6 @@ CONFIG_ARCH_IQ80321=y ...@@ -93,7 +93,6 @@ CONFIG_ARCH_IQ80321=y
# CONFIG_ARCH_IQ31244 is not set # CONFIG_ARCH_IQ31244 is not set
# CONFIG_ARCH_IQ80331 is not set # CONFIG_ARCH_IQ80331 is not set
# CONFIG_MACH_IQ80332 is not set # CONFIG_MACH_IQ80332 is not set
# CONFIG_ARCH_EP80219 is not set
# #
# IOP3xx Chipset Features # IOP3xx Chipset Features
...@@ -231,8 +230,8 @@ CONFIG_MTD_CFI_UTIL=y ...@@ -231,8 +230,8 @@ CONFIG_MTD_CFI_UTIL=y
# #
# CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_START=0xf0000000 CONFIG_MTD_PHYSMAP_START=0x0
CONFIG_MTD_PHYSMAP_LEN=0x00800000 CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_BANKWIDTH=1 CONFIG_MTD_PHYSMAP_BANKWIDTH=1
# CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_EDB7312 is not set # CONFIG_MTD_EDB7312 is not set
......
arch/arm/configs/iq80331_defconfig
View file @ c680b77e
...@@ -93,12 +93,6 @@ CONFIG_ARCH_IOP33X=y ...@@ -93,12 +93,6 @@ CONFIG_ARCH_IOP33X=y
# CONFIG_ARCH_IQ31244 is not set # CONFIG_ARCH_IQ31244 is not set
CONFIG_ARCH_IQ80331=y CONFIG_ARCH_IQ80331=y
# CONFIG_MACH_IQ80332 is not set # CONFIG_MACH_IQ80332 is not set
# CONFIG_ARCH_EP80219 is not set
#
# IOP3xx Chipset Features
#
CONFIG_IOP331_STEPD=y
# #
# Processor Type # Processor Type
...@@ -236,8 +230,8 @@ CONFIG_MTD_CFI_UTIL=y ...@@ -236,8 +230,8 @@ CONFIG_MTD_CFI_UTIL=y
# #
# CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_START=0xc0000000 CONFIG_MTD_PHYSMAP_START=0x0
CONFIG_MTD_PHYSMAP_LEN=0x00800000 CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_BANKWIDTH=1 CONFIG_MTD_PHYSMAP_BANKWIDTH=1
# CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_EDB7312 is not set # CONFIG_MTD_EDB7312 is not set
......
arch/arm/configs/iq80332_defconfig
View file @ c680b77e
...@@ -93,12 +93,6 @@ CONFIG_ARCH_IOP33X=y ...@@ -93,12 +93,6 @@ CONFIG_ARCH_IOP33X=y
# CONFIG_ARCH_IQ31244 is not set # CONFIG_ARCH_IQ31244 is not set
# CONFIG_ARCH_IQ80331 is not set # CONFIG_ARCH_IQ80331 is not set
CONFIG_MACH_IQ80332=y CONFIG_MACH_IQ80332=y
# CONFIG_ARCH_EP80219 is not set
#
# IOP3xx Chipset Features
#
# CONFIG_IOP331_STEPD is not set
# #
# Processor Type # Processor Type
...@@ -236,8 +230,8 @@ CONFIG_MTD_CFI_UTIL=y ...@@ -236,8 +230,8 @@ CONFIG_MTD_CFI_UTIL=y
# #
# CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_START=0xc0000000 CONFIG_MTD_PHYSMAP_START=0x0
CONFIG_MTD_PHYSMAP_LEN=0x00800000 CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_BANKWIDTH=1 CONFIG_MTD_PHYSMAP_BANKWIDTH=1
# CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_EDB7312 is not set # CONFIG_MTD_EDB7312 is not set
......
arch/arm/mach-iop32x/Kconfig
View file @ c680b77e
...@@ -16,13 +16,6 @@ config ARCH_IQ31244 ...@@ -16,13 +16,6 @@ config ARCH_IQ31244
Say Y here if you want to run your kernel on the Intel IQ31244 Say Y here if you want to run your kernel on the Intel IQ31244
evaluation kit for the IOP321 chipset. evaluation kit for the IOP321 chipset.
config ARCH_EP80219
bool "Enable support for EP80219"
select ARCH_IQ31244
help
Say Y here if you want to run your kernel on the Intel EP80219
evaluation kit for the Intel 80219 chipset (a IOP321 variant).
endmenu endmenu
endif endif
arch/arm/mach-iop32x/Makefile
View file @ c680b77e
...@@ -2,10 +2,10 @@ ...@@ -2,10 +2,10 @@
# Makefile for the linux kernel. # Makefile for the linux kernel.
# #
obj-y := common.o setup.o irq.o obj-y := irq.o
obj-m := obj-m :=
obj-n := obj-n :=
obj- := obj- :=
obj-$(CONFIG_ARCH_IQ80321) += iq80321-mm.o iq80321-pci.o obj-$(CONFIG_ARCH_IQ80321) += iq80321.o
obj-$(CONFIG_ARCH_IQ31244) += iq31244-mm.o iq31244-pci.o obj-$(CONFIG_ARCH_IQ31244) += iq31244.o
arch/arm/mach-iop32x/common.c deleted 100644 → 0
View file @ 7412b10f
/*
* arch/arm/mach-iop32x/common.c
*
* Common routines shared across all IOP3xx implementations
*
* Author: Deepak Saxena <dsaxena@mvista.com>
*
* Copyright 2003 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/delay.h>
#include <asm/hardware.h>
#include <asm/hardware/iop3xx.h>
#ifdef CONFIG_ARCH_EP80219
#include <linux/kernel.h>
/*
* Default power-off for EP80219
*/
static inline void ep80219_send_to_pic(__u8 c) {
}
void ep80219_power_off(void)
{
/*
* This function will send a SHUTDOWN_COMPLETE message to the PIC controller
* over I2C. We are not using the i2c subsystem since we are going to power
* off and it may be removed
*/
/* Send the Address byte w/ the start condition */
*IOP3XX_IDBR1 = 0x60;
*IOP3XX_ICR1 = 0xE9;
mdelay(1);
/* Send the START_MSG byte w/ no start or stop condition */
*IOP3XX_IDBR1 = 0x0F;
*IOP3XX_ICR1 = 0xE8;
mdelay(1);
/* Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or stop condition */
*IOP3XX_IDBR1 = 0x03;
*IOP3XX_ICR1 = 0xE8;
mdelay(1);
/* Send an ignored byte w/ stop condition */
*IOP3XX_IDBR1 = 0x00;
*IOP3XX_ICR1 = 0xEA;
while (1) ;
}
#include <linux/init.h>
#include <linux/pm.h>
static int __init ep80219_init(void)
{
pm_power_off = ep80219_power_off;
return 0;
}
arch_initcall(ep80219_init);
#endif
arch/arm/mach-iop32x/iq31244-mm.c deleted 100644 → 0
View file @ 7412b10f
/*
* linux/arch/arm/mach-iop32x/iq31244-mm.c
*
* Low level memory initialization for iq80321 platform
*
* Author: Rory Bolt <rorybolt@pacbell.net>
* Copyright (C) 2002 Rory Bolt
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <asm/hardware/iop3xx.h>
/*
* IQ80321 specific IO mappings
*
* We use RedBoot's setup for the onboard devices.
*/
static struct map_desc iq31244_io_desc[] __initdata = {
{ /* on-board devices */
.virtual = IQ31244_UART,
.pfn = __phys_to_pfn(IQ31244_UART),
.length = 0x00100000,
.type = MT_DEVICE
}
};
void __init iq31244_map_io(void)
{
iop3xx_map_io();
iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
}
arch/arm/mach-iop32x/iq31244-pci.c deleted 100644 → 0
View file @ 7412b10f
/*
* arch/arm/mach-iop32x/iq31244-pci.c
*
* PCI support for the Intel IQ31244 reference board
*
* Author: Rory Bolt <rorybolt@pacbell.net>
* Copyright (C) 2002 Rory Bolt
* Copyright (C) 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
/*
* The following macro is used to lookup irqs in a standard table
* format for those systems that do not already have PCI
* interrupts properly routed. We assume 1 <= pin <= 4
*/
#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
({ int _ctl_ = -1; \
unsigned int _idsel = idsel - minid; \
if (_idsel <= maxid) \
_ctl_ = pci_irq_table[_idsel][pin-1]; \
_ctl_; })
#define INTA IRQ_IQ31244_INTA
#define INTB IRQ_IQ31244_INTB
#define INTC IRQ_IQ31244_INTC
#define INTD IRQ_IQ31244_INTD
#define INTE IRQ_IQ31244_I82546
static inline int __init
iq31244_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
{
static int pci_irq_table[][4] = {
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
#ifdef CONFIG_ARCH_EP80219
{INTB, INTB, INTB, INTB}, /* CFlash */
{INTE, INTE, INTE, INTE}, /* 82551 Pro 100 */
{INTD, INTD, INTD, INTD}, /* PCI-X Slot */
{INTC, INTC, INTC, INTC}, /* SATA */
#else
{INTB, INTB, INTB, INTB}, /* CFlash */
{INTC, INTC, INTC, INTC}, /* SATA */
{INTD, INTD, INTD, INTD}, /* PCI-X Slot */
{INTE, INTE, INTE, INTE}, /* 82546 GigE */
#endif // CONFIG_ARCH_EP80219
};
BUG_ON(pin < 1 || pin > 4);
return PCI_IRQ_TABLE_LOOKUP(0, 7);
}
static struct hw_pci iq31244_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iop3xx_pci_setup,
.scan = iop3xx_pci_scan_bus,
.preinit = iop3xx_pci_preinit,
.map_irq = iq31244_map_irq
};
static int __init iq31244_pci_init(void)
{
if (machine_is_iq31244())
pci_common_init(&iq31244_pci);
return 0;
}
subsys_initcall(iq31244_pci_init);
arch/arm/mach-iop32x/iq31244.c 0 → 100644
View file @ c680b77e
/*
* arch/arm/mach-iop32x/iq31244.c
*
* Board support code for the Intel EP80219 and IQ31244 platforms.
*
* Author: Rory Bolt <rorybolt@pacbell.net>
* Copyright (C) 2002 Rory Bolt
* Copyright 2003 (c) MontaVista, Software, Inc.
* Copyright (C) 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/pm.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/pci.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
/*
* The EP80219 and IQ31244 use the same machine ID. To find out
* which of the two we're running on, we look at the processor ID.
*/
static int is_80219(void)
{
extern int processor_id;
return !!((processor_id & 0xffffffe0) == 0x69052e20);
}
/*
* EP80219/IQ31244 timer tick configuration.
*/
static void __init iq31244_timer_init(void)
{
if (is_80219()) {
/* 33.333 MHz crystal. */
iop3xx_init_time(200000000);
} else {
/* 33.000 MHz crystal. */
iop3xx_init_time(198000000);
}
}
static struct sys_timer iq31244_timer = {
.init = iq31244_timer_init,
.offset = iop3xx_gettimeoffset,
};
/*
* IQ31244 I/O.
*/
static struct map_desc iq31244_io_desc[] __initdata = {
{ /* on-board devices */
.virtual = IQ31244_UART,
.pfn = __phys_to_pfn(IQ31244_UART),
.length = 0x00100000,
.type = MT_DEVICE,
},
};
void __init iq31244_map_io(void)
{
iop3xx_map_io();
iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
}
/*
* EP80219/IQ31244 PCI.
*/
static inline int __init
ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
if (slot == 0) {
/* CFlash */
irq = IRQ_IOP321_XINT1;
} else if (slot == 1) {
/* 82551 Pro 100 */
irq = IRQ_IOP321_XINT0;
} else if (slot == 2) {
/* PCI-X Slot */
irq = IRQ_IOP321_XINT3;
} else if (slot == 3) {
/* SATA */
irq = IRQ_IOP321_XINT2;
} else {
printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
"device PCI:%d:%d:%d\n", dev->bus->number,
PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
irq = -1;
}
return irq;
}
static struct hw_pci ep80219_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
.scan = iop3xx_pci_scan_bus,
.map_irq = ep80219_pci_map_irq,
};
static inline int __init
iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
if (slot == 0) {
/* CFlash */
irq = IRQ_IOP321_XINT1;
} else if (slot == 1) {
/* SATA */
irq = IRQ_IOP321_XINT2;
} else if (slot == 2) {
/* PCI-X Slot */
irq = IRQ_IOP321_XINT3;
} else if (slot == 3) {
/* 82546 GigE */
irq = IRQ_IOP321_XINT0;
} else {
printk(KERN_ERR "iq31244_pci_map_irq() called for unknown "
"device PCI:%d:%d:%d\n", dev->bus->number,
PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
irq = -1;
}
return irq;
}
static struct hw_pci iq31244_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
.scan = iop3xx_pci_scan_bus,
.map_irq = iq31244_pci_map_irq,
};
static int __init iq31244_pci_init(void)
{
if (machine_is_iq31244()) {
if (is_80219()) {
pci_common_init(&ep80219_pci);
} else {
pci_common_init(&iq31244_pci);
}
}
return 0;
}
subsys_initcall(iq31244_pci_init);
/*
* IQ31244 machine initialisation.
*/
static struct physmap_flash_data iq31244_flash_data = {
.width = 2,
};
static struct resource iq31244_flash_resource = {
.start = 0xf0000000,
.end = 0xf07fffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device iq31244_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &iq31244_flash_data,
},
.num_resources = 1,
.resource = &iq31244_flash_resource,
};
static struct plat_serial8250_port iq31244_serial_port[] = {
{
.mapbase = IQ31244_UART,
.membase = (char *)IQ31244_UART,
.irq = IRQ_IOP321_XINT1,
.flags = UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 0,
.uartclk = 1843200,
},
{ },
};
static struct resource iq31244_uart_resource = {
.start = IQ31244_UART,
.end = IQ31244_UART + 7,
.flags = IORESOURCE_MEM,
};
static struct platform_device iq31244_serial_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = iq31244_serial_port,
},
.num_resources = 1,
.resource = &iq31244_uart_resource,
};
/*
* This function will send a SHUTDOWN_COMPLETE message to the PIC
* controller over I2C. We are not using the i2c subsystem since
* we are going to power off and it may be removed
*/
void ep80219_power_off(void)
{
/*
* Send the Address byte w/ the start condition
*/
*IOP3XX_IDBR1 = 0x60;
*IOP3XX_ICR1 = 0xE9;
mdelay(1);
/*
* Send the START_MSG byte w/ no start or stop condition
*/
*IOP3XX_IDBR1 = 0x0F;
*IOP3XX_ICR1 = 0xE8;
mdelay(1);
/*
* Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or
* stop condition
*/
*IOP3XX_IDBR1 = 0x03;
*IOP3XX_ICR1 = 0xE8;
mdelay(1);
/*
* Send an ignored byte w/ stop condition
*/
*IOP3XX_IDBR1 = 0x00;
*IOP3XX_ICR1 = 0xEA;
while (1)
;
}
static void __init iq31244_init_machine(void)
{
platform_device_register(&iop3xx_i2c0_device);
platform_device_register(&iop3xx_i2c1_device);
platform_device_register(&iq31244_flash_device);
platform_device_register(&iq31244_serial_device);
if (is_80219())
pm_power_off = ep80219_power_off;
}
MACHINE_START(IQ31244, "Intel IQ31244")
/* Maintainer: Intel Corp. */
.phys_io = IQ31244_UART,
.io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = iq31244_map_io,
.init_irq = iop321_init_irq,
.timer = &iq31244_timer,
.init_machine = iq31244_init_machine,
MACHINE_END
arch/arm/mach-iop32x/iq80321-mm.c deleted 100644 → 0
View file @ 7412b10f
/*
* linux/arch/arm/mach-iop32x/iq80321-mm.c
*
* Low level memory initialization for iq80321 platform
*
* Author: Rory Bolt <rorybolt@pacbell.net>
* Copyright (C) 2002 Rory Bolt
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <asm/hardware/iop3xx.h>
/*
* IQ80321 specific IO mappings
*
* We use RedBoot's setup for the onboard devices.
*/
static struct map_desc iq80321_io_desc[] __initdata = {
{ /* on-board devices */
.virtual = IQ80321_UART,
.pfn = __phys_to_pfn(IQ80321_UART),
.length = 0x00100000,
.type = MT_DEVICE
}
};
void __init iq80321_map_io(void)
{
iop3xx_map_io();
iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc));
}
arch/arm/mach-iop32x/iq80321-pci.c deleted 100644 → 0
View file @ 7412b10f
/*
* arch/arm/mach-iop32x/iq80321-pci.c
*
* PCI support for the Intel IQ80321 reference board
*
* Author: Rory Bolt <rorybolt@pacbell.net>
* Copyright (C) 2002 Rory Bolt
* Copyright (C) 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
/*
* The following macro is used to lookup irqs in a standard table
* format for those systems that do not already have PCI
* interrupts properly routed. We assume 1 <= pin <= 4
*/
#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
({ int _ctl_ = -1; \
unsigned int _idsel = idsel - minid; \
if (_idsel <= maxid) \
_ctl_ = pci_irq_table[_idsel][pin-1]; \
_ctl_; })
#define INTA IRQ_IQ80321_INTA
#define INTB IRQ_IQ80321_INTB
#define INTC IRQ_IQ80321_INTC
#define INTD IRQ_IQ80321_INTD
#define INTE IRQ_IQ80321_I82544
static inline int __init
iq80321_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
{
static int pci_irq_table[][4] = {
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{INTE, INTE, INTE, INTE}, /* Gig-E */
{-1, -1, -1, -1}, /* Unused */
{INTC, INTD, INTA, INTB}, /* PCI-X Slot */
{-1, -1, -1, -1},
};
BUG_ON(pin < 1 || pin > 4);
// return PCI_IRQ_TABLE_LOOKUP(4, 7);
return pci_irq_table[idsel%4][pin-1];
}
static struct hw_pci iq80321_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iop3xx_pci_setup,
.scan = iop3xx_pci_scan_bus,
.preinit = iop3xx_pci_preinit,
.map_irq = iq80321_map_irq
};
static int __init iq80321_pci_init(void)
{
if (machine_is_iq80321())
pci_common_init(&iq80321_pci);
return 0;
}
subsys_initcall(iq80321_pci_init);
arch/arm/mach-iop32x/iq80321.c 0 → 100644
View file @ c680b77e
/*
* arch/arm/mach-iop32x/iq80321.c
*
* Board support code for the Intel IQ80321 platform.
*
* Author: Rory Bolt <rorybolt@pacbell.net>
* Copyright (C) 2002 Rory Bolt
* Copyright (C) 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/pci.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
/*
* IQ80321 timer tick configuration.
*/
static void __init iq80321_timer_init(void)
{
/* 33.333 MHz crystal. */
iop3xx_init_time(200000000);
}
static struct sys_timer iq80321_timer = {
.init = iq80321_timer_init,
.offset = iop3xx_gettimeoffset,
};
/*
* IQ80321 I/O.
*/
static struct map_desc iq80321_io_desc[] __initdata = {
{ /* on-board devices */
.virtual = IQ80321_UART,
.pfn = __phys_to_pfn(IQ80321_UART),
.length = 0x00100000,
.type = MT_DEVICE,
},
};
void __init iq80321_map_io(void)
{
iop3xx_map_io();
iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc));
}
/*
* IQ80321 PCI.
*/
static inline int __init
iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
if ((slot == 2 || slot == 6) && pin == 1) {
/* PCI-X Slot INTA */
irq = IRQ_IOP321_XINT2;
} else if ((slot == 2 || slot == 6) && pin == 2) {
/* PCI-X Slot INTA */
irq = IRQ_IOP321_XINT3;
} else if ((slot == 2 || slot == 6) && pin == 3) {
/* PCI-X Slot INTA */
irq = IRQ_IOP321_XINT0;
} else if ((slot == 2 || slot == 6) && pin == 4) {
/* PCI-X Slot INTA */
irq = IRQ_IOP321_XINT1;
} else if (slot == 4 || slot == 8) {
/* Gig-E */
irq = IRQ_IOP321_XINT0;
} else {
printk(KERN_ERR "iq80321_pci_map_irq() called for unknown "
"device PCI:%d:%d:%d\n", dev->bus->number,
PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
irq = -1;
}
return irq;
}
static struct hw_pci iq80321_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
.scan = iop3xx_pci_scan_bus,
.map_irq = iq80321_pci_map_irq,
};
static int __init iq80321_pci_init(void)
{
if (machine_is_iq80321())
pci_common_init(&iq80321_pci);
return 0;
}
subsys_initcall(iq80321_pci_init);
/*
* IQ80321 machine initialisation.
*/
static struct physmap_flash_data iq80321_flash_data = {
.width = 1,
};
static struct resource iq80321_flash_resource = {
.start = 0xf0000000,
.end = 0xf07fffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device iq80321_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &iq80321_flash_data,
},
.num_resources = 1,
.resource = &iq80321_flash_resource,
};
static struct plat_serial8250_port iq80321_serial_port[] = {
{
.mapbase = IQ80321_UART,
.membase = (char *)IQ80321_UART,
.irq = IRQ_IOP321_XINT1,
.flags = UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 0,
.uartclk = 1843200,
},
{ },
};
static struct resource iq80321_uart_resource = {
.start = IQ80321_UART,
.end = IQ80321_UART + 7,
.flags = IORESOURCE_MEM,
};
static struct platform_device iq80321_serial_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = iq80321_serial_port,
},
.num_resources = 1,
.resource = &iq80321_uart_resource,
};
static void __init iq80321_init_machine(void)
{
platform_device_register(&iop3xx_i2c0_device);
platform_device_register(&iop3xx_i2c1_device);
platform_device_register(&iq80321_flash_device);
platform_device_register(&iq80321_serial_device);
}
MACHINE_START(IQ80321, "Intel IQ80321")
/* Maintainer: Intel Corp. */
.phys_io = IQ80321_UART,
.io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = iq80321_map_io,
.init_irq = iop321_init_irq,
.timer = &iq80321_timer,
.init_machine = iq80321_init_machine,
MACHINE_END
arch/arm/mach-iop32x/setup.c deleted 100644 → 0
View file @ 7412b10f
/*
* linux/arch/arm/mach-iop32x/setup.c
*
* Author: Nicolas Pitre <nico@cam.org>
* Copyright (C) 2001 MontaVista Software, Inc.
* Copyright (C) 2004 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/major.h>
#include <linux/fs.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_core.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <asm/system.h>
#include <asm/memory.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/hardware/iop3xx.h>
#define IOP321_UART_XTAL 1843200
#ifdef CONFIG_ARCH_IQ80321
#define UARTBASE IQ80321_UART
#define IRQ_UART IRQ_IQ80321_UART
#endif
#ifdef CONFIG_ARCH_IQ31244
#define UARTBASE IQ31244_UART
#define IRQ_UART IRQ_IQ31244_UART
#endif
static struct uart_port iop321_serial_ports[] = {
{
.membase = (char*)(UARTBASE),
.mapbase = (UARTBASE),
.irq = IRQ_UART,
.flags = UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 0,
.uartclk = IOP321_UART_XTAL,
.line = 0,
.type = PORT_16550A,
.fifosize = 16
}
};
void __init iop32x_init(void)
{
platform_device_register(&iop3xx_i2c0_device);
platform_device_register(&iop3xx_i2c1_device);
early_serial_setup(&iop321_serial_ports[0]);
}
#ifdef CONFIG_ARCH_IQ80321
extern void iq80321_map_io(void);
#endif
#ifdef CONFIG_ARCH_IQ31244
extern void iq31244_map_io(void);
#endif
static void __init iop3xx_timer_init(void)
{
iop3xx_init_time(IOP321_TICK_RATE);
}
struct sys_timer iop321_timer = {
.init = iop3xx_timer_init,
.offset = iop3xx_gettimeoffset,
};
#if defined(CONFIG_ARCH_IQ80321)
MACHINE_START(IQ80321, "Intel IQ80321")
/* Maintainer: Intel Corporation */
.phys_io = IQ80321_UART,
.io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc,
.map_io = iq80321_map_io,
.init_irq = iop321_init_irq,
.timer = &iop321_timer,
.boot_params = 0xa0000100,
.init_machine = iop32x_init,
MACHINE_END
#elif defined(CONFIG_ARCH_IQ31244)
MACHINE_START(IQ31244, "Intel IQ31244")
/* Maintainer: Intel Corp. */
.phys_io = IQ31244_UART,
.io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
.map_io = iq31244_map_io,
.init_irq = iop321_init_irq,
.timer = &iop321_timer,
.boot_params = 0xa0000100,
.init_machine = iop32x_init,
MACHINE_END
#else
#error No machine descriptor defined for this IOP3XX implementation
#endif
arch/arm/mach-iop33x/Kconfig
View file @ c680b77e
...@@ -16,12 +16,6 @@ config MACH_IQ80332 ...@@ -16,12 +16,6 @@ config MACH_IQ80332
Say Y here if you want to run your kernel on the Intel IQ80332 Say Y here if you want to run your kernel on the Intel IQ80332
evaluation kit for the IOP332 chipset. evaluation kit for the IOP332 chipset.
config IOP331_STEPD
bool "Chip stepping D of the IOP80331 processor or IOP80333"
help
Say Y here if you have StepD of the IOP80331 or IOP8033
based platforms.
endmenu endmenu
endif endif
arch/arm/mach-iop33x/Makefile
View file @ c680b77e
...@@ -2,10 +2,10 @@ ...@@ -2,10 +2,10 @@
# Makefile for the linux kernel. # Makefile for the linux kernel.
# #
obj-y := setup.o irq.o obj-y := irq.o uart.o
obj-m := obj-m :=
obj-n := obj-n :=
obj- := obj- :=
obj-$(CONFIG_ARCH_IQ80331) += iq80331-pci.o obj-$(CONFIG_ARCH_IQ80331) += iq80331.o
obj-$(CONFIG_MACH_IQ80332) += iq80332-pci.o obj-$(CONFIG_MACH_IQ80332) += iq80332.o
arch/arm/mach-iop33x/iq80331-pci.c deleted 100644 → 0
View file @ 7412b10f
/*
* arch/arm/mach-iop33x/iq80331-pci.c
*
* PCI support for the Intel IQ80331 reference board
*
* Author: Dave Jiang <dave.jiang@intel.com>
* Copyright (C) 2003, 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
/*
* The following macro is used to lookup irqs in a standard table
* format for those systems that do not already have PCI
* interrupts properly routed. We assume 1 <= pin <= 4
*/
#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
({ int _ctl_ = -1; \
unsigned int _idsel = idsel - minid; \
if (_idsel <= maxid) \
_ctl_ = pci_irq_table[_idsel][pin-1]; \
_ctl_; })
#define INTA IRQ_IQ80331_INTA
#define INTB IRQ_IQ80331_INTB
#define INTC IRQ_IQ80331_INTC
#define INTD IRQ_IQ80331_INTD
//#define INTE IRQ_IQ80331_I82544
static inline int __init
iq80331_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
{
static int pci_irq_table[][4] = {
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{INTB, INTC, INTD, INTA}, /* PCI-X Slot */
{INTC, INTC, INTC, INTC}, /* GigE */
};
BUG_ON(pin < 1 || pin > 4);
return PCI_IRQ_TABLE_LOOKUP(1, 7);
}
static struct hw_pci iq80331_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iop3xx_pci_setup,
.scan = iop3xx_pci_scan_bus,
.preinit = iop3xx_pci_preinit,
.map_irq = iq80331_map_irq
};
static int __init iq80331_pci_init(void)
{
if (machine_is_iq80331())
pci_common_init(&iq80331_pci);
return 0;
}
subsys_initcall(iq80331_pci_init);
arch/arm/mach-iop33x/iq80331.c 0 → 100644
View file @ c680b77e
/*
* arch/arm/mach-iop33x/iq80331.c
*
* Board support code for the Intel IQ80331 platform.
*
* Author: Dave Jiang <dave.jiang@intel.com>
* Copyright (C) 2003 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/pci.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
/*
* IQ80331 timer tick configuration.
*/
static void __init iq80331_timer_init(void)
{
/* D-Step parts run at a higher internal bus frequency */
if (*IOP3XX_ATURID >= 0xa)
iop3xx_init_time(333000000);
else
iop3xx_init_time(266000000);
}
static struct sys_timer iq80331_timer = {
.init = iq80331_timer_init,
.offset = iop3xx_gettimeoffset,
};
/*
* IQ80331 PCI.
*/
static inline int __init
iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
if (slot == 1 && pin == 1) {
/* PCI-X Slot INTA */
irq = IRQ_IOP331_XINT1;
} else if (slot == 1 && pin == 2) {
/* PCI-X Slot INTB */
irq = IRQ_IOP331_XINT2;
} else if (slot == 1 && pin == 3) {
/* PCI-X Slot INTC */
irq = IRQ_IOP331_XINT3;
} else if (slot == 1 && pin == 4) {
/* PCI-X Slot INTD */
irq = IRQ_IOP331_XINT0;
} else if (slot == 2) {
/* GigE */
irq = IRQ_IOP331_XINT2;
} else {
printk(KERN_ERR "iq80331_pci_map_irq() called for unknown "
"device PCI:%d:%d:%d\n", dev->bus->number,
PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
irq = -1;
}
return irq;
}
static struct hw_pci iq80331_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
.scan = iop3xx_pci_scan_bus,
.map_irq = iq80331_pci_map_irq,
};
static int __init iq80331_pci_init(void)
{
if (machine_is_iq80331())
pci_common_init(&iq80331_pci);
return 0;
}
subsys_initcall(iq80331_pci_init);
/*
* IQ80331 machine initialisation.
*/
static struct physmap_flash_data iq80331_flash_data = {
.width = 1,
};
static struct resource iq80331_flash_resource = {
.start = 0xc0000000,
.end = 0xc07fffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device iq80331_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &iq80331_flash_data,
},
.num_resources = 1,
.resource = &iq80331_flash_resource,
};
static void __init iq80331_init_machine(void)
{
platform_device_register(&iop3xx_i2c0_device);
platform_device_register(&iop3xx_i2c1_device);
platform_device_register(&iop33x_uart0_device);
platform_device_register(&iop33x_uart1_device);
platform_device_register(&iq80331_flash_device);
}
MACHINE_START(IQ80331, "Intel IQ80331")
/* Maintainer: Intel Corp. */
.phys_io = 0xfefff000,
.io_pg_offst = ((0xfffff000) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.map_io = iop3xx_map_io,
.init_irq = iop331_init_irq,
.timer = &iq80331_timer,
.init_machine = iq80331_init_machine,
MACHINE_END
arch/arm/mach-iop33x/iq80332-pci.c deleted 100644 → 0
View file @ 7412b10f
/*
* arch/arm/mach-iop33x/iq80332-pci.c
*
* PCI support for the Intel IQ80332 reference board
*
* Author: Dave Jiang <dave.jiang@intel.com>
* Copyright (C) 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
/*
* The following macro is used to lookup irqs in a standard table
* format for those systems that do not already have PCI
* interrupts properly routed. We assume 1 <= pin <= 4
*/
#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
({ int _ctl_ = -1; \
unsigned int _idsel = idsel - minid; \
if (_idsel <= maxid) \
_ctl_ = pci_irq_table[_idsel][pin-1]; \
_ctl_; })
#define INTA IRQ_IQ80332_INTA
#define INTB IRQ_IQ80332_INTB
#define INTC IRQ_IQ80332_INTC
#define INTD IRQ_IQ80332_INTD
//#define INTE IRQ_IQ80332_I82544
static inline int __init
iq80332_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
{
static int pci_irq_table[][8] = {
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{-1, -1, -1, -1},
{-1, -1, -1, -1},
{-1, -1, -1, -1},
{INTA, INTB, INTC, INTD}, /* PCI-X Slot */
{-1, -1, -1, -1},
{INTC, INTC, INTC, INTC}, /* GigE */
{-1, -1, -1, -1},
{-1, -1, -1, -1},
};
BUG_ON(pin < 1 || pin > 4);
return PCI_IRQ_TABLE_LOOKUP(1, 7);
}
static struct hw_pci iq80332_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iop3xx_pci_setup,
.scan = iop3xx_pci_scan_bus,
.preinit = iop3xx_pci_preinit,
.map_irq = iq80332_map_irq
};
static int __init iq80332_pci_init(void)
{
if (machine_is_iq80332())
pci_common_init(&iq80332_pci);
return 0;
}
subsys_initcall(iq80332_pci_init);
arch/arm/mach-iop33x/iq80332.c 0 → 100644
View file @ c680b77e
/*
* arch/arm/mach-iop33x/iq80332.c
*
* Board support code for the Intel IQ80332 platform.
*
* Author: Dave Jiang <dave.jiang@intel.com>
* Copyright (C) 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/pci.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
/*
* IQ80332 timer tick configuration.
*/
static void __init iq80332_timer_init(void)
{
/* D-Step parts and the iop333 run at a higher internal bus frequency */
if (*IOP3XX_ATURID >= 0xa || *IOP3XX_ATUDID == 0x374)
iop3xx_init_time(333000000);
else
iop3xx_init_time(266000000);
}
static struct sys_timer iq80332_timer = {
.init = iq80332_timer_init,
.offset = iop3xx_gettimeoffset,
};
/*
* IQ80332 PCI.
*/
static inline int __init
iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
if (slot == 4 && pin == 1) {
/* PCI-X Slot INTA */
irq = IRQ_IOP331_XINT0;
} else if (slot == 4 && pin == 2) {
/* PCI-X Slot INTB */
irq = IRQ_IOP331_XINT1;
} else if (slot == 4 && pin == 3) {
/* PCI-X Slot INTC */
irq = IRQ_IOP331_XINT2;
} else if (slot == 4 && pin == 4) {
/* PCI-X Slot INTD */
irq = IRQ_IOP331_XINT3;
} else if (slot == 6) {
/* GigE */
irq = IRQ_IOP331_XINT2;
} else {
printk(KERN_ERR "iq80332_pci_map_irq() called for unknown "
"device PCI:%d:%d:%d\n", dev->bus->number,
PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
irq = -1;
}
return irq;
}
static struct hw_pci iq80332_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
.scan = iop3xx_pci_scan_bus,
.map_irq = iq80332_pci_map_irq,
};
static int __init iq80332_pci_init(void)
{
if (machine_is_iq80332())
pci_common_init(&iq80332_pci);
return 0;
}
subsys_initcall(iq80332_pci_init);
/*
* IQ80332 machine initialisation.
*/
static struct physmap_flash_data iq80332_flash_data = {
.width = 1,
};
static struct resource iq80332_flash_resource = {
.start = 0xc0000000,
.end = 0xc07fffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device iq80332_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &iq80332_flash_data,
},
.num_resources = 1,
.resource = &iq80332_flash_resource,
};
static void __init iq80332_init_machine(void)
{
platform_device_register(&iop3xx_i2c0_device);
platform_device_register(&iop3xx_i2c1_device);
platform_device_register(&iop33x_uart0_device);
platform_device_register(&iop33x_uart1_device);
platform_device_register(&iq80332_flash_device);
}
MACHINE_START(IQ80332, "Intel IQ80332")
/* Maintainer: Intel Corp. */
.phys_io = 0xfefff000,
.io_pg_offst = ((0xfffff000) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.map_io = iop3xx_map_io,
.init_irq = iop331_init_irq,
.timer = &iq80332_timer,
.init_machine = iq80332_init_machine,
MACHINE_END
arch/arm/mach-iop33x/setup.c deleted 100644 → 0
View file @ 7412b10f
/*
* linux/arch/arm/mach-iop33x/setup.c
*
* Author: Dave Jiang (dave.jiang@intel.com)
* Copyright (C) 2004 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/major.h>
#include <linux/fs.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <asm/system.h>
#include <asm/memory.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/hardware/iop3xx.h>
#define IOP331_UART_XTAL 33334000
static struct resource iop33x_uart0_resources[] = {
[0] = {
.start = IOP331_UART0_PHYS,
.end = IOP331_UART0_PHYS + 0x3f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP331_UART0,
.end = IRQ_IOP331_UART0,
.flags = IORESOURCE_IRQ
}
};
static struct resource iop33x_uart1_resources[] = {
[0] = {
.start = IOP331_UART1_PHYS,
.end = IOP331_UART1_PHYS + 0x3f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP331_UART1,
.end = IRQ_IOP331_UART1,
.flags = IORESOURCE_IRQ
}
};
static struct plat_serial8250_port iop33x_uart0_data[] = {
{
.membase = (char*)(IOP331_UART0_VIRT),
.mapbase = (IOP331_UART0_PHYS),
.irq = IRQ_IOP331_UART0,
.uartclk = IOP331_UART_XTAL,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_SKIP_TEST,
},
{ },
};
static struct plat_serial8250_port iop33x_uart1_data[] = {
{
.membase = (char*)(IOP331_UART1_VIRT),
.mapbase = (IOP331_UART1_PHYS),
.irq = IRQ_IOP331_UART1,
.uartclk = IOP331_UART_XTAL,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_SKIP_TEST,
},
{ },
};
static struct platform_device iop33x_uart0 = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev.platform_data = iop33x_uart0_data,
.num_resources = 2,
.resource = iop33x_uart0_resources,
};
static struct platform_device iop33x_uart1 = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM1,
.dev.platform_data = iop33x_uart1_data,
.num_resources = 2,
.resource = iop33x_uart1_resources,
};
static struct platform_device *iop33x_devices[] __initdata = {
&iop33x_uart0,
&iop33x_uart1,
};
void __init iop33x_init(void)
{
if(iop_is_331())
{
platform_add_devices(iop33x_devices,
ARRAY_SIZE(iop33x_devices));
}
platform_device_register(&iop3xx_i2c0_device);
platform_device_register(&iop3xx_i2c1_device);
}
#ifdef CONFIG_ARCH_IOP33X
extern void iop331_init_irq(void);
#endif
static void __init iop3xx_timer_init(void)
{
iop3xx_init_time(IOP331_TICK_RATE);
}
struct sys_timer iop331_timer = {
.init = iop3xx_timer_init,
.offset = iop3xx_gettimeoffset,
};
#if defined(CONFIG_ARCH_IQ80331)
MACHINE_START(IQ80331, "Intel IQ80331")
/* Maintainer: Intel Corp. */
.phys_io = 0xfefff000,
.io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, // virtual, physical
.map_io = iop3xx_map_io,
.init_irq = iop331_init_irq,
.timer = &iop331_timer,
.boot_params = 0x0100,
.init_machine = iop33x_init,
MACHINE_END
#elif defined(CONFIG_MACH_IQ80332)
MACHINE_START(IQ80332, "Intel IQ80332")
/* Maintainer: Intel Corp. */
.phys_io = 0xfefff000,
.io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, // virtual, physical
.map_io = iop3xx_map_io,
.init_irq = iop331_init_irq,
.timer = &iop331_timer,
.boot_params = 0x0100,
.init_machine = iop33x_init,
MACHINE_END
#else
#error No machine descriptor defined for this IOP3XX implementation
#endif
arch/arm/mach-iop33x/uart.c 0 → 100644
View file @ c680b77e
/*
* linux/arch/arm/mach-iop33x/uart.c
*
* Author: Dave Jiang (dave.jiang@intel.com)
* Copyright (C) 2004 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/major.h>
#include <linux/fs.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <asm/system.h>
#include <asm/memory.h>
#include <asm/hardware.h>
#include <asm/hardware/iop3xx.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#define IOP331_UART_XTAL 33334000
static struct plat_serial8250_port iop33x_uart0_data[] = {
{
.membase = (char *)IOP331_UART0_VIRT,
.mapbase = IOP331_UART0_PHYS,
.irq = IRQ_IOP331_UART0,
.uartclk = IOP331_UART_XTAL,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_SKIP_TEST,
},
{ },
};
static struct resource iop33x_uart0_resources[] = {
[0] = {
.start = IOP331_UART0_PHYS,
.end = IOP331_UART0_PHYS + 0x3f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP331_UART0,
.end = IRQ_IOP331_UART0,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device iop33x_uart0_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = iop33x_uart0_data,
},
.num_resources = 2,
.resource = iop33x_uart0_resources,
};
static struct resource iop33x_uart1_resources[] = {
[0] = {
.start = IOP331_UART1_PHYS,
.end = IOP331_UART1_PHYS + 0x3f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP331_UART1,
.end = IRQ_IOP331_UART1,
.flags = IORESOURCE_IRQ,
},
};
static struct plat_serial8250_port iop33x_uart1_data[] = {
{
.membase = (char *)IOP331_UART1_VIRT,
.mapbase = IOP331_UART1_PHYS,
.irq = IRQ_IOP331_UART1,
.uartclk = IOP331_UART_XTAL,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_SKIP_TEST,
},
{ },
};
struct platform_device iop33x_uart1_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM1,
.dev = {
.platform_data = iop33x_uart1_data,
},
.num_resources = 2,
.resource = iop33x_uart1_resources,
};
include/asm-arm/arch-iop32x/iop321.h
View file @ c680b77e
...@@ -150,18 +150,6 @@ ...@@ -150,18 +150,6 @@
#define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8) #define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8)
#define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC) #define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC)
/* Timers */
#ifdef CONFIG_ARCH_IQ80321
#define IOP321_TICK_RATE 200000000 /* 200 MHz clock */
#elif defined(CONFIG_ARCH_IQ31244)
#define IOP321_TICK_RATE 198000000 /* 33.000 MHz crystal */
#endif
#ifdef CONFIG_ARCH_EP80219
#undef IOP321_TICK_RATE
#define IOP321_TICK_RATE 200000000 /* 33.333333 Mhz crystal */
#endif
/* Application accelerator unit 0x00000800 - 0x000008FF */ /* Application accelerator unit 0x00000800 - 0x000008FF */
#define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800) #define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800)
#define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804) #define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804)
......
include/asm-arm/arch-iop32x/iq31244.h
View file @ c680b77e
...@@ -7,18 +7,11 @@ ...@@ -7,18 +7,11 @@
#ifndef _IQ31244_H_ #ifndef _IQ31244_H_
#define _IQ31244_H_ #define _IQ31244_H_
#define IQ31244_FLASHBASE 0xf0000000 /* Flash */
#define IQ31244_FLASHSIZE 0x00800000
#define IQ31244_FLASHWIDTH 2
#define IQ31244_UART 0xfe800000 /* UART #1 */ #define IQ31244_UART 0xfe800000 /* UART #1 */
#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */ #define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */
#define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ #define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */
#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ #define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */ #define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */
#ifndef __ASSEMBLY__
extern void iq31244_map_io(void);
#endif
#endif // _IQ31244_H_ #endif // _IQ31244_H_
include/asm-arm/arch-iop32x/iq80321.h
View file @ c680b77e
...@@ -7,18 +7,11 @@ ...@@ -7,18 +7,11 @@
#ifndef _IQ80321_H_ #ifndef _IQ80321_H_
#define _IQ80321_H_ #define _IQ80321_H_
#define IQ80321_FLASHBASE 0xf0000000 /* Flash */
#define IQ80321_FLASHSIZE 0x00800000
#define IQ80321_FLASHWIDTH 1
#define IQ80321_UART 0xfe800000 /* UART #1 */ #define IQ80321_UART 0xfe800000 /* UART #1 */
#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */ #define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */
#define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ #define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */
#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ #define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */ #define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */
#ifndef __ASSEMBLY__
extern void iq80321_map_io(void);
#endif
#endif // _IQ80321_H_ #endif // _IQ80321_H_
include/asm-arm/arch-iop32x/irqs.h
View file @ c680b77e
...@@ -47,42 +47,4 @@ ...@@ -47,42 +47,4 @@
#define NR_IRQS 32 #define NR_IRQS 32
/*
* Interrupts available on the IQ80321 board
*/
/*
* On board devices
*/
#define IRQ_IQ80321_I82544 IRQ_IOP321_XINT0
#define IRQ_IQ80321_UART IRQ_IOP321_XINT1
/*
* PCI interrupts
*/
#define IRQ_IQ80321_INTA IRQ_IOP321_XINT0
#define IRQ_IQ80321_INTB IRQ_IOP321_XINT1
#define IRQ_IQ80321_INTC IRQ_IOP321_XINT2
#define IRQ_IQ80321_INTD IRQ_IOP321_XINT3
/*
* Interrupts on the IQ31244 board
*/
/*
* On board devices
*/
#define IRQ_IQ31244_UART IRQ_IOP321_XINT1
#define IRQ_IQ31244_I82546 IRQ_IOP321_XINT0
#define IRQ_IQ31244_SATA IRQ_IOP321_XINT2
#define IRQ_IQ31244_PCIX_SLOT IRQ_IOP321_XINT3
/*
* PCI interrupts
*/
#define IRQ_IQ31244_INTA IRQ_IOP321_XINT0
#define IRQ_IQ31244_INTB IRQ_IOP321_XINT1
#define IRQ_IQ31244_INTC IRQ_IOP321_XINT2
#define IRQ_IQ31244_INTD IRQ_IOP321_XINT3
#endif // _IRQ_H_ #endif // _IRQ_H_
include/asm-arm/arch-iop33x/hardware.h
View file @ c680b77e
...@@ -22,6 +22,11 @@ ...@@ -22,6 +22,11 @@
#define PCIBIOS_MIN_IO 0x00000000 #define PCIBIOS_MIN_IO 0x00000000
#define PCIBIOS_MIN_MEM 0x00000000 #define PCIBIOS_MIN_MEM 0x00000000
#ifndef __ASSEMBLY__
extern struct platform_device iop33x_uart0_device;
extern struct platform_device iop33x_uart1_device;
#endif
/* /*
* Generic chipset bits * Generic chipset bits
......
include/asm-arm/arch-iop33x/iop331.h
View file @ c680b77e
...@@ -136,16 +136,6 @@ ...@@ -136,16 +136,6 @@
#define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC) #define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC)
/* Timers */
#if defined(CONFIG_ARCH_IOP33X)
#define IOP331_TICK_RATE 266000000 /* 266 MHz IB clock */
#endif
#if defined(CONFIG_IOP331_STEPD) || defined(CONFIG_ARCH_IQ80333)
#undef IOP331_TICK_RATE
#define IOP331_TICK_RATE 333000000 /* 333 Mhz IB clock */
#endif
/* Application accelerator unit 0x00000800 - 0x000008FF */ /* Application accelerator unit 0x00000800 - 0x000008FF */
#define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800) #define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800)
#define IOP331_AAU_ASR (volatile u32 *)IOP331_REG_ADDR(0x00000804) #define IOP331_AAU_ASR (volatile u32 *)IOP331_REG_ADDR(0x00000804)
......
include/asm-arm/arch-iop33x/iq80331.h
View file @ c680b77e
...@@ -7,17 +7,10 @@ ...@@ -7,17 +7,10 @@
#ifndef _IQ80331_H_ #ifndef _IQ80331_H_
#define _IQ80331_H_ #define _IQ80331_H_
#define IQ80331_FLASHBASE 0xc0000000 /* Flash */
#define IQ80331_FLASHSIZE 0x00800000
#define IQ80331_FLASHWIDTH 1
#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */ #define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */
#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ #define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */ #define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */
#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */ #define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */
#ifndef __ASSEMBLY__
extern void iq80331_map_io(void);
#endif
#endif // _IQ80331_H_ #endif // _IQ80331_H_
include/asm-arm/arch-iop33x/iq80332.h
View file @ c680b77e
...@@ -7,17 +7,10 @@ ...@@ -7,17 +7,10 @@
#ifndef _IQ80332_H_ #ifndef _IQ80332_H_
#define _IQ80332_H_ #define _IQ80332_H_
#define IQ80332_FLASHBASE 0xc0000000 /* Flash */
#define IQ80332_FLASHSIZE 0x00800000
#define IQ80332_FLASHWIDTH 1
#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */ #define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */
#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ #define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */ #define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */
#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */ #define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */
#ifndef __ASSEMBLY__
extern void iq80332_map_io(void);
#endif
#endif // _IQ80332_H_ #endif // _IQ80332_H_
include/asm-arm/arch-iop33x/irqs.h
View file @ c680b77e
...@@ -57,42 +57,4 @@ ...@@ -57,42 +57,4 @@
#define NR_IRQS 64 #define NR_IRQS 64
/*
* Interrupts available on the IQ80331 board
*/
/*
* On board devices
*/
#define IRQ_IQ80331_I82544 IRQ_IOP331_XINT0
#define IRQ_IQ80331_UART0 IRQ_IOP331_UART0
#define IRQ_IQ80331_UART1 IRQ_IOP331_UART1
/*
* PCI interrupts
*/
#define IRQ_IQ80331_INTA IRQ_IOP331_XINT0
#define IRQ_IQ80331_INTB IRQ_IOP331_XINT1
#define IRQ_IQ80331_INTC IRQ_IOP331_XINT2
#define IRQ_IQ80331_INTD IRQ_IOP331_XINT3
/*
* Interrupts available on the IQ80332 board
*/
/*
* On board devices
*/
#define IRQ_IQ80332_I82544 IRQ_IOP331_XINT0
#define IRQ_IQ80332_UART0 IRQ_IOP331_UART0
#define IRQ_IQ80332_UART1 IRQ_IOP331_UART1
/*
* PCI interrupts
*/
#define IRQ_IQ80332_INTA IRQ_IOP331_XINT0
#define IRQ_IQ80332_INTB IRQ_IOP331_XINT1
#define IRQ_IQ80332_INTC IRQ_IOP331_XINT2
#define IRQ_IQ80332_INTD IRQ_IOP331_XINT3
#endif // _IRQ_H_ #endif // _IRQ_H_
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