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Commit c7e86e34 authored by Nathanael Nerode's avatar Nathanael Nerode Committed by David S. Miller
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dgrs: remove from build, config, and maintainer list 

Stop building and configuring driver for Digi RightSwitch, which was
never actually sold to anyone, and remove it from MAINTAINERS.

In response to an investigation into the firmware of the "Digi Rightswitch"
driver, Andres Salomon discovered:
>
> Dear Andres:
>
> After further research, we found that this product was killed in place
> and never reached the market.  We would like to request that this not be
> included.

Since the product never reached market, clearly nobody is using this orphaned
driver.
Signed-off-by: default avatarNathanael Nerode <neroden@gcc.gnu.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jeff Garzik <jeff@garzik.org>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 928773c2
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Documentation/networking/dgrs.txt deleted 100644 → 0
View file @ 928773c2
The Digi International RightSwitch SE-X (dgrs) Device Driver
This is a Linux driver for the Digi International RightSwitch SE-X
EISA and PCI boards. These are 4 (EISA) or 6 (PCI) port Ethernet
switches and a NIC combined into a single board. This driver can
be compiled into the kernel statically or as a loadable module.
There is also a companion management tool, called "xrightswitch".
The management tool lets you watch the performance graphically,
as well as set the SNMP agent IP and IPX addresses, IEEE Spanning
Tree, and Aging time. These can also be set from the command line
when the driver is loaded. The driver command line options are:
debug=NNN Debug printing level
dma=0/1 Disable/Enable DMA on PCI card
spantree=0/1 Disable/Enable IEEE spanning tree
hashexpire=NNN Change address aging time (default 300 seconds)
ipaddr=A,B,C,D Set SNMP agent IP address i.e. 199,86,8,221
iptrap=A,B,C,D Set SNMP agent IP trap address i.e. 199,86,8,221
ipxnet=NNN Set SNMP agent IPX network number
nicmode=0/1 Disable/Enable multiple NIC mode
There is also a tool for setting up input and output packet filters
on each port, called "dgrsfilt".
Both the management tool and the filtering tool are available
separately from the following FTP site:
ftp://ftp.dgii.com/drivers/rightswitch/linux/
When nicmode=1, the board and driver operate as 4 or 6 individual
NIC ports (eth0...eth5) instead of as a switch. All switching
functions are disabled. In the future, the board firmware may include
a routing cache when in this mode.
Copyright 1995-1996 Digi International Inc.
This software may be used and distributed according to the terms
of the GNU General Public License, incorporated herein by reference.
For information on purchasing a RightSwitch SE-4 or SE-6
board, please contact Digi's sales department at 1-612-912-3444
or 1-800-DIGIBRD. Outside the U.S., please check our Web page at:
http://www.dgii.com
for sales offices worldwide. Tech support is also available through
the channels listed on the Web site, although as long as I am
employed on networking products at Digi I will be happy to provide
any bug fixes that may be needed.
-Rick Richardson, rick@dgii.com
MAINTAINERS
View file @ c7e86e34
......@@ -1274,12 +1274,6 @@ L: Eng.Linux@digi.com
W: http://www.digi.com
S: Orphaned
DIGI RIGHTSWITCH NETWORK DRIVER
P: Rick Richardson
L: netdev@vger.kernel.org
W: http://www.digi.com
S: Orphaned
DIRECTORY NOTIFICATION
P: Stephen Rothwell
M: sfr@canb.auug.org.au
......
drivers/net/Kconfig
View file @ c7e86e34
......@@ -1459,21 +1459,6 @@ config TC35815
depends on NET_PCI && PCI && MIPS
select MII
config DGRS
tristate "Digi Intl. RightSwitch SE-X support"
depends on NET_PCI && (PCI || EISA)
---help---
This is support for the Digi International RightSwitch series of
PCI/EISA Ethernet switch cards. These include the SE-4 and the SE-6
models. If you have a network card of this type, say Y and read the
Ethernet-HOWTO, available from
<http://www.tldp.org/docs.html#howto>. More specific
information is contained in <file:Documentation/networking/dgrs.txt>.
To compile this driver as a module, choose M here and read
<file:Documentation/networking/net-modules.txt>. The module
will be called dgrs.
config EEPRO100
tristate "EtherExpressPro/100 support (eepro100, original Becker driver)"
depends on NET_PCI && PCI
......
drivers/net/Makefile
View file @ c7e86e34
......@@ -44,7 +44,6 @@ obj-$(CONFIG_SUNVNET) += sunvnet.o
obj-$(CONFIG_MACE) += mace.o
obj-$(CONFIG_BMAC) += bmac.o
obj-$(CONFIG_DGRS) += dgrs.o
obj-$(CONFIG_VORTEX) += 3c59x.o
obj-$(CONFIG_TYPHOON) += typhoon.o
obj-$(CONFIG_NE2K_PCI) += ne2k-pci.o 8390.o
......
drivers/net/dgrs.c deleted 100644 → 0
View file @ 928773c2
This diff is collapsed.
drivers/net/dgrs.h deleted 100644 → 0
View file @ 928773c2
/*
* ioctl's for the Digi Intl. RightSwitch
*
* These network driver ioctl's are a bit obtuse compared to the usual
* ioctl's for a "normal" device driver. Hey, I didn't invent it.
*
* Typical use:
*
* struct ifreq ifr;
* DGRS_IOCTL ioc;
* int x;
*
* strcpy(ifr.ifr_name, "eth1");
* ifr.ifr_data = (caddr_t) &ioc;
* ioc.cmd = DGRS_GETMEM;
* ioc.len = sizeof(x);
* ioc.data = (caddr_t) &x;
* rc = ioctl(fd, DGRSIOCTL, &ifr);
* printf("rc=%d mem=%x\n", rc, x);
*
*/
#include <linux/sockios.h>
#define DGRSIOCTL SIOCDEVPRIVATE
typedef struct dgrs_ioctl {
unsigned short cmd; /* Command to run */
unsigned short len; /* Length of the data buffer */
unsigned char __user *data; /* Pointer to the data buffer */
unsigned short port; /* port number for command, if needed */
unsigned short filter; /* filter number for command, if needed */
} DGRS_IOCTL;
/*
* Commands for the driver
*/
#define DGRS_GETMEM 0x01 /* Get the dual port memory address */
#define DGRS_SETFILTER 0x02 /* Set a filter */
drivers/net/dgrs_asstruct.h deleted 100644 → 0
View file @ 928773c2
/*
* For declaring structures shared with assembly routines
*
* $Id: asstruct.h,v 1.1.1.1 1994/10/23 05:08:32 rick Exp $
*/
#ifdef ASSEMBLER
# define MO(t,a) (a)
# define VMO(t,a) (a)
# define BEGIN_STRUCT(x) _Off=0
# define S1A(t,x,n) _Off=(_Off+0)&~0; x=_Off; _Off=_Off+(1*n)
# define S2A(t,x,n) _Off=(_Off+1)&~1; x=_Off; _Off=_Off+(2*n)
# define S4A(t,x,n) _Off=(_Off+3)&~3; x=_Off; _Off=_Off+(4*n)
# define WORD(x) _Off=(_Off+3)&~3; x=_Off; _Off=_Off+4
# define WORDA(x,n) _Off=(_Off+3)&~3; x=_Off; _Off=_Off+(4*n)
# define VWORD(x) _Off=(_Off+3)&~3; x=_Off; _Off=_Off+4
# define S1(t,x) _Off=(_Off+0)&~0; x=_Off; _Off=_Off+1
# define S2(t,x) _Off=(_Off+1)&~1; x=_Off; _Off=_Off+2
# define S4(t,x) _Off=(_Off+3)&~3; x=_Off; _Off=_Off+4
# define END_STRUCT(x) _Off=(_Off+3)&~3; x=_Off
#else /* C */
#define VMO(t,a) (*(volatile t *)(a))
# define BEGIN_STRUCT(x) struct x {
# define S1(t,x) t x ;
# define S1A(t,x,n) t x[n] ;
# define S2(t,x) t x ;
# define S2A(t,x,n) t x[n] ;
# define S4(t,x) t x ;
# define S4A(t,x,n) t x[n] ;
# define END_STRUCT(x) } ;
#endif
drivers/net/dgrs_bcomm.h deleted 100644 → 0
View file @ 928773c2
/*
* The bios low-memory structure
*
* Some of the variables in here can be used to set parameters that
* are stored in NVRAM and will retain their old values the next time
* the card is brought up. To use the values stored in NVRAM, the
* parameter should be set to "all ones". This tells the firmware to
* use the NVRAM value or a suitable default. The value that is used
* will be stored back into this structure by the firmware. If the
* value of the variable is not "all ones", then that value will be
* used and will be stored into NVRAM if it isn't already there.
* The variables this applies to are the following:
* Variable Set to: Gets default of:
* bc_hashexpire -1 300 (5 minutes)
* bc_spantree -1 1 (spanning tree on)
* bc_ipaddr FF:FF:FF:FF 0 (no SNMP IP address)
* bc_ipxnet FF:FF:FF:FF 0 (no SNMP IPX net)
* bc_iptrap FF:FF:FF:FF 0 (no SNMP IP trap address)
*
* Some variables MUST have their value set after the firmware
* is loaded onto the board, but before the processor is released.
* These are:
* bc_host 0 means no host "port", run as standalone switch.
* 1 means run as a switch, with a host port. (normal)
* 2 means run as multiple NICs, not as a switch.
* -1 means run in diagnostics mode.
* bc_nowait
* bc_hostarea_len
* bc_filter_len
*
*/
BEGIN_STRUCT(bios_comm)
S4(ulong, bc_intflag) /* Count of all interrupts */
S4(ulong, bc_lbolt) /* Count of timer interrupts */
S4(ulong, bc_maincnt) /* Count of main loops */
S4(ulong, bc_hashcnt) /* Count of entries in hash table */
S4A(ulong, bc_cnt, 8) /* Misc counters, for debugging */
S4A(ulong, bc_flag, 8) /* Misc flags, for debugging */
S4(ulong, bc_memsize) /* Size of memory */
S4(ulong, bc_dcache) /* Size of working dcache */
S4(ulong, bc_icache) /* Size of working icache */
S4(long, bc_status) /* Firmware status */
S1A(char, bc_file, 8) /* File name of assertion failure */
S4(ulong, bc_line) /* Line # of assertion failure */
S4(uchar *, bc_ramstart)
S4(uchar *, bc_ramend)
S4(uchar *, bc_heapstart) /* Start of heap (end of loaded memory) */
S4(uchar *, bc_heapend) /* End of heap */
/* Configurable Parameters */
S4(long, bc_host) /* 1=Host Port, 0=No Host Port, -1=Test Mode */
S4(long, bc_nowait) /* Don't wait for 2host circ buffer to empty*/
S4(long, bc_150ohm) /* 0 == 100 ohm UTP, 1 == 150 ohm STP */
S4(long, bc_squelch) /* 0 == normal squelch, 1 == reduced squelch */
S4(ulong, bc_hashexpire) /* Expiry time in seconds for hash table */
S4(long, bc_spantree) /* 1 == enable IEEE spanning tree */
S2A(ushort, bc_eaddr, 3) /* New ether address */
S2(ushort, bc_dummy1) /* padding for DOS compilers */
/* Various debugging aids */
S4(long, bc_debug) /* Debugging is turned on */
S4(long, bc_spew) /* Spew data on port 4 for bs_spew seconds */
S4(long, bc_spewlen) /* Length of spewed data packets */
S4(long, bc_maxrfd) /* If != 0, max number of RFD's to allocate */
S4(long, bc_maxrbd) /* If != 0, max number of RBD's to allocate */
/* Circular buffers for messages to/from host */
S4(ulong, bc_2host_head)
S4(ulong, bc_2host_tail)
S4(ulong, bc_2host_mask)
S1A(char, bc_2host, 0x200) /* Circ buff to host */
S4(ulong, bc_2idt_head)
S4(ulong, bc_2idt_tail)
S4(ulong, bc_2idt_mask)
S1A(char, bc_2idt, 0x200) /* Circ buff to idt */
/* Pointers to structures for driver access */
S4(uchar *, bc_port) /* pointer to Port[] structures */
S4(long, bc_nports) /* Number of ports */
S4(long, bc_portlen) /* sizeof(PORT) */
S4(uchar *, bc_hash) /* Pointer to hash table */
S4(long, bc_hashlen) /* sizeof(Table) */
/* SNMP agent addresses */
S1A(uchar, bc_ipaddr, 4) /* IP address for SNMP */
S1A(uchar, bc_ipxnet, 4) /* IPX net address for SNMP */
S4(long, bc_nohostintr) /* Do not cause periodic host interrupts */
S4(uchar *, bc_dmaaddr) /* Physical addr of host DMA buf for diags */
S4(ulong, bc_dmalen) /* Length of DMA buffer 0..2048 */
/*
* Board memory allocated on startup for use by host, usually
* for the purposes of creating DMA chain descriptors. The
* "len" must be set before the processor is released. The
* address of the area is returned in bc_hostarea. The area
* is guaranteed to be aligned on a 16 byte boundary.
*/
S4(ulong, bc_hostarea_len) /* RW: Number of bytes to allocate */
S4(uchar *, bc_hostarea) /* RO: Address of allocated memory */
/*
* Variables for communicating filters into the board
*/
S4(ulong *, bc_filter_area) /* RO: Space to put filter into */
S4(ulong, bc_filter_area_len) /* RO: Length of area, in bytes */
S4(long, bc_filter_cmd) /* RW: Filter command, see below */
S4(ulong, bc_filter_len) /* RW: Actual length of filter */
S4(ulong, bc_filter_port) /* RW: Port # for filter 0..6 */
S4(ulong, bc_filter_num) /* RW: Filter #, 0=input, 1=output */
/* more SNMP agent addresses */
S1A(uchar, bc_iptrap, 4) /* IP address for SNMP */
S4A(long, bc_spare, 2) /* spares */
END_STRUCT(bios_comm)
#define bc VMO(struct bios_comm, 0xa3000100)
/*
* bc_status values
*/
#define BC_INIT 0
#define BC_RUN 100
/*
* bc_host values
*/
#define BC_DIAGS -1
#define BC_SASWITCH 0
#define BC_SWITCH 1
#define BC_MULTINIC 2
/*
* Values for spew (debugging)
*/
#define BC_SPEW_ENABLE 0x80000000
/*
* filter commands
*/
#define BC_FILTER_ERR -1
#define BC_FILTER_OK 0
#define BC_FILTER_SET 1
#define BC_FILTER_CLR 2
drivers/net/dgrs_es4h.h deleted 100644 → 0
View file @ 928773c2
/************************************************************************/
/* */
/* es4h.h: Hardware definition of the ES/4h Ethernet Switch, from */
/* both the host and the 3051's point of view. */
/* NOTE: this name is a misnomer now that there is a PCI */
/* board. Everything that says "es4h" should really be */
/* "se4". But we'll keep the old name for now. */
/* */
/* $Id: es4h.h,v 1.10 1996/08/22 17:16:53 rick Exp $ */
/* */
/************************************************************************/
/************************************************************************/
/* */
/* EISA I/O Registers. These are located at 0x1000 * slot-number */
/* plus the indicated address. I.E. 0x4000-0x4009 for slot 4. */
/* */
/************************************************************************/
#define ES4H_MANUFmsb 0x00 /* Read-only */
#define ES4H_MANUFlsb 0x01 /* Read-only */
# define ES4H_MANUF_CODE 0x1049 /* = "DBI" */
#define ES4H_PRODUCT 0x02 /* Read-only */
# define ES4H_PRODUCT_CODE 0x0A
# define EPC_PRODUCT_CODE 0x03
#define ES4H_REVISION 0x03 /* Read-only */
# define ES4H_REVISION_CODE 0x01
#define ES4H_EC 0x04 /* EISA Control */
# define ES4H_EC_RESET 0x04 /* WO, EISA reset */
# define ES4H_EC_ENABLE 0x01 /* RW, EISA enable - set to */
/* 1 before memory enable */
#define ES4H_PC 0x05 /* Processor Control */
# define ES4H_PC_RESET 0x04 /* RW, 3051 reset */
# define ES4H_PC_INT 0x08 /* WO, assert 3051 intr. 3 */
#define ES4H_MW 0x06 /* Memory Window select and enable */
# define ES4H_MW_ENABLE 0x80 /* WO, enable memory */
# define ES4H_MW_SELECT_MASK 0x1f /* WO, 32k window selected */
#define ES4H_IS 0x07 /* Interrupt, addr select */
# define ES4H_IS_INTMASK 0x07 /* WO, interrupt select */
# define ES4H_IS_INTOFF 0x00 /* No IRQ */
# define ES4H_IS_INT3 0x03 /* IRQ 3 */
# define ES4H_IS_INT5 0x02 /* IRQ 5 */
# define ES4H_IS_INT7 0x01 /* IRQ 7 */
# define ES4H_IS_INT10 0x04 /* IRQ 10 */
# define ES4H_IS_INT11 0x05 /* IRQ 11 */
# define ES4H_IS_INT12 0x06 /* IRQ 12 */
# define ES4H_IS_INT15 0x07 /* IRQ 15 */
# define ES4H_IS_INTACK 0x10 /* WO, interrupt ack */
# define ES4H_IS_INTPEND 0x10 /* RO, interrupt pending */
# define ES4H_IS_LINEAR 0x40 /* WO, no memory windowing */
# define ES4H_IS_AS15 0x80 /* RW, address select bit 15 */
#define ES4H_AS_23_16 0x08 /* Address select bits 23-16 */
#define ES4H_AS_31_24 0x09 /* Address select bits 31-24 */
#define ES4H_IO_MAX 0x09 /* Size of I/O space */
/*
* PCI
*/
#define SE6_RESET PLX_USEROUT
/************************************************************************/
/* */
/* 3051 Memory Map */
/* */
/* Note: 3051 has 4K I-cache, 2K D-cache. 1 cycle is 50 nsec. */
/* */
/************************************************************************/
#define SE4_NPORTS 4 /* # of ethernet ports */
#define SE6_NPORTS 6 /* # of ethernet ports */
#define SE_NPORTS 6 /* Max # of ethernet ports */
#define ES4H_RAM_BASE 0x83000000 /* Base address of RAM */
#define ES4H_RAM_SIZE 0x00200000 /* Size of RAM (2MB) */
#define ES4H_RAM_INTBASE 0x83800000 /* Base of int-on-write RAM */
/* a.k.a. PKT RAM */
/* Ethernet controllers */
/* See: i82596.h */
#define ES4H_ETHER0_PORT 0xA2000000
#define ES4H_ETHER0_CMD 0xA2000100
#define ES4H_ETHER1_PORT 0xA2000200
#define ES4H_ETHER1_CMD 0xA2000300
#define ES4H_ETHER2_PORT 0xA2000400
#define ES4H_ETHER2_CMD 0xA2000500
#define ES4H_ETHER3_PORT 0xA2000600
#define ES4H_ETHER3_CMD 0xA2000700
#define ES4H_ETHER4_PORT 0xA2000800 /* RS SE-6 only */
#define ES4H_ETHER4_CMD 0xA2000900 /* RS SE-6 only */
#define ES4H_ETHER5_PORT 0xA2000A00 /* RS SE-6 only */
#define ES4H_ETHER5_CMD 0xA2000B00 /* RS SE-6 only */
#define ES4H_I8254 0xA2040000 /* 82C54 timers */
/* See: i8254.h */
#define SE4_I8254_HZ (23000000/4) /* EISA clock input freq. */
#define SE4_IDT_HZ (46000000) /* EISA CPU freq. */
#define SE6_I8254_HZ (20000000/4) /* PCI clock input freq. */
#define SE6_IDT_HZ (50000000) /* PCI CPU freq. */
#define ES4H_I8254_HZ (23000000/4) /* EISA clock input freq. */
#define ES4H_GPP 0xA2050000 /* General purpose port */
/*
* SE-4 (EISA) GPP bits
*/
# define ES4H_GPP_C0_100 0x0001 /* WO, Chan 0: 100 ohm TP */
# define ES4H_GPP_C0_SQE 0x0002 /* WO, Chan 0: normal squelch */
# define ES4H_GPP_C1_100 0x0004 /* WO, Chan 1: 100 ohm TP */
# define ES4H_GPP_C1_SQE 0x0008 /* WO, Chan 1: normal squelch */
# define ES4H_GPP_C2_100 0x0010 /* WO, Chan 2: 100 ohm TP */
# define ES4H_GPP_C2_SQE 0x0020 /* WO, Chan 2: normal squelch */
# define ES4H_GPP_C3_100 0x0040 /* WO, Chan 3: 100 ohm TP */
# define ES4H_GPP_C3_SQE 0x0080 /* WO, Chan 3: normal squelch */
# define ES4H_GPP_SQE 0x00AA /* WO, All: normal squelch */
# define ES4H_GPP_100 0x0055 /* WO, All: 100 ohm TP */
# define ES4H_GPP_HOSTINT 0x0100 /* RO, cause intr. to host */
/* Hold high > 250 nsec */
# define SE4_GPP_EED 0x0200 /* RW, EEPROM data bit */
# define SE4_GPP_EECS 0x0400 /* RW, EEPROM chip select */
# define SE4_GPP_EECK 0x0800 /* RW, EEPROM clock */
/*
* SE-6 (PCI) GPP bits
*/
# define SE6_GPP_EED 0x0001 /* RW, EEPROM data bit */
# define SE6_GPP_EECS 0x0002 /* RW, EEPROM chip select */
# define SE6_GPP_EECK 0x0004 /* RW, EEPROM clock */
# define SE6_GPP_LINK 0x00fc /* R, Link status LEDs */
#define ES4H_INTVEC 0xA2060000 /* RO: Interrupt Vector */
# define ES4H_IV_DMA0 0x01 /* Chan 0 DMA interrupt */
# define ES4H_IV_PKT0 0x02 /* Chan 0 PKT interrupt */
# define ES4H_IV_DMA1 0x04 /* Chan 1 DMA interrupt */
# define ES4H_IV_PKT1 0x08 /* Chan 1 PKT interrupt */
# define ES4H_IV_DMA2 0x10 /* Chan 2 DMA interrupt */
# define ES4H_IV_PKT2 0x20 /* Chan 2 PKT interrupt */
# define ES4H_IV_DMA3 0x40 /* Chan 3 DMA interrupt */
# define ES4H_IV_PKT3 0x80 /* Chan 3 PKT interrupt */
#define ES4H_INTACK 0xA2060000 /* WO: Interrupt Ack */
# define ES4H_INTACK_8254 0x01 /* Real Time Clock (int 0) */
# define ES4H_INTACK_HOST 0x02 /* Host (int 1) */
# define ES4H_INTACK_PKT0 0x04 /* Chan 0 Pkt (int 2) */
# define ES4H_INTACK_PKT1 0x08 /* Chan 1 Pkt (int 3) */
# define ES4H_INTACK_PKT2 0x10 /* Chan 2 Pkt (int 4) */
# define ES4H_INTACK_PKT3 0x20 /* Chan 3 Pkt (int 5) */
#define SE6_PLX 0xA2070000 /* PLX 9060, SE-6 (PCI) only */
/* see plx9060.h */
#define SE6_PCI_VENDOR_ID 0x114F /* Digi PCI vendor ID */
#define SE6_PCI_DEVICE_ID 0x0003 /* RS SE-6 device ID */
#define SE6_PCI_ID ((SE6_PCI_DEVICE_ID<<16) | SE6_PCI_VENDOR_ID)
/*
* IDT Interrupts
*/
#define ES4H_INT_8254 IDT_INT0
#define ES4H_INT_HOST IDT_INT1
#define ES4H_INT_ETHER0 IDT_INT2
#define ES4H_INT_ETHER1 IDT_INT3
#define ES4H_INT_ETHER2 IDT_INT4
#define ES4H_INT_ETHER3 IDT_INT5
/*
* Because there are differences between the SE-4 and the SE-6,
* we assume that the following globals will be set up at init
* time in main.c to containt the appropriate constants from above
*/
extern ushort Gpp; /* Softcopy of GPP register */
extern ushort EEck; /* Clock bit */
extern ushort EEcs; /* CS bit */
extern ushort EEd; /* Data bit */
extern ulong I8254_Hz; /* i8254 input frequency */
extern ulong IDT_Hz; /* IDT CPU frequency */
extern int Nports; /* Number of ethernet controllers */
extern int Nchan; /* Nports+1 */
drivers/net/dgrs_ether.h deleted 100644 → 0
View file @ 928773c2
/*
* A filtering function. There are two filters/port. Filter "0"
* is the input filter, and filter "1" is the output filter.
*/
typedef int (FILTER_FUNC)(uchar *pktp, int pktlen, ulong *scratch, int port);
#define NFILTERS 2
/*
* The per port structure
*/
typedef struct
{
int chan; /* Channel number (0-3) */
ulong portaddr; /* address of 596 port register */
volatile ulong *ca; /* address of 596 chan attention */
ulong intmask; /* Interrupt mask for this port */
ulong intack; /* Ack bit for this port */
uchar ethaddr[6]; /* Ethernet address of this port */
int is_promisc; /* Port is promiscuous */
int debug; /* Debugging turned on */
I596_ISCP *iscpp; /* Uncached ISCP pointer */
I596_SCP *scpp; /* Uncached SCP pointer */
I596_SCB *scbp; /* Uncached SCB pointer */
I596_ISCP iscp;
I596_SCB scb;
/* Command Queue */
I596_CB *cb0;
I596_CB *cbN;
I596_CB *cb_head;
I596_CB *cb_tail;
/* Receive Queue */
I596_RFD *rfd0;
I596_RFD *rfdN;
I596_RFD *rfd_head;
I596_RFD *rfd_tail;
/* Receive Buffers */
I596_RBD *rbd0;
I596_RBD *rbdN;
I596_RBD *rbd_head;
I596_RBD *rbd_tail;
int buf_size; /* Size of an RBD buffer */
int buf_cnt; /* Total RBD's allocated */
/* Rx Statistics */
ulong cnt_rx_cnt; /* Total packets rcvd, good and bad */
ulong cnt_rx_good; /* Total good packets rcvd */
ulong cnt_rx_bad; /* Total of all bad packets rcvd */
/* Subtotals can be gotten from SCB */
ulong cnt_rx_nores; /* No resources */
ulong cnt_rx_bytes; /* Total bytes rcvd */
/* Tx Statistics */
ulong cnt_tx_queued;
ulong cnt_tx_done;
ulong cnt_tx_freed;
ulong cnt_tx_nores; /* No resources */
ulong cnt_tx_bad;
ulong cnt_tx_err_late;
ulong cnt_tx_err_nocrs;
ulong cnt_tx_err_nocts;
ulong cnt_tx_err_under;
ulong cnt_tx_err_maxcol;
ulong cnt_tx_collisions;
/* Special stuff for host */
# define rfd_freed cnt_rx_cnt
ulong rbd_freed;
int host_timer;
/* Added after first beta */
ulong cnt_tx_races; /* Counts race conditions */
int spanstate;
ulong cnt_st_tx; /* send span tree pkts */
ulong cnt_st_fail_tx; /* Failures to send span tree pkts */
ulong cnt_st_fail_rbd;/* Failures to send span tree pkts */
ulong cnt_st_rx; /* rcv span tree pkts */
ulong cnt_st_rx_bad; /* bogus st packets rcvd */
ulong cnt_rx_fwd; /* Rcvd packets that were forwarded */
ulong cnt_rx_mcast; /* Multicast pkts received */
ulong cnt_tx_mcast; /* Multicast pkts transmitted */
ulong cnt_tx_bytes; /* Bytes transmitted */
/*
* Packet filtering
* Filter 0: input filter
* Filter 1: output filter
*/
ulong *filter_space[NFILTERS];
FILTER_FUNC *filter_func[NFILTERS];
ulong filter_cnt[NFILTERS];
ulong filter_len[NFILTERS];
ulong pad[ (512-300) / 4];
} PORT;
/*
* Port[0] is host interface
* Port[1..SE_NPORTS] are external 10 Base T ports. Fewer may be in
* use, depending on whether this is an SE-4 or
* an SE-6.
* Port[SE_NPORTS] Pseudo-port for Spanning tree and SNMP
*/
extern PORT Port[1+SE_NPORTS+1];
extern int Nports; /* Number of genuine ethernet controllers */
extern int Nchan; /* ... plus one for host interface */
extern int FirstChan; /* 0 or 1, depedning on whether host is used */
extern int NumChan; /* 4 or 5 */
/*
* A few globals
*/
extern int IsPromisc;
extern int MultiNicMode;
/*
* Functions
*/
extern void eth_xmit_spew_on(PORT *p, int cnt);
extern void eth_xmit_spew_off(PORT *p);
extern I596_RBD *alloc_rbds(PORT *p, int num);
extern I596_CB * eth_cb_alloc(PORT *p);
drivers/net/dgrs_firmware.c deleted 100644 → 0
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drivers/net/dgrs_i82596.h deleted 100644 → 0
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drivers/net/dgrs_plx9060.h deleted 100644 → 0
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/*
* PLX 9060 PCI Interface chip
*/
/*
* PCI configuration registers, same offset on local and PCI sides,
* but on PCI side, must use PCI BIOS calls to read/write.
*/
#define PCI_PLXREGS_BASE_ADDR 0x10
#define PCI_PLXREGS_IO_ADDR 0x14
#define PCI_SPACE0_BASE_ADDR 0x18
#define PCI_ROM_BASE_ADDR 0x30
# define PCI_ROM_ENABLED 0x00000001
#define PCI_INT_LINE 0x3C
/*
* Registers accessible directly from PCI and local side.
* Offset is from PCI side. Add PLX_LCL_OFFSET for local address.
*/
#define PLX_LCL_OFFSET 0x80 /* Offset of regs from local side */
/*
* Local Configuration Registers
*/
#define PLX_SPACE0_RANGE 0x00 /* Range for PCI to Lcl Addr Space 0 */
#define PLX_SPACE0_BASE_ADDR 0x04 /* Lcl Base address remap */
#define PLX_ROM_RANGE 0x10 /* Range for expansion ROM (DMA) */
#define PLX_ROM_BASE_ADDR 0x14 /* Lcl base address remap for ROM */
#define PLX_BUS_REGION 0x18 /* Bus Region Descriptors */
/*
* Shared Run Time Registers
*/
#define PLX_MBOX0 0x40
#define PLX_MBOX1 0x44
#define PLX_MBOX2 0x48
#define PLX_MBOX3 0x4C
#define PLX_MBOX4 0x50
#define PLX_MBOX5 0x54
#define PLX_MBOX6 0x58
#define PLX_MBOX7 0x5C
#define PLX_PCI2LCL_DOORBELL 0x60
#define PLX_LCL2PCI_DOORBELL 0x64
#define PLX_INT_CSR 0x68 /* Interrupt Control/Status */
# define PLX_LSERR_ENABLE 0x00000001
# define PLX_LSERR_PE 0x00000002
# define PLX_SERR 0x00000004
# undef PLX_UNUSED /* 0x00000008 */
# undef PLX_UNUSED /* 0x00000010 */
# undef PLX_UNUSED /* 0x00000020 */
# undef PLX_UNUSED /* 0x00000040 */
# undef PLX_UNUSED /* 0x00000080 */
# define PLX_PCI_IE 0x00000100
# define PLX_PCI_DOORBELL_IE 0x00000200
# define PLX_PCI_ABORT_IE 0x00000400
# define PLX_PCI_LOCAL_IE 0x00000800
# define PLX_RETRY_ABORT_ENABLE 0x00001000
# define PLX_PCI_DOORBELL_INT 0x00002000
# define PLX_PCI_ABORT_INT 0x00004000
# define PLX_PCI_LOCAL_INT 0x00008000
# define PLX_LCL_IE 0x00010000
# define PLX_LCL_DOORBELL_IE 0x00020000
# define PLX_LCL_DMA0_IE 0x00040000
# define PLX_LCL_DMA1_IE 0x00080000
# define PLX_LCL_DOORBELL_INT 0x00100000
# define PLX_LCL_DMA0_INT 0x00200000
# define PLX_LCL_DMA1_INT 0x00400000
# define PLX_LCL_BIST_INT 0x00800000
# define PLX_BM_DIRECT_ 0x01000000
# define PLX_BM_DMA0_ 0x02000000
# define PLX_BM_DMA1_ 0x04000000
# define PLX_BM_ABORT_ 0x08000000
# undef PLX_UNUSED /* 0x10000000 */
# undef PLX_UNUSED /* 0x20000000 */
# undef PLX_UNUSED /* 0x40000000 */
# undef PLX_UNUSED /* 0x80000000 */
#define PLX_MISC_CSR 0x6c /* EEPROM,PCI,User,Init Control/Status*/
# define PLX_USEROUT 0x00010000
# define PLX_USERIN 0x00020000
# define PLX_EECK 0x01000000
# define PLX_EECS 0x02000000
# define PLX_EEWD 0x04000000
# define PLX_EERD 0x08000000
/*
* DMA registers. Offset is from local side
*/
#define PLX_DMA0_MODE 0x100
# define PLX_DMA_MODE_WIDTH32 0x00000003
# define PLX_DMA_MODE_WAITSTATES(X) ((X)<<2)
# define PLX_DMA_MODE_NOREADY 0x00000000
# define PLX_DMA_MODE_READY 0x00000040
# define PLX_DMA_MODE_NOBTERM 0x00000000
# define PLX_DMA_MODE_BTERM 0x00000080
# define PLX_DMA_MODE_NOBURST 0x00000000
# define PLX_DMA_MODE_BURST 0x00000100
# define PLX_DMA_MODE_NOCHAIN 0x00000000
# define PLX_DMA_MODE_CHAIN 0x00000200
# define PLX_DMA_MODE_DONE_IE 0x00000400
# define PLX_DMA_MODE_ADDR_HOLD 0x00000800
#define PLX_DMA0_PCI_ADDR 0x104
/* non-chaining mode PCI address */
#define PLX_DMA0_LCL_ADDR 0x108
/* non-chaining mode local address */
#define PLX_DMA0_SIZE 0x10C
/* non-chaining mode length */
#define PLX_DMA0_DESCRIPTOR 0x110
# define PLX_DMA_DESC_EOC 0x00000002
# define PLX_DMA_DESC_TC_IE 0x00000004
# define PLX_DMA_DESC_TO_HOST 0x00000008
# define PLX_DMA_DESC_TO_BOARD 0x00000000
# define PLX_DMA_DESC_NEXTADDR 0xFFFFfff0
#define PLX_DMA1_MODE 0x114
#define PLX_DMA1_PCI_ADDR 0x118
#define PLX_DMA1_LCL_ADDR 0x11C
#define PLX_DMA1_SIZE 0x110
#define PLX_DMA1_DESCRIPTOR 0x124
#define PLX_DMA_CSR 0x128
# define PLX_DMA_CSR_0_ENABLE 0x00000001
# define PLX_DMA_CSR_0_START 0x00000002
# define PLX_DMA_CSR_0_ABORT 0x00000004
# define PLX_DMA_CSR_0_CLR_INTR 0x00000008
# define PLX_DMA_CSR_0_DONE 0x00000010
# define PLX_DMA_CSR_1_ENABLE 0x00000100
# define PLX_DMA_CSR_1_START 0x00000200
# define PLX_DMA_CSR_1_ABORT 0x00000400
# define PLX_DMA_CSR_1_CLR_INTR 0x00000800
# define PLX_DMA_CSR_1_DONE 0x00001000
#define PLX_DMA_ARB0 0x12C
# define PLX_DMA_ARB0_LATENCY_T 0x000000FF
# define PLX_DMA_ARB0_PAUSE_T 0x0000FF00
# define PLX_DMA_ARB0_LATENCY_EN 0x00010000
# define PLX_DMA_ARB0_PAUSE_EN 0x00020000
# define PLX_DMA_ARB0_BREQ_EN 0x00040000
# define PLX_DMA_ARB0_PRI 0x00180000
# define PLX_DMA_ARB0_PRI_ROUND 0x00000000
# define PLX_DMA_ARB0_PRI_0 0x00080000
# define PLX_DMA_ARB0_PRI_1 0x00100000
#define PLX_DMA_ARB1 0x130
/* Chan 0: FIFO DEPTH=16 */
# define PLX_DMA_ARB1_0_P2L_LW_TRIG(X) ( ((X)&15) << 0 )
# define PLX_DMA_ARB1_0_L2P_LR_TRIG(X) ( ((X)&15) << 4 )
# define PLX_DMA_ARB1_0_L2P_PW_TRIG(X) ( ((X)&15) << 8 )
# define PLX_DMA_ARB1_0_P2L_PR_TRIG(X) ( ((X)&15) << 12 )
/* Chan 1: FIFO DEPTH=8 */
# define PLX_DMA_ARB1_1_P2L_LW_TRIG(X) ( ((X)& 7) << 16 )
# define PLX_DMA_ARB1_1_L2P_LR_TRIG(X) ( ((X)& 7) << 20 )
# define PLX_DMA_ARB1_1_L2P_PW_TRIG(X) ( ((X)& 7) << 24 )
# define PLX_DMA_ARB1_1_P2L_PR_TRIG(X) ( ((X)& 7) << 28 )
typedef struct _dmachain
{
ulong pciaddr;
ulong lcladdr;
ulong len;
ulong next;
} DMACHAIN;
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