Commit c82baa28 authored by yanyang1's avatar yanyang1 Committed by Alex Deucher

drm/amd/powerplay: add Tonga dpm support (v3)

This implements DPM for tonga.  DPM handles dynamic
clock and voltage scaling.

v2: merge all the patches related with tonga dpm
v3: merge dpm force level fix, cgs display fix, spelling fix
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: default avataryanyang1 <young.yang@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarEric Huang <JinHuiEric.Huang@amd.com>
parent 1060029f
......@@ -2,7 +2,10 @@
subdir-ccflags-y += -Iinclude/drm \
-Idrivers/gpu/drm/amd/powerplay/inc/ \
-Idrivers/gpu/drm/amd/include/asic_reg \
-Idrivers/gpu/drm/amd/include
-Idrivers/gpu/drm/amd/include \
-Idrivers/gpu/drm/amd/powerplay/smumgr\
-Idrivers/gpu/drm/amd/powerplay/hwmgr \
-Idrivers/gpu/drm/amd/powerplay/eventmgr
AMD_PP_PATH = ../powerplay
......
......@@ -4,7 +4,9 @@
HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
hardwaremanager.o pp_acpi.o cz_hwmgr.o \
cz_clockpowergating.o
cz_clockpowergating.o \
tonga_processpptables.o ppatomctrl.o \
tonga_hwmgr.o pppcielanes.o
AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
......
......@@ -28,6 +28,7 @@
#include "power_state.h"
#include "hwmgr.h"
#include "cz_hwmgr.h"
#include "tonga_hwmgr.h"
int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
{
......@@ -53,6 +54,15 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
case AMD_FAMILY_CZ:
cz_hwmgr_init(hwmgr);
break;
case AMD_FAMILY_VI:
switch (hwmgr->chip_id) {
case CHIP_TONGA:
tonga_hwmgr_init(hwmgr);
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
......
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef PP_HWMGR_PPT_H
#define PP_HWMGR_PPT_H
#include "hardwaremanager.h"
#include "smumgr.h"
#include "atom-types.h"
struct phm_ppt_v1_clock_voltage_dependency_record {
uint32_t clk;
uint8_t vddInd;
uint16_t vdd_offset;
uint16_t vddc;
uint16_t vddgfx;
uint16_t vddci;
uint16_t mvdd;
uint8_t phases;
uint8_t cks_enable;
uint8_t cks_voffset;
};
typedef struct phm_ppt_v1_clock_voltage_dependency_record phm_ppt_v1_clock_voltage_dependency_record;
struct phm_ppt_v1_clock_voltage_dependency_table {
uint32_t count; /* Number of entries. */
phm_ppt_v1_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
};
typedef struct phm_ppt_v1_clock_voltage_dependency_table phm_ppt_v1_clock_voltage_dependency_table;
/* Multimedia Clock Voltage Dependency records and table */
struct phm_ppt_v1_mm_clock_voltage_dependency_record {
uint32_t dclk; /* UVD D-clock */
uint32_t vclk; /* UVD V-clock */
uint32_t eclk; /* VCE clock */
uint32_t aclk; /* ACP clock */
uint32_t samclock; /* SAMU clock */
uint8_t vddcInd;
uint16_t vddgfx_offset;
uint16_t vddc;
uint16_t vddgfx;
uint8_t phases;
};
typedef struct phm_ppt_v1_mm_clock_voltage_dependency_record phm_ppt_v1_mm_clock_voltage_dependency_record;
struct phm_ppt_v1_mm_clock_voltage_dependency_table {
uint32_t count; /* Number of entries. */
phm_ppt_v1_mm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
};
typedef struct phm_ppt_v1_mm_clock_voltage_dependency_table phm_ppt_v1_mm_clock_voltage_dependency_table;
struct phm_ppt_v1_voltage_lookup_record {
uint16_t us_calculated;
uint16_t us_vdd; /* Base voltage */
uint16_t us_cac_low;
uint16_t us_cac_mid;
uint16_t us_cac_high;
};
typedef struct phm_ppt_v1_voltage_lookup_record phm_ppt_v1_voltage_lookup_record;
struct phm_ppt_v1_voltage_lookup_table {
uint32_t count;
phm_ppt_v1_voltage_lookup_record entries[1]; /* Dynamically allocate count entries. */
};
typedef struct phm_ppt_v1_voltage_lookup_table phm_ppt_v1_voltage_lookup_table;
/* PCIE records and Table */
struct phm_ppt_v1_pcie_record {
uint8_t gen_speed;
uint8_t lane_width;
};
typedef struct phm_ppt_v1_pcie_record phm_ppt_v1_pcie_record;
struct phm_ppt_v1_pcie_table {
uint32_t count; /* Number of entries. */
phm_ppt_v1_pcie_record entries[1]; /* Dynamically allocate count entries. */
};
typedef struct phm_ppt_v1_pcie_table phm_ppt_v1_pcie_table;
#endif
This diff is collapsed.
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef PP_ATOMVOLTAGECTRL_H
#define PP_ATOMVOLTAGECTRL_H
#include "hwmgr.h"
#define MEM_TYPE_GDDR5 0x50
#define MEM_TYPE_GDDR4 0x40
#define MEM_TYPE_GDDR3 0x30
#define MEM_TYPE_DDR2 0x20
#define MEM_TYPE_GDDR1 0x10
#define MEM_TYPE_DDR3 0xb0
#define MEM_TYPE_MASK 0xF0
/* As returned from PowerConnectorDetectionTable. */
#define PP_ATOM_POWER_BUDGET_DISABLE_OVERDRIVE 0x80
#define PP_ATOM_POWER_BUDGET_SHOW_WARNING 0x40
#define PP_ATOM_POWER_BUDGET_SHOW_WAIVER 0x20
#define PP_ATOM_POWER_POWER_BUDGET_BEHAVIOUR 0x0F
/* New functions for Evergreen and beyond. */
#define PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES 32
struct pp_atomctrl_clock_dividers {
uint32_t pll_post_divider;
uint32_t pll_feedback_divider;
uint32_t pll_ref_divider;
bool enable_post_divider;
};
typedef struct pp_atomctrl_clock_dividers pp_atomctrl_clock_dividers;
union pp_atomctrl_tcipll_fb_divider {
struct {
uint32_t ul_fb_div_frac : 14;
uint32_t ul_fb_div : 12;
uint32_t un_used : 6;
};
uint32_t ul_fb_divider;
};
typedef union pp_atomctrl_tcipll_fb_divider pp_atomctrl_tcipll_fb_divider;
struct pp_atomctrl_clock_dividers_rv730 {
uint32_t pll_post_divider;
pp_atomctrl_tcipll_fb_divider mpll_feedback_divider;
uint32_t pll_ref_divider;
bool enable_post_divider;
bool enable_dithen;
uint32_t vco_mode;
};
typedef struct pp_atomctrl_clock_dividers_rv730 pp_atomctrl_clock_dividers_rv730;
struct pp_atomctrl_clock_dividers_kong {
uint32_t pll_post_divider;
uint32_t real_clock;
};
typedef struct pp_atomctrl_clock_dividers_kong pp_atomctrl_clock_dividers_kong;
struct pp_atomctrl_clock_dividers_ci {
uint32_t pll_post_divider; /* post divider value */
uint32_t real_clock;
pp_atomctrl_tcipll_fb_divider ul_fb_div; /* Output Parameter: PLL FB divider */
uint8_t uc_pll_ref_div; /* Output Parameter: PLL ref divider */
uint8_t uc_pll_post_div; /* Output Parameter: PLL post divider */
uint8_t uc_pll_cntl_flag; /*Output Flags: control flag */
};
typedef struct pp_atomctrl_clock_dividers_ci pp_atomctrl_clock_dividers_ci;
struct pp_atomctrl_clock_dividers_vi {
uint32_t pll_post_divider; /* post divider value */
uint32_t real_clock;
pp_atomctrl_tcipll_fb_divider ul_fb_div; /*Output Parameter: PLL FB divider */
uint8_t uc_pll_ref_div; /*Output Parameter: PLL ref divider */
uint8_t uc_pll_post_div; /*Output Parameter: PLL post divider */
uint8_t uc_pll_cntl_flag; /*Output Flags: control flag */
};
typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi;
union pp_atomctrl_s_mpll_fb_divider {
struct {
uint32_t cl_kf : 12;
uint32_t clk_frac : 12;
uint32_t un_used : 8;
};
uint32_t ul_fb_divider;
};
typedef union pp_atomctrl_s_mpll_fb_divider pp_atomctrl_s_mpll_fb_divider;
enum pp_atomctrl_spread_spectrum_mode {
pp_atomctrl_spread_spectrum_mode_down = 0,
pp_atomctrl_spread_spectrum_mode_center
};
typedef enum pp_atomctrl_spread_spectrum_mode pp_atomctrl_spread_spectrum_mode;
struct pp_atomctrl_memory_clock_param {
pp_atomctrl_s_mpll_fb_divider mpll_fb_divider;
uint32_t mpll_post_divider;
uint32_t bw_ctrl;
uint32_t dll_speed;
uint32_t vco_mode;
uint32_t yclk_sel;
uint32_t qdr;
uint32_t half_rate;
};
typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param;
struct pp_atomctrl_internal_ss_info {
uint32_t speed_spectrum_percentage; /* in 1/100 percentage */
uint32_t speed_spectrum_rate; /* in KHz */
pp_atomctrl_spread_spectrum_mode speed_spectrum_mode;
};
typedef struct pp_atomctrl_internal_ss_info pp_atomctrl_internal_ss_info;
#ifndef NUMBER_OF_M3ARB_PARAMS
#define NUMBER_OF_M3ARB_PARAMS 3
#endif
#ifndef NUMBER_OF_M3ARB_PARAM_SETS
#define NUMBER_OF_M3ARB_PARAM_SETS 10
#endif
struct pp_atomctrl_kong_system_info {
uint32_t ul_bootup_uma_clock; /* in 10kHz unit */
uint16_t us_max_nb_voltage; /* high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
uint16_t us_min_nb_voltage; /* low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
uint16_t us_bootup_nb_voltage; /* boot up NB voltage */
uint8_t uc_htc_tmp_lmt; /* bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD */
uint8_t uc_tj_offset; /* bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD */
/* 0: default 1: uvd 2: fs-3d */
uint32_t ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */
};
typedef struct pp_atomctrl_kong_system_info pp_atomctrl_kong_system_info;
struct pp_atomctrl_memory_info {
uint8_t memory_vendor;
uint8_t memory_type;
};
typedef struct pp_atomctrl_memory_info pp_atomctrl_memory_info;
#define MAX_AC_TIMING_ENTRIES 16
struct pp_atomctrl_memory_clock_range_table {
uint8_t num_entries;
uint8_t rsv[3];
uint32_t mclk[MAX_AC_TIMING_ENTRIES];
};
typedef struct pp_atomctrl_memory_clock_range_table pp_atomctrl_memory_clock_range_table;
struct pp_atomctrl_voltage_table_entry {
uint16_t value;
uint32_t smio_low;
};
typedef struct pp_atomctrl_voltage_table_entry pp_atomctrl_voltage_table_entry;
struct pp_atomctrl_voltage_table {
uint32_t count;
uint32_t mask_low;
uint32_t phase_delay; /* Used for ATOM_GPIO_VOLTAGE_OBJECT_V3 and later */
pp_atomctrl_voltage_table_entry entries[PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES];
};
typedef struct pp_atomctrl_voltage_table pp_atomctrl_voltage_table;
#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
#define VBIOS_MAX_AC_TIMING_ENTRIES 20
struct pp_atomctrl_mc_reg_entry {
uint32_t mclk_max;
uint32_t mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
};
typedef struct pp_atomctrl_mc_reg_entry pp_atomctrl_mc_reg_entry;
struct pp_atomctrl_mc_register_address {
uint16_t s1;
uint8_t uc_pre_reg_data;
};
typedef struct pp_atomctrl_mc_register_address pp_atomctrl_mc_register_address;
struct pp_atomctrl_mc_reg_table {
uint8_t last; /* number of registers */
uint8_t num_entries; /* number of AC timing entries */
pp_atomctrl_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
};
typedef struct pp_atomctrl_mc_reg_table pp_atomctrl_mc_reg_table;
struct pp_atomctrl_gpio_pin_assignment {
uint16_t us_gpio_pin_aindex;
uint8_t uc_gpio_pin_bit_shift;
};
typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment;
extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment);
extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);
extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);
extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
extern bool atomctrl_is_voltage_controled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
#endif
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef PP_INTERRUPT_H
#define PP_INTERRUPT_H
/**
* The type of the interrupt callback functions in PowerPlay
*/
typedef void (*pp_interrupt_callback) (void *context, uint32_t ul_context_data);
/**
* Event Manager action chain list information
*/
struct pp_interrupt_registration_info {
pp_interrupt_callback callback; /* Pointer to callback function */
void *context; /* Pointer to callback function context */
uint32_t *interrupt_enable_id; /* Registered interrupt id */
};
typedef struct pp_interrupt_registration_info pp_interrupt_registration_info;
#endif
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <linux/types.h>
#include "atom-types.h"
#include "atombios.h"
#include "pppcielanes.h"
/** \file
* Functions related to PCIe lane changes.
*/
/* For converting from number of lanes to lane bits. */
static const unsigned char pp_r600_encode_lanes[] = {
0, /* 0 Not Supported */
1, /* 1 Lane */
2, /* 2 Lanes */
0, /* 3 Not Supported */
3, /* 4 Lanes */
0, /* 5 Not Supported */
0, /* 6 Not Supported */
0, /* 7 Not Supported */
4, /* 8 Lanes */
0, /* 9 Not Supported */
0, /* 10 Not Supported */
0, /* 11 Not Supported */
5, /* 12 Lanes (Not actually supported) */
0, /* 13 Not Supported */
0, /* 14 Not Supported */
0, /* 15 Not Supported */
6 /* 16 Lanes */
};
static const unsigned char pp_r600_decoded_lanes[8] = { 16, 1, 2, 4, 8, 12, 16, };
uint8_t encode_pcie_lane_width(uint32_t num_lanes)
{
return pp_r600_encode_lanes[num_lanes];
}
uint8_t decode_pcie_lane_width(uint32_t num_lanes)
{
return pp_r600_decoded_lanes[num_lanes];
}
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef PP_PCIELANES_H
#define PP_PCIELANES_H
extern uint8_t encode_pcie_lane_width(uint32_t num_lanes);
extern uint8_t decode_pcie_lane_width(uint32_t num_lanes);
#endif
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef TONGA_DYN_DEFAULTS_H
#define TONGA_DYN_DEFAULTS_H
/** \file
* Volcanic Islands Dynamic default parameters.
*/
enum TONGAdpm_TrendDetection {
TONGAdpm_TrendDetection_AUTO,
TONGAdpm_TrendDetection_UP,
TONGAdpm_TrendDetection_DOWN
};
typedef enum TONGAdpm_TrendDetection TONGAdpm_TrendDetection;
/* Bit vector representing same fields as hardware register. */
#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102 /* CP_Gfx_busy */
/* HDP_busy */
/* IH_busy */
/* DRM_busy */
/* DRMDMA_busy */
/* UVD_busy */
/* VCE_busy */
/* ACP_busy */
/* SAMU_busy */
/* AVP_busy */
/* SDMA enabled */
#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT1 0x000400 /* FE_Gfx_busy - Intended for primary usage. Rest are for flexibility. */
/* SH_Gfx_busy */
/* RB_Gfx_busy */
/* VCE_busy */
#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT2 0xC00080 /* SH_Gfx_busy - Intended for primary usage. Rest are for flexibility. */
/* FE_Gfx_busy */
/* RB_Gfx_busy */
/* ACP_busy */
#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT3 0xC00200 /* RB_Gfx_busy - Intended for primary usage. Rest are for flexibility. */
/* FE_Gfx_busy */
/* SH_Gfx_busy */
/* UVD_busy */
#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT4 0xC01680 /* UVD_busy */
/* VCE_busy */
/* ACP_busy */
/* SAMU_busy */
#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT5 0xC00033 /* GFX, HDP, DRMDMA */
#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT6 0xC00033 /* GFX, HDP, DRMDMA */
#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT7 0x3FFFC000 /* GFX, HDP, DRMDMA */
/* thermal protection counter (units).*/
#define PPTONGA_THERMALPROTECTCOUNTER_DFLT 0x200 /* ~19us */
/* static screen threshold unit */
#define PPTONGA_STATICSCREENTHRESHOLDUNIT_DFLT 0
/* static screen threshold */
#define PPTONGA_STATICSCREENTHRESHOLD_DFLT 0x00C8
/* gfx idle clock stop threshold */
#define PPTONGA_GFXIDLECLOCKSTOPTHRESHOLD_DFLT 0x200 /* ~19us with static screen threshold unit of 0 */
/* Fixed reference divider to use when building baby stepping tables. */
#define PPTONGA_REFERENCEDIVIDER_DFLT 4
/*
* ULV voltage change delay time
* Used to be delay_vreg in N.I. split for S.I.
* Using N.I. delay_vreg value as default
* ReferenceClock = 2700
* VoltageResponseTime = 1000
* VDDCDelayTime = (VoltageResponseTime * ReferenceClock) / 1600 = 1687
*/
#define PPTONGA_ULVVOLTAGECHANGEDELAY_DFLT 1687
#define PPTONGA_CGULVPARAMETER_DFLT 0x00040035
#define PPTONGA_CGULVCONTROL_DFLT 0x00007450
#define PPTONGA_TARGETACTIVITY_DFLT 30 /*30% */
#define PPTONGA_MCLK_TARGETACTIVITY_DFLT 10 /*10% */
#endif
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/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef TONGA_POWERTUNE_H
#define TONGA_POWERTUNE_H
enum _phw_tonga_ptc_config_reg_type {
TONGA_CONFIGREG_MMR = 0,
TONGA_CONFIGREG_SMC_IND,
TONGA_CONFIGREG_DIDT_IND,
TONGA_CONFIGREG_CACHE,
TONGA_CONFIGREG_MAX
};
typedef enum _phw_tonga_ptc_config_reg_type phw_tonga_ptc_config_reg_type;
/* PowerContainment Features */
#define POWERCONTAINMENT_FEATURE_BAPM 0x00000001
#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
struct _phw_tonga_pt_config_reg {
uint32_t Offset;
uint32_t Mask;
uint32_t Shift;
uint32_t Value;
phw_tonga_ptc_config_reg_type Type;
};
typedef struct _phw_tonga_pt_config_reg phw_tonga_pt_config_reg;
struct _phw_tonga_pt_defaults {
uint8_t svi_load_line_en;
uint8_t svi_load_line_vddC;
uint8_t tdc_vddc_throttle_release_limit_perc;
uint8_t tdc_mawt;
uint8_t tdc_waterfall_ctl;
uint8_t dte_ambient_temp_base;
uint32_t display_cac;
uint32_t bamp_temp_gradient;
uint16_t bapmti_r[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
uint16_t bapmti_rc[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
};
typedef struct _phw_tonga_pt_defaults phw_tonga_pt_defaults;
#endif
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/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef TONGA_PROCESSPPTABLES_H
#define TONGA_PROCESSPPTABLES_H
#include "hwmgr.h"
extern const struct pp_table_func tonga_pptable_funcs;
extern int tonga_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr);
extern int tonga_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, uint32_t entry_index,
struct pp_power_state *power_state, int (*call_back_func)(struct pp_hwmgr *, void *,
struct pp_power_state *, void *, uint32_t));
#endif
......@@ -28,6 +28,7 @@
#include "pp_instance.h"
#include "hardwaremanager.h"
#include "pp_power_source.h"
#include "hwmgr_ppt.h"
struct pp_instance;
struct pp_hwmgr;
......@@ -400,7 +401,24 @@ struct phm_clock_and_voltage_limits {
uint16_t vddgfx;
};
/* Structure to hold PPTable information */
struct phm_ppt_v1_information {
struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
struct phm_clock_array *valid_sclk_values;
struct phm_clock_array *valid_mclk_values;
struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
struct phm_ppm_table *ppm_parameter_table;
struct phm_cac_tdp_table *cac_dtp_table;
struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
struct phm_ppt_v1_pcie_table *pcie_table;
uint16_t us_ulv_voltage_offset;
};
struct phm_dynamic_state_info {
struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
......@@ -434,6 +452,70 @@ struct phm_dynamic_state_info {
struct phm_vq_budgeting_table *vq_budgeting_table;
};
struct pp_fan_info {
bool bNoFan;
uint8_t ucTachometerPulsesPerRevolution;
uint32_t ulMinRPM;
uint32_t ulMaxRPM;
};
struct pp_advance_fan_control_parameters {
uint16_t usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
uint16_t usTMed; /* The middle temperature where we change slopes. */
uint16_t usTHigh; /* The high temperature for setting the second slope. */
uint16_t usPWMMin; /* The minimum PWM value in percent (0.01% increments). */
uint16_t usPWMMed; /* The PWM value (in percent) at TMed. */
uint16_t usPWMHigh; /* The PWM value at THigh. */
uint8_t ucTHyst; /* Temperature hysteresis. Integer. */
uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */
uint16_t usTMax; /* The max temperature */
uint8_t ucFanControlMode;
uint16_t usFanPWMMinLimit;
uint16_t usFanPWMMaxLimit;
uint16_t usFanPWMStep;
uint16_t usDefaultMaxFanPWM;
uint16_t usFanOutputSensitivity;
uint16_t usDefaultFanOutputSensitivity;
uint16_t usMaxFanPWM; /* The max Fan PWM value for Fuzzy Fan Control feature */
uint16_t usFanRPMMinLimit; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
uint16_t usFanRPMMaxLimit; /* Maximum limit range in percentage, usually set to 100% by default */
uint16_t usFanRPMStep; /* Step increments/decerements, in percent */
uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
uint16_t usMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
uint16_t usFanCurrentLow; /* Low current */
uint16_t usFanCurrentHigh; /* High current */
uint16_t usFanRPMLow; /* Low RPM */
uint16_t usFanRPMHigh; /* High RPM */
uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */
uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */
uint16_t usFanGainEdge; /* The following is added for Fiji */
uint16_t usFanGainHotspot;
uint16_t usFanGainLiquid;
uint16_t usFanGainVrVddc;
uint16_t usFanGainVrMvdd;
uint16_t usFanGainPlx;
uint16_t usFanGainHbm;
};
struct pp_thermal_controller_info {
uint8_t ucType;
uint8_t ucI2cLine;
uint8_t ucI2cAddress;
struct pp_fan_info fanInfo;
struct pp_advance_fan_control_parameters advanceFanControlParameters;
};
struct phm_microcode_version_info {
uint32_t SMC;
uint32_t DMCU;
uint32_t MC;
uint32_t NB;
};
/**
* The main hardware manager structure.
*/
struct pp_hwmgr {
uint32_t chip_family;
uint32_t chip_id;
......@@ -466,6 +548,8 @@ struct pp_hwmgr {
struct pp_power_state *ps;
enum pp_power_source power_source;
uint32_t num_ps;
struct pp_thermal_controller_info thermal_controller;
struct phm_microcode_version_info microcode_version_info;
uint32_t ps_size;
struct pp_power_state *current_ps;
struct pp_power_state *request_ps;
......@@ -487,7 +571,13 @@ extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
uint32_t index, uint32_t value, uint32_t mask);
extern uint32_t phm_read_indirect_register(struct pp_hwmgr *hwmgr,
uint32_t indirect_port, uint32_t index);
extern void phm_write_indirect_register(struct pp_hwmgr *hwmgr,
uint32_t indirect_port,
uint32_t index,
uint32_t value);
extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
uint32_t indirect_port,
......
......@@ -31,7 +31,7 @@
#define PP_ASSERT_WITH_CODE(cond, msg, code) \
do { \
if (!(cond)) { \
printk(msg); \
printk("%s\n", msg); \
code; \
} \
} while (0)
......
/*
* Copyright 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU_UCODE_XFER_VI_H
#define SMU_UCODE_XFER_VI_H
#define SMU_DRAMData_TOC_VERSION 1
#define MAX_IH_REGISTER_COUNT 65535
#define SMU_DIGEST_SIZE_BYTES 20
#define SMU_FB_SIZE_BYTES 1048576
#define SMU_MAX_ENTRIES 12
#define UCODE_ID_SMU 0
#define UCODE_ID_SDMA0 1
#define UCODE_ID_SDMA1 2
#define UCODE_ID_CP_CE 3
#define UCODE_ID_CP_PFP 4
#define UCODE_ID_CP_ME 5
#define UCODE_ID_CP_MEC 6
#define UCODE_ID_CP_MEC_JT1 7
#define UCODE_ID_CP_MEC_JT2 8
#define UCODE_ID_GMCON_RENG 9
#define UCODE_ID_RLC_G 10
#define UCODE_ID_IH_REG_RESTORE 11
#define UCODE_ID_VBIOS 12
#define UCODE_ID_MISC_METADATA 13
#define UCODE_ID_RLC_SCRATCH 32
#define UCODE_ID_RLC_SRM_ARAM 33
#define UCODE_ID_RLC_SRM_DRAM 34
#define UCODE_ID_MEC_STORAGE 35
#define UCODE_ID_VBIOS_PARAMETERS 36
#define UCODE_META_DATA 0xFF
#define UCODE_ID_SMU_MASK 0x00000001
#define UCODE_ID_SDMA0_MASK 0x00000002
#define UCODE_ID_SDMA1_MASK 0x00000004
#define UCODE_ID_CP_CE_MASK 0x00000008
#define UCODE_ID_CP_PFP_MASK 0x00000010
#define UCODE_ID_CP_ME_MASK 0x00000020
#define UCODE_ID_CP_MEC_MASK 0x00000040
#define UCODE_ID_CP_MEC_JT1_MASK 0x00000080
#define UCODE_ID_CP_MEC_JT2_MASK 0x00000100
#define UCODE_ID_GMCON_RENG_MASK 0x00000200
#define UCODE_ID_RLC_G_MASK 0x00000400
#define UCODE_ID_IH_REG_RESTORE_MASK 0x00000800
#define UCODE_ID_VBIOS_MASK 0x00001000
#define UCODE_FLAG_UNHALT_MASK 0x1
struct SMU_Entry {
#ifndef __BIG_ENDIAN
uint16_t id;
uint16_t version;
uint32_t image_addr_high;
uint32_t image_addr_low;
uint32_t meta_data_addr_high;
uint32_t meta_data_addr_low;
uint32_t data_size_byte;
uint16_t flags;
uint16_t num_register_entries;
#else
uint16_t version;
uint16_t id;
uint32_t image_addr_high;
uint32_t image_addr_low;
uint32_t meta_data_addr_high;
uint32_t meta_data_addr_low;
uint32_t data_size_byte;
uint16_t num_register_entries;
uint16_t flags;
#endif
};
struct SMU_DRAMData_TOC {
uint32_t structure_version;
uint32_t num_entries;
struct SMU_Entry entry[SMU_MAX_ENTRIES];
};
#endif
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