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Commit c8bc5e39 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'fixes-non-critical' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull "ARM: Non-critical bug fixes" from Ardn Bergmann:
 "Simple bug fixes that were not considered important enough for
  inclusion into 3.3.  One bug fix was originally intended for 3.3 but
  accidentally got missed, but is not marked stable because it should
  only get backported once later fixes also make it into v3.4.

  Signed-off-by: Arnd Bergmann <arnd@arndb.de>"

* tag 'fixes-non-critical' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (66 commits)
  iomux-mx25.h slew rate adjusted for LCD __LD pins
  ARM: davinci: DA850: move da850_register_pm to .init.text
  ARM: davinci: cpufreq: fix compiler warning
  ARM: OMAP2+: Fix build for omap4 only builds with missing include of linux/bug.h
  ARM: OMAP2+: Fix section warnings for hsmmc_init_one
  ARM: OMAP2+: Fix build issues with missing include of linux/bug.h
  ARM: OMAP2+: gpmc-smsc911x: only register regulator for first instance
  ARM: OMAP3+: PM: VP: fix integer truncation error
  ARM: OMAP2+: PM: fix wakeupgen warning when hotplug disabled
  ARM: OMAP2+: PM: fix section mismatch with omap2_init_processor_devices()
  ARM: OMAP2: Fix section warning for n8x0 when CONFIG_MMC_OMAP is not set
  ARM: OMAP2+: Fix omap24xx_io_desc warning if SoC subtypes are not selected
  ARM: OMAP1: Fix section mismatch for omap1_init_early()
  ARM: OMAP1: Fix typo in lcd_dma.c
  ARM: OMAP: mailbox: trivial whitespace fix
  ARM: OMAP: Remove definition cpu_is_omap4430()
  ARM: OMAP2+: included some headers twice
  ARM: OMAP: clock.c: included linux/debugfs.h twice
  ARM: OMAP: don't build hwspinlock in vain
  ARM: OMAP2+: ads7846_init: put gpio_pendown into pdata if it's provided
  ...
parents e22057c8 489e7bec
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Showing with 650 additions and 323 deletions
arch/arm/Kconfig
View file @ c8bc5e39
......@@ -907,6 +907,7 @@ config ARCH_U300
config ARCH_U8500
bool "ST-Ericsson U8500 Series"
depends on MMU
select CPU_V7
select ARM_AMBA
select GENERIC_CLOCKEVENTS
......@@ -1583,7 +1584,7 @@ config LOCAL_TIMERS
config ARCH_NR_GPIO
int
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 350 if ARCH_U8500
default 355 if ARCH_U8500
default 0
help
Maximum number of GPIOs in the system.
......
arch/arm/configs/imx_v4_v5_defconfig
View file @ c8bc5e39
......@@ -68,6 +68,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_CFI_I2 is not set
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y
......
arch/arm/configs/lpc32xx_defconfig 0 → 100644
View file @ c8bc5e39
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_LPC32XX=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0"
CONFIG_CPU_IDLE=y
CONFIG_FPE_NWFPE=y
CONFIG_VFP=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_AOUT=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_MUSEUM_IDS=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_MISC_DEVICES=y
CONFIG_EEPROM_AT25=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_PHYLIB=y
CONFIG_SMSC_PHY=y
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_LPC32XX=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_PNX=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_PNX4008_WATCHDOG=y
CONFIG_FB=y
CONFIG_FB_ARMCLCD=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SEQUENCER=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_SEQUENCER_OSS=y
CONFIG_SND_DYNAMIC_MINORS=y
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
# CONFIG_SND_SPI is not set
CONFIG_SND_SOC=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_LIBUSUAL=y
CONFIG_MMC=y
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
CONFIG_RTC_DRV_LPC32XX=y
CONFIG_EXT2_FS=y
CONFIG_AUTOFS4_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_WBUF_VERIFY=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_INFO=y
# CONFIG_FTRACE is not set
# CONFIG_ARM_UNWIND is not set
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
CONFIG_CRYPTO_ANSI_CPRNG=y
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_CCITT=y
arch/arm/mach-davinci/cpufreq.c
View file @ c8bc5e39
......@@ -95,7 +95,7 @@ static int davinci_target(struct cpufreq_policy *policy,
if (freqs.old == freqs.new)
return ret;
dev_dbg(&cpufreq.dev, "transition: %u --> %u\n", freqs.old, freqs.new);
dev_dbg(cpufreq.dev, "transition: %u --> %u\n", freqs.old, freqs.new);
ret = cpufreq_frequency_table_target(policy, pdata->freq_table,
freqs.new, relation, &idx);
......
arch/arm/mach-davinci/da850.c
View file @ c8bc5e39
......@@ -1026,7 +1026,7 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate)
}
#endif
int da850_register_pm(struct platform_device *pdev)
int __init da850_register_pm(struct platform_device *pdev)
{
int ret;
struct davinci_pm_config *pdata = pdev->dev.platform_data;
......
arch/arm/mach-davinci/dma.c
View file @ c8bc5e39
......@@ -1508,12 +1508,8 @@ static int __init edma_probe(struct platform_device *pdev)
goto fail;
}
/* Everything lives on transfer controller 1 until otherwise
* specified. This way, long transfers on the low priority queue
* started by the codec engine will not cause audio defects.
*/
for (i = 0; i < edma_cc[j]->num_channels; i++)
map_dmach_queue(j, i, EVENTQ_1);
map_dmach_queue(j, i, info[j]->default_queue);
queue_tc_mapping = info[j]->queue_tc_mapping;
queue_priority_mapping = info[j]->queue_priority_mapping;
......
arch/arm/mach-davinci/include/mach/edma.h
View file @ c8bc5e39
......@@ -250,6 +250,11 @@ struct edma_soc_info {
unsigned n_slot;
unsigned n_tc;
unsigned n_cc;
/*
* Default queue is expected to be a low-priority queue.
* This way, long transfers on the default queue started
* by the codec engine will not cause audio defects.
*/
enum dma_event_q default_queue;
/* Resource reservation for other cores */
......
arch/arm/mach-imx/mach-pcm038.c
View file @ c8bc5e39
......@@ -233,7 +233,7 @@ static struct regulator_init_data sdhc1_data = {
static struct regulator_consumer_supply cam_consumers[] = {
{
.dev = NULL,
.dev_name = NULL,
.supply = "imx_cam_vcc",
},
};
......
arch/arm/mach-imx/mm-imx3.c
View file @ c8bc5e39
......@@ -76,7 +76,7 @@ static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
return __arm_ioremap(phys_addr, size, mtype);
}
void imx3_init_l2x0(void)
void __init imx3_init_l2x0(void)
{
void __iomem *l2x0_base;
void __iomem *clkctl_base;
......
arch/arm/mach-lpc32xx/clock.c
View file @ c8bc5e39
......@@ -82,6 +82,7 @@
* will also impact the individual peripheral rates.
*/
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
......@@ -97,9 +98,10 @@
#include "clock.h"
#include "common.h"
static DEFINE_SPINLOCK(global_clkregs_lock);
static struct clk clk_armpll;
static struct clk clk_usbpll;
static DEFINE_MUTEX(clkm_lock);
/*
* Post divider values for PLLs based on selected register value
......@@ -127,7 +129,7 @@ static struct clk osc_32KHz = {
static int local_pll397_enable(struct clk *clk, int enable)
{
u32 reg;
unsigned long timeout = 1 + msecs_to_jiffies(10);
unsigned long timeout = jiffies + msecs_to_jiffies(10);
reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
......@@ -142,7 +144,7 @@ static int local_pll397_enable(struct clk *clk, int enable)
/* Wait for PLL397 lock */
while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
(timeout > jiffies))
time_before(jiffies, timeout))
cpu_relax();
if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
......@@ -156,7 +158,7 @@ static int local_pll397_enable(struct clk *clk, int enable)
static int local_oscmain_enable(struct clk *clk, int enable)
{
u32 reg;
unsigned long timeout = 1 + msecs_to_jiffies(10);
unsigned long timeout = jiffies + msecs_to_jiffies(10);
reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
......@@ -171,7 +173,7 @@ static int local_oscmain_enable(struct clk *clk, int enable)
/* Wait for main oscillator to start */
while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
(timeout > jiffies))
time_before(jiffies, timeout))
cpu_relax();
if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
......@@ -383,7 +385,7 @@ static int local_usbpll_enable(struct clk *clk, int enable)
{
u32 reg;
int ret = -ENODEV;
unsigned long timeout = 1 + msecs_to_jiffies(10);
unsigned long timeout = jiffies + msecs_to_jiffies(10);
reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
......@@ -396,7 +398,7 @@ static int local_usbpll_enable(struct clk *clk, int enable)
__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
/* Wait for PLL lock */
while ((timeout > jiffies) & (ret == -ENODEV)) {
while (time_before(jiffies, timeout) && (ret == -ENODEV)) {
reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
ret = 0;
......@@ -891,20 +893,8 @@ static struct clk clk_lcd = {
.enable_mask = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
};
static inline void clk_lock(void)
{
mutex_lock(&clkm_lock);
}
static inline void clk_unlock(void)
{
mutex_unlock(&clkm_lock);
}
static void local_clk_disable(struct clk *clk)
{
WARN_ON(clk->usecount == 0);
/* Don't attempt to disable clock if it has no users */
if (clk->usecount > 0) {
clk->usecount--;
......@@ -947,10 +937,11 @@ static int local_clk_enable(struct clk *clk)
int clk_enable(struct clk *clk)
{
int ret;
unsigned long flags;
clk_lock();
spin_lock_irqsave(&global_clkregs_lock, flags);
ret = local_clk_enable(clk);
clk_unlock();
spin_unlock_irqrestore(&global_clkregs_lock, flags);
return ret;
}
......@@ -961,9 +952,11 @@ EXPORT_SYMBOL(clk_enable);
*/
void clk_disable(struct clk *clk)
{
clk_lock();
unsigned long flags;
spin_lock_irqsave(&global_clkregs_lock, flags);
local_clk_disable(clk);
clk_unlock();
spin_unlock_irqrestore(&global_clkregs_lock, flags);
}
EXPORT_SYMBOL(clk_disable);
......@@ -972,13 +965,7 @@ EXPORT_SYMBOL(clk_disable);
*/
unsigned long clk_get_rate(struct clk *clk)
{
unsigned long rate;
clk_lock();
rate = clk->get_rate(clk);
clk_unlock();
return rate;
return clk->get_rate(clk);
}
EXPORT_SYMBOL(clk_get_rate);
......@@ -994,11 +981,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
* the actual rate set as part of the peripheral dividers
* instead of high level clock control
*/
if (clk->set_rate) {
clk_lock();
if (clk->set_rate)
ret = clk->set_rate(clk, rate);
clk_unlock();
}
return ret;
}
......@@ -1009,15 +993,11 @@ EXPORT_SYMBOL(clk_set_rate);
*/
long clk_round_rate(struct clk *clk, unsigned long rate)
{
clk_lock();
if (clk->round_rate)
rate = clk->round_rate(clk, rate);
else
rate = clk->get_rate(clk);
clk_unlock();
return rate;
}
EXPORT_SYMBOL(clk_round_rate);
......@@ -1075,10 +1055,10 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
_REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
_REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
_REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0)
_REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1)
_REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
_REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
_REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
_REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc)
_REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
_REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
_REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
_REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
......
arch/arm/mach-lpc32xx/common.h
View file @ c8bc5e39
......@@ -65,7 +65,6 @@ extern u32 clk_get_pclk_div(void);
*/
extern void lpc32xx_get_uid(u32 devid[4]);
extern void lpc32xx_watchdog_reset(void);
extern u32 lpc32xx_return_iram_size(void);
/*
......
arch/arm/mach-lpc32xx/include/mach/platform.h
View file @ c8bc5e39
......@@ -591,42 +591,42 @@
/*
* Timer/counter register offsets
*/
#define LCP32XX_TIMER_IR(x) io_p2v((x) + 0x00)
#define LCP32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
#define LCP32XX_TIMER_TC(x) io_p2v((x) + 0x08)
#define LCP32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
#define LCP32XX_TIMER_PC(x) io_p2v((x) + 0x10)
#define LCP32XX_TIMER_MCR(x) io_p2v((x) + 0x14)
#define LCP32XX_TIMER_MR0(x) io_p2v((x) + 0x18)
#define LCP32XX_TIMER_MR1(x) io_p2v((x) + 0x1C)
#define LCP32XX_TIMER_MR2(x) io_p2v((x) + 0x20)
#define LCP32XX_TIMER_MR3(x) io_p2v((x) + 0x24)
#define LCP32XX_TIMER_CCR(x) io_p2v((x) + 0x28)
#define LCP32XX_TIMER_CR0(x) io_p2v((x) + 0x2C)
#define LCP32XX_TIMER_CR1(x) io_p2v((x) + 0x30)
#define LCP32XX_TIMER_CR2(x) io_p2v((x) + 0x34)
#define LCP32XX_TIMER_CR3(x) io_p2v((x) + 0x38)
#define LCP32XX_TIMER_EMR(x) io_p2v((x) + 0x3C)
#define LCP32XX_TIMER_CTCR(x) io_p2v((x) + 0x70)
#define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00)
#define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
#define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08)
#define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
#define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10)
#define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14)
#define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18)
#define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C)
#define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20)
#define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24)
#define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28)
#define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C)
#define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30)
#define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34)
#define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38)
#define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C)
#define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70)
/*
* ir register definitions
*/
#define LCP32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3))
#define LCP32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3)))
#define LPC32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3))
#define LPC32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3)))
/*
* tcr register definitions
*/
#define LCP32XX_TIMER_CNTR_TCR_EN 0x1
#define LCP32XX_TIMER_CNTR_TCR_RESET 0x2
#define LPC32XX_TIMER_CNTR_TCR_EN 0x1
#define LPC32XX_TIMER_CNTR_TCR_RESET 0x2
/*
* mcr register definitions
*/
#define LCP32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3))
#define LCP32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1))
#define LCP32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2))
#define LPC32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3))
#define LPC32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1))
#define LPC32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2))
/*
* Standard UART register offsets
......@@ -690,5 +690,8 @@
#define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130)
#define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134)
#define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138)
#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
#endif
arch/arm/mach-lpc32xx/phy3250.c
View file @ c8bc5e39
......@@ -247,6 +247,8 @@ static struct platform_device lpc32xx_gpio_led_device = {
};
static struct platform_device *phy3250_devs[] __initdata = {
&lpc32xx_rtc_device,
&lpc32xx_tsc_device,
&lpc32xx_i2c0_device,
&lpc32xx_i2c1_device,
&lpc32xx_i2c2_device,
......
arch/arm/mach-lpc32xx/pm.c
View file @ c8bc5e39
......@@ -13,7 +13,7 @@
/*
* LPC32XX CPU and system power management
*
* The LCP32XX has three CPU modes for controlling system power: run,
* The LPC32XX has three CPU modes for controlling system power: run,
* direct-run, and halt modes. When switching between halt and run modes,
* the CPU transistions through direct-run mode. For Linux, direct-run
* mode is not used in normal operation. Halt mode is used when the
......
arch/arm/mach-lpc32xx/timer.c
View file @ c8bc5e39
......@@ -34,11 +34,11 @@
static int lpc32xx_clkevt_next_event(unsigned long delta,
struct clock_event_device *dev)
{
__raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
__raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
return 0;
}
......@@ -58,7 +58,7 @@ static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
* disable the timer to wait for the first call to
* set_next_event().
*/
__raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
break;
case CLOCK_EVT_MODE_UNUSED:
......@@ -81,8 +81,8 @@ static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
struct clock_event_device *evt = &lpc32xx_clkevt;
/* Clear match */
__raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
evt->event_handler(evt);
......@@ -128,14 +128,14 @@ static void __init lpc32xx_timer_init(void)
clkrate = clkrate / clk_get_pclk_div();
/* Initial timer setup */
__raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
__raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
__raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
LCP32XX_TIMER_CNTR_MCR_STOP(0) |
LCP32XX_TIMER_CNTR_MCR_RESET(0),
LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
__raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) |
LPC32XX_TIMER_CNTR_MCR_STOP(0) |
LPC32XX_TIMER_CNTR_MCR_RESET(0),
LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
/* Setup tick interrupt */
setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
......@@ -151,14 +151,14 @@ static void __init lpc32xx_timer_init(void)
clockevents_register_device(&lpc32xx_clkevt);
/* Use timer1 as clock source. */
__raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
__raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
__raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
__raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
clocksource_mmio_init(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
__raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
__raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
"lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
}
......
arch/arm/mach-omap1/io.c
View file @ c8bc5e39
......@@ -118,7 +118,7 @@ void __init omap16xx_map_io(void)
/*
* Common low-level hardware init for omap1.
*/
void omap1_init_early(void)
void __init omap1_init_early(void)
{
omap_check_revision();
......
arch/arm/mach-omap2/Kconfig
View file @ c8bc5e39
......@@ -32,7 +32,7 @@ config ARCH_OMAP3
depends on ARCH_OMAP2PLUS
default y
select CPU_V7
select USB_ARCH_HAS_EHCI
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select ARCH_HAS_OPP
select PM_OPP if PM
select ARM_CPU_SUSPEND if PM
......@@ -52,7 +52,7 @@ config ARCH_OMAP4
select ARM_ERRATA_720789
select ARCH_HAS_OPP
select PM_OPP if PM
select USB_ARCH_HAS_EHCI
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select ARM_CPU_SUSPEND if PM
comment "OMAP Core Type"
......
arch/arm/mach-omap2/Makefile
View file @ c8bc5e39
......@@ -4,7 +4,7 @@
# Common support
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
common.o gpio.o dma.o wd_timer.o display.o
common.o gpio.o dma.o wd_timer.o display.o i2c.o
omap-2-3-common = irq.o sdrc.o
hwmod-common = omap_hwmod.o \
......@@ -184,9 +184,6 @@ obj-$(CONFIG_OMAP_IOMMU) += iommu2.o
iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o
obj-y += $(iommu-m) $(iommu-y)
i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
obj-y += $(i2c-omap-m) $(i2c-omap-y)
ifneq ($(CONFIG_TIDSPBRIDGE),)
obj-y += dsp.o
endif
......@@ -270,6 +267,8 @@ obj-y += $(smc91x-m) $(smc91x-y)
smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
obj-y += $(smsc911x-m) $(smsc911x-y)
obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
ifneq ($(CONFIG_HWSPINLOCK_OMAP),)
obj-y += hwspinlock.o
endif
obj-y += common-board-devices.o twl-common.o
arch/arm/mach-omap2/board-2430sdp.c
View file @ c8bc5e39
......@@ -279,7 +279,7 @@ static void __init omap_2430sdp_init(void)
platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
omap_serial_init();
omap_sdrc_init(NULL, NULL);
omap2_hsmmc_init(mmc);
omap_hsmmc_init(mmc);
omap2_usbfs_init(&sdp2430_usb_config);
omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
......
arch/arm/mach-omap2/board-3430sdp.c
View file @ c8bc5e39
......@@ -232,11 +232,13 @@ static struct omap2_hsmmc_info mmc[] = {
*/
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
.gpio_wp = 4,
.deferred = true,
},
{
.mmc = 2,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
.gpio_wp = 7,
.deferred = true,
},
{} /* Terminator */
};
......@@ -249,7 +251,7 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
*/
mmc[0].gpio_cd = gpio + 0;
mmc[1].gpio_cd = gpio + 1;
omap2_hsmmc_init(mmc);
omap_hsmmc_late_init(mmc);
/* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
......@@ -606,6 +608,7 @@ static void __init omap_3430sdp_init(void)
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_board_config = sdp3430_config;
omap_board_config_size = ARRAY_SIZE(sdp3430_config);
omap_hsmmc_init(mmc);
omap3430_i2c_init();
omap_display_init(&sdp3430_dss_data);
if (omap_rev() > OMAP3430_REV_ES1_0)
......
arch/arm/mach-omap2/board-4430sdp.c
View file @ c8bc5e39
......@@ -521,9 +521,9 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
struct omap2_hsmmc_info *c;
omap2_hsmmc_init(controllers);
omap_hsmmc_init(controllers);
for (c = controllers; c->mmc; c++)
omap4_twl6030_hsmmc_set_late_init(c->dev);
omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
return 0;
}
......
arch/arm/mach-omap2/board-am3517evm.c
View file @ c8bc5e39
......@@ -504,7 +504,7 @@ static void __init am3517_evm_init(void)
am3517_evm_musb_init();
/* MMC init function */
omap2_hsmmc_init(mmc);
omap_hsmmc_init(mmc);
}
MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
......
arch/arm/mach-omap2/board-cm-t35.c
View file @ c8bc5e39
......@@ -413,7 +413,7 @@ static struct omap2_hsmmc_info mmc[] = {
.caps = MMC_CAP_4_BIT_DATA,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
.deferred = true,
},
{
.mmc = 2,
......@@ -471,7 +471,7 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
omap_hsmmc_late_init(mmc);
return 0;
}
......@@ -639,6 +639,7 @@ static void __init cm_t3x_common_init(void)
omap_serial_init();
omap_sdrc_init(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_hsmmc_init(mmc);
cm_t35_init_i2c();
omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL);
cm_t35_init_ethernet();
......
arch/arm/mach-omap2/board-devkit8000.c
View file @ c8bc5e39
......@@ -100,6 +100,7 @@ static struct omap2_hsmmc_info mmc[] = {
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
.gpio_wp = 29,
.deferred = true,
},
{} /* Terminator */
};
......@@ -228,7 +229,7 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
omap_hsmmc_late_init(mmc);
/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
......@@ -636,6 +637,7 @@ static void __init devkit8000_init(void)
omap_dm9000_init();
omap_hsmmc_init(mmc);
devkit8000_i2c_init();
platform_add_devices(devkit8000_devices,
ARRAY_SIZE(devkit8000_devices));
......
arch/arm/mach-omap2/board-flash.c
View file @ c8bc5e39
......@@ -189,7 +189,7 @@ static u8 get_gpmc0_type(void)
*
* @return - void.
*/
void board_flash_init(struct flash_partitions partition_info[],
void __init board_flash_init(struct flash_partitions partition_info[],
char chip_sel_board[][GPMC_CS_NUM], int nand_type)
{
u8 cs = 0;
......
arch/arm/mach-omap2/board-igep0020.c
View file @ c8bc5e39
......@@ -295,6 +295,7 @@ static struct omap2_hsmmc_info mmc[] = {
.caps = MMC_CAP_4_BIT_DATA,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
.deferred = true,
},
#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
{
......@@ -402,7 +403,7 @@ static int igep_twl_gpio_setup(struct device *dev,
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
omap_hsmmc_late_init(mmc);
/* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
......@@ -639,6 +640,9 @@ static void __init igep_init(void)
/* Get IGEP2 hardware revision */
igep2_get_revision();
omap_hsmmc_init(mmc);
/* Register I2C busses and drivers */
igep_i2c_init();
platform_add_devices(igep_devices, ARRAY_SIZE(igep_devices));
......
arch/arm/mach-omap2/board-ldp.c
View file @ c8bc5e39
......@@ -27,7 +27,6 @@
#include <linux/io.h>
#include <linux/smsc911x.h>
#include <linux/mmc/host.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
......@@ -424,7 +423,7 @@ static void __init omap_ldp_init(void)
board_nand_init(ldp_nand_partitions,
ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
omap2_hsmmc_init(mmc);
omap_hsmmc_init(mmc);
ldp_display_init();
}
......
arch/arm/mach-omap2/board-n8x0.c
View file @ c8bc5e39
......@@ -36,10 +36,6 @@
#include "mux.h"
static int slot1_cover_open;
static int slot2_cover_open;
static struct device *mmc_device;
#define TUSB6010_ASYNC_CS 1
#define TUSB6010_SYNC_CS 4
#define TUSB6010_GPIO_INT 58
......@@ -211,6 +207,10 @@ static struct omap_onenand_platform_data board_onenand_data[] = {
#define N810_EMMC_VSD_GPIO 23
#define N810_EMMC_VIO_GPIO 9
static int slot1_cover_open;
static int slot2_cover_open;
static struct device *mmc_device;
static int n8x0_mmc_switch_slot(struct device *dev, int slot)
{
#ifdef CONFIG_MMC_DEBUG
......
arch/arm/mach-omap2/board-omap3beagle.c
View file @ c8bc5e39
......@@ -253,6 +253,7 @@ static struct omap2_hsmmc_info mmc[] = {
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
.gpio_wp = -EINVAL,
.deferred = true,
},
{} /* Terminator */
};
......@@ -272,12 +273,10 @@ static int beagle_twl_gpio_setup(struct device *dev,
{
int r;
if (beagle_config.mmc1_gpio_wp != -EINVAL)
omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
mmc[0].gpio_wp = beagle_config.mmc1_gpio_wp;
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
omap_hsmmc_late_init(mmc);
/*
* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
......@@ -521,6 +520,11 @@ static void __init omap3_beagle_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3_beagle_init_rev();
if (beagle_config.mmc1_gpio_wp != -EINVAL)
omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
omap_hsmmc_init(mmc);
omap3_beagle_i2c_init();
gpio_buttons[0].gpio = beagle_config.usr_button_gpio;
......
arch/arm/mach-omap2/board-omap3evm.c
View file @ c8bc5e39
......@@ -317,6 +317,7 @@ static struct omap2_hsmmc_info mmc[] = {
.caps = MMC_CAP_4_BIT_DATA,
.gpio_cd = -EINVAL,
.gpio_wp = 63,
.deferred = true,
},
#ifdef CONFIG_WL12XX_PLATFORM_DATA
{
......@@ -361,9 +362,8 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
int r, lcd_bl_en;
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
omap_mux_init_gpio(63, OMAP_PIN_INPUT);
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
omap_hsmmc_late_init(mmc);
/*
* Most GPIOs are for USB OTG. Some are mostly sent to
......@@ -644,6 +644,9 @@ static void __init omap3_evm_init(void)
omap_board_config = omap3_evm_config;
omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
omap_mux_init_gpio(63, OMAP_PIN_INPUT);
omap_hsmmc_init(mmc);
omap3_evm_i2c_init();
omap_display_init(&omap3_evm_dss_data);
......
arch/arm/mach-omap2/board-omap3logic.c
View file @ c8bc5e39
......@@ -128,7 +128,7 @@ static void __init board_mmc_init(void)
return;
}
omap2_hsmmc_init(board_mmc_info);
omap_hsmmc_init(board_mmc_info);
}
static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
......
arch/arm/mach-omap2/board-omap3pandora.c
View file @ c8bc5e39
......@@ -273,6 +273,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = {
.gpio_cd = -EINVAL,
.gpio_wp = 126,
.ext_clock = 0,
.deferred = true,
},
{
.mmc = 2,
......@@ -281,6 +282,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = {
.gpio_wp = 127,
.ext_clock = 1,
.transceiver = true,
.deferred = true,
},
{
.mmc = 3,
......@@ -300,7 +302,7 @@ static int omap3pandora_twl_gpio_setup(struct device *dev,
/* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */
omap3pandora_mmc[0].gpio_cd = gpio + 0;
omap3pandora_mmc[1].gpio_cd = gpio + 1;
omap2_hsmmc_init(omap3pandora_mmc);
omap_hsmmc_late_init(omap3pandora_mmc);
/* gpio + 13 drives 32kHz buffer for wifi module */
gpio_32khz = gpio + 13;
......@@ -343,7 +345,7 @@ static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = {
};
static struct regulator_consumer_supply pandora_usb_phy_supply[] = {
REGULATOR_SUPPLY("hsusb0", "ehci-omap.0"),
REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
};
/* ads7846 on SPI and 2 nub controllers on I2C */
......@@ -561,13 +563,13 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
.phy_reset = true,
.reset_gpio_port[0] = 16,
.reset_gpio_port[1] = -EINVAL,
.reset_gpio_port[0] = -EINVAL,
.reset_gpio_port[1] = 16,
.reset_gpio_port[2] = -EINVAL
};
......@@ -580,6 +582,7 @@ static struct omap_board_mux board_mux[] __initdata = {
static void __init omap3pandora_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_hsmmc_init(omap3pandora_mmc);
omap3pandora_i2c_init();
pandora_wl1251_init();
platform_add_devices(omap3pandora_devices,
......
arch/arm/mach-omap2/board-omap3stalker.c
View file @ c8bc5e39
......@@ -213,6 +213,7 @@ static struct omap2_hsmmc_info mmc[] = {
.caps = MMC_CAP_4_BIT_DATA,
.gpio_cd = -EINVAL,
.gpio_wp = 23,
.deferred = true,
},
{} /* Terminator */
};
......@@ -282,9 +283,8 @@ omap3stalker_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
omap_mux_init_gpio(23, OMAP_PIN_INPUT);
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
omap_hsmmc_late_init(mmc);
/*
* Most GPIOs are for USB OTG. Some are mostly sent to
......@@ -425,6 +425,9 @@ static void __init omap3_stalker_init(void)
omap_board_config = omap3_stalker_config;
omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
omap_mux_init_gpio(23, OMAP_PIN_INPUT);
omap_hsmmc_init(mmc);
omap3_stalker_i2c_init();
platform_add_devices(omap3_stalker_devices,
......
arch/arm/mach-omap2/board-omap3touchbook.c
View file @ c8bc5e39
......@@ -100,6 +100,7 @@ static struct omap2_hsmmc_info mmc[] = {
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
.gpio_wp = 29,
.deferred = true,
},
{} /* Terminator */
};
......@@ -117,15 +118,9 @@ static struct gpio_led gpio_leds[];
static int touchbook_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
if (system_rev >= 0x20 && system_rev <= 0x34301000) {
omap_mux_init_gpio(23, OMAP_PIN_INPUT);
mmc[0].gpio_wp = 23;
} else {
omap_mux_init_gpio(29, OMAP_PIN_INPUT);
}
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
omap_hsmmc_late_init(mmc);
/* REVISIT: need ehci-omap hooks for external VBUS
* power switch and overcurrent detect
......@@ -351,6 +346,14 @@ static void __init omap3_touchbook_init(void)
pm_power_off = omap3_touchbook_poweroff;
if (system_rev >= 0x20 && system_rev <= 0x34301000) {
omap_mux_init_gpio(23, OMAP_PIN_INPUT);
mmc[0].gpio_wp = 23;
} else {
omap_mux_init_gpio(29, OMAP_PIN_INPUT);
}
omap_hsmmc_init(mmc);
omap3_touchbook_i2c_init();
platform_add_devices(omap3_touchbook_devices,
ARRAY_SIZE(omap3_touchbook_devices));
......
arch/arm/mach-omap2/board-omap4panda.c
View file @ c8bc5e39
......@@ -271,9 +271,9 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
struct omap2_hsmmc_info *c;
omap2_hsmmc_init(controllers);
omap_hsmmc_init(controllers);
for (c = controllers; c->mmc; c++)
omap4_twl6030_hsmmc_set_late_init(c->dev);
omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
return 0;
}
......@@ -504,7 +504,7 @@ static struct omap_dss_board_info omap4_panda_dss_data = {
.default_device = &omap4_panda_dvi_device,
};
void omap4_panda_display_init(void)
void __init omap4_panda_display_init(void)
{
int r;
......
arch/arm/mach-omap2/board-overo.c
View file @ c8bc5e39
......@@ -407,8 +407,6 @@ static inline void __init overo_init_keys(void) { return; }
static int overo_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
omap2_hsmmc_init(mmc);
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
......@@ -505,6 +503,7 @@ static void __init overo_init(void)
int ret;
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_hsmmc_init(mmc);
overo_i2c_init();
omap_display_init(&overo_dss_data);
omap_serial_init();
......
arch/arm/mach-omap2/board-rm680.c
View file @ c8bc5e39
......@@ -120,7 +120,7 @@ static void __init rm680_peripherals_init(void)
ARRAY_SIZE(rm680_peripherals_devices));
rm680_i2c_init();
gpmc_onenand_init(board_onenand_data);
omap2_hsmmc_init(mmc);
omap_hsmmc_init(mmc);
}
#ifdef CONFIG_OMAP_MUX
......
arch/arm/mach-omap2/board-rx51-peripherals.c
View file @ c8bc5e39
......@@ -1145,7 +1145,7 @@ void __init rx51_peripherals_init(void)
partition = omap_mux_get("core");
if (partition)
omap2_hsmmc_init(mmc);
omap_hsmmc_init(mmc);
rx51_charger_init();
}
......
arch/arm/mach-omap2/board-zoom-display.c
View file @ c8bc5e39
......@@ -55,6 +55,7 @@ static void zoom_panel_disable_lcd(struct omap_dss_device *dssdev)
static int zoom_set_bl_intensity(struct omap_dss_device *dssdev, int level)
{
#ifdef CONFIG_TWL4030_CORE
unsigned char c;
u8 mux_pwm, enb_pwm;
......@@ -90,6 +91,9 @@ static int zoom_set_bl_intensity(struct omap_dss_device *dssdev, int level)
c = ((50 * (100 - level)) / 100) + 1;
twl_i2c_write_u8(TWL4030_MODULE_PWM1, 0x7F, TWL_LED_PWMOFF);
twl_i2c_write_u8(TWL4030_MODULE_PWM1, c, TWL_LED_PWMON);
#else
pr_warn("Backlight not enabled\n");
#endif
return 0;
}
......
arch/arm/mach-omap2/board-zoom-peripherals.c
View file @ c8bc5e39
......@@ -205,6 +205,7 @@ static struct omap2_hsmmc_info mmc[] = {
.caps = MMC_CAP_4_BIT_DATA,
.gpio_wp = -EINVAL,
.power_saving = true,
.deferred = true,
},
{
.name = "internal",
......@@ -233,7 +234,7 @@ static int zoom_twl_gpio_setup(struct device *dev,
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
omap_hsmmc_late_init(mmc);
ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
"lcd enable");
......@@ -301,6 +302,7 @@ void __init zoom_peripherals_init(void)
if (ret)
pr_err("error setting wl12xx data: %d\n", ret);
omap_hsmmc_init(mmc);
omap_i2c_init();
platform_device_register(&omap_vwlan_device);
usb_musb_init(NULL);
......
arch/arm/mach-omap2/clkt_clksel.c
View file @ c8bc5e39
......@@ -43,6 +43,7 @@
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/bug.h>
#include <plat/clock.h>
......
arch/arm/mach-omap2/common-board-devices.c
View file @ c8bc5e39
......@@ -76,13 +76,15 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
gpio_set_debounce(gpio_pendown, gpio_debounce);
}
ads7846_config.gpio_pendown = gpio_pendown;
spi_bi->bus_num = bus_num;
spi_bi->irq = OMAP_GPIO_IRQ(gpio_pendown);
if (board_pdata)
if (board_pdata) {
board_pdata->gpio_pendown = gpio_pendown;
spi_bi->platform_data = board_pdata;
} else {
ads7846_config.gpio_pendown = gpio_pendown;
}
spi_register_board_info(&ads7846_spi_board_info, 1);
}
......
arch/arm/mach-omap2/control.h
View file @ c8bc5e39
......@@ -338,6 +338,11 @@
#define AM35XX_HECC_SW_RST BIT(3)
#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
/*
* CONTROL AM33XX STATUS register
*/
#define AM33XX_CONTROL_STATUS 0x040
/*
* CONTROL OMAP STATUS register to identify OMAP3 features
*/
......
arch/arm/mach-omap2/devices.c
View file @ c8bc5e39
......@@ -276,7 +276,7 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
}
#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
static inline void omap_init_mbox(void)
static inline void __init omap_init_mbox(void)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
......@@ -316,7 +316,7 @@ static inline void omap_init_audio(void) {}
#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
static void omap_init_mcpdm(void)
static void __init omap_init_mcpdm(void)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
......@@ -337,7 +337,7 @@ static inline void omap_init_mcpdm(void) {}
#if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
static void omap_init_dmic(void)
static void __init omap_init_dmic(void)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
......@@ -359,7 +359,7 @@ static inline void omap_init_dmic(void) {}
#include <plat/mcspi.h>
static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused)
{
struct platform_device *pdev;
char *name = "omap2_mcspi";
......@@ -633,9 +633,7 @@ void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
#define OMAP_HDQ_BASE 0x480B2000
#endif
static struct resource omap_hdq_resources[] = {
{
.start = OMAP_HDQ_BASE,
......@@ -658,7 +656,10 @@ static struct platform_device omap_hdq_dev = {
};
static inline void omap_hdq_init(void)
{
(void) platform_device_register(&omap_hdq_dev);
if (cpu_is_omap2420())
return;
platform_device_register(&omap_hdq_dev);
}
#else
static inline void omap_hdq_init(void) {}
......
arch/arm/mach-omap2/display.c
View file @ c8bc5e39
......@@ -124,7 +124,7 @@ static void omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
}
}
static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
static int __init omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
{
u32 enable_mask, enable_shift;
u32 pipd_mask, pipd_shift;
......@@ -157,7 +157,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
return 0;
}
int omap_hdmi_init(enum omap_hdmi_flags flags)
int __init omap_hdmi_init(enum omap_hdmi_flags flags)
{
if (cpu_is_omap44xx())
omap4_hdmi_mux_pads(flags);
......@@ -165,7 +165,7 @@ int omap_hdmi_init(enum omap_hdmi_flags flags)
return 0;
}
static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
static int __init omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
{
if (cpu_is_omap44xx())
return omap4_dsi_mux_pads(dsi_id, lane_mask);
......@@ -173,7 +173,7 @@ static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
return 0;
}
static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
static void __init omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
{
if (cpu_is_omap44xx())
omap4_dsi_mux_pads(dsi_id, 0);
......
arch/arm/mach-omap2/dma.c
View file @ c8bc5e39
......@@ -227,7 +227,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
dma_stride = OMAP2_DMA_STRIDE;
dma_common_ch_start = CSDP;
if (cpu_is_omap3630() || cpu_is_omap4430())
if (cpu_is_omap3630() || cpu_is_omap44xx())
dma_common_ch_end = CCDN;
else
dma_common_ch_end = CCFN;
......
arch/arm/mach-omap2/gpio.c
View file @ c8bc5e39
......@@ -24,7 +24,7 @@
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
{
struct platform_device *pdev;
struct omap_gpio_platform_data *pdata;
......
arch/arm/mach-omap2/gpmc-smsc911x.c
View file @ c8bc5e39
......@@ -101,11 +101,14 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
gpmc_cfg = board_data;
if (!gpmc_cfg->id) {
ret = platform_device_register(&gpmc_smsc911x_regulator);
if (ret < 0) {
pr_err("Unable to register smsc911x regulators: %d\n", ret);
pr_err("Unable to register smsc911x regulators: %d\n",
ret);
return;
}
}
if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
pr_err("Failed to request GPMC mem region\n");
......
arch/arm/mach-omap2/gpmc.c
View file @ c8bc5e39
......@@ -888,6 +888,7 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
gpmc_write_reg(GPMC_ECC_CONFIG, val);
return 0;
}
EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
/**
* gpmc_calculate_ecc - generate non-inverted ecc bytes
......@@ -918,3 +919,4 @@ int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
gpmc_ecc_used = -EINVAL;
return 0;
}
EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
arch/arm/mach-omap2/hsmmc.c
View file @ c8bc5e39
......@@ -293,7 +293,7 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
}
}
static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
struct omap_mmc_platform_data *mmc)
{
char *hc_name;
......@@ -429,66 +429,131 @@ static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
}
static int omap_hsmmc_done;
void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
{
struct platform_device *pdev;
struct omap_mmc_platform_data *mmc_pdata;
int res;
if (omap_hsmmc_done != 1)
return;
omap_hsmmc_done++;
for (; c->mmc; c++) {
if (!c->deferred)
continue;
pdev = c->pdev;
if (!pdev)
continue;
mmc_pdata = pdev->dev.platform_data;
if (!mmc_pdata)
continue;
mmc_pdata->slots[0].switch_pin = c->gpio_cd;
mmc_pdata->slots[0].gpio_wp = c->gpio_wp;
res = omap_device_register(pdev);
if (res)
pr_err("Could not late init MMC %s\n",
c->name);
}
}
#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
int ctrl_nr)
{
struct omap_hwmod *oh;
struct omap_hwmod *ohs[1];
struct omap_device *od;
struct platform_device *pdev;
char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
struct omap_mmc_platform_data *mmc_data;
struct omap_mmc_dev_attr *mmc_dev_attr;
char *name;
int l;
int res;
mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
if (!mmc_data) {
pr_err("Cannot allocate memory for mmc device!\n");
goto done;
return;
}
if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
pr_err("%s fails!\n", __func__);
goto done;
}
res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
if (res < 0)
goto free_mmc;
omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
name = "omap_hsmmc";
l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
"mmc%d", ctrl_nr);
WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
"String buffer overflow in MMC%d device setup\n", ctrl_nr);
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("Could not look up %s\n", oh_name);
kfree(mmc_data->slots[0].name);
goto done;
goto free_name;
}
ohs[0] = oh;
if (oh->dev_attr != NULL) {
mmc_dev_attr = oh->dev_attr;
mmc_data->controller_flags = mmc_dev_attr->flags;
}
pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
sizeof(struct omap_mmc_platform_data), NULL, 0, false);
if (IS_ERR(pdev)) {
WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
kfree(mmc_data->slots[0].name);
goto done;
pdev = platform_device_alloc(name, ctrl_nr - 1);
if (!pdev) {
pr_err("Could not allocate pdev for %s\n", name);
goto free_name;
}
/*
* return device handle to board setup code
* required to populate for regulator framework structure
*/
hsmmcinfo->dev = &pdev->dev;
dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
if (!od) {
pr_err("Could not allocate od for %s\n", name);
goto put_pdev;
}
res = platform_device_add_data(pdev, mmc_data,
sizeof(struct omap_mmc_platform_data));
if (res) {
pr_err("Could not add pdata for %s\n", name);
goto put_pdev;
}
hsmmcinfo->pdev = pdev;
if (hsmmcinfo->deferred)
goto free_mmc;
res = omap_device_register(pdev);
if (res) {
pr_err("Could not register od for %s\n", name);
goto free_od;
}
goto free_mmc;
free_od:
omap_device_delete(od);
put_pdev:
platform_device_put(pdev);
free_name:
kfree(mmc_data->slots[0].name);
done:
free_mmc:
kfree(mmc_data);
}
void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
u32 reg;
......@@ -521,7 +586,7 @@ void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
}
for (; controllers->mmc; controllers++)
omap_init_hsmmc(controllers, controllers->mmc);
omap_hsmmc_init_one(controllers, controllers->mmc);
}
......
arch/arm/mach-omap2/hsmmc.h
View file @ c8bc5e39
......@@ -21,10 +21,11 @@ struct omap2_hsmmc_info {
bool no_off; /* power_saving and power is not to go off */
bool no_off_init; /* no power off when not in MMC sleep state */
bool vcc_aux_disable_is_sleep; /* Regulator off remapped to sleep */
bool deferred; /* mmc needs a deferred probe */
int gpio_cd; /* or -EINVAL */
int gpio_wp; /* or -EINVAL */
char *name; /* or NULL for default */
struct device *dev; /* returned: pointer to mmc adapter */
struct platform_device *pdev; /* mmc controller instance */
int ocr_mask; /* temporary HACK */
/* Remux (pad configuration) when powering on/off */
void (*remux)(struct device *dev, int slot, int power_on);
......@@ -34,11 +35,16 @@ struct omap2_hsmmc_info {
#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
void omap2_hsmmc_init(struct omap2_hsmmc_info *);
void omap_hsmmc_init(struct omap2_hsmmc_info *);
void omap_hsmmc_late_init(struct omap2_hsmmc_info *);
#else
static inline void omap2_hsmmc_init(struct omap2_hsmmc_info *info)
static inline void omap_hsmmc_init(struct omap2_hsmmc_info *info)
{
}
static inline void omap_hsmmc_late_init(struct omap2_hsmmc_info *info)
{
}
......
arch/arm/mach-omap2/id.c
View file @ c8bc5e39
......@@ -44,6 +44,8 @@ int omap_type(void)
if (cpu_is_omap24xx()) {
val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
} else if (cpu_is_am33xx()) {
val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
} else if (cpu_is_omap34xx()) {
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
} else if (cpu_is_omap44xx()) {
......
arch/arm/mach-omap2/io.c
View file @ c8bc5e39
......@@ -42,14 +42,13 @@
#include "clockdomain.h"
#include <plat/omap_hwmod.h>
#include <plat/multi.h>
#include "common.h"
/*
* The machine specific code may provide the extra mapping besides the
* default mapping provided here.
*/
#ifdef CONFIG_ARCH_OMAP2
#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
static struct map_desc omap24xx_io_desc[] __initdata = {
{
.virtual = L3_24XX_VIRT,
......
arch/arm/mach-omap2/mcbsp.c
View file @ c8bc5e39
......@@ -158,7 +158,7 @@ static int omap3_enable_st_clock(unsigned int id, bool enable)
return 0;
}
static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
{
int id, count = 1;
char *name = "omap-mcbsp";
......
arch/arm/mach-omap2/mux.c
View file @ c8bc5e39
......@@ -100,7 +100,7 @@ void omap_mux_write_array(struct omap_mux_partition *partition,
static char *omap_mux_options;
static int _omap_mux_init_gpio(struct omap_mux_partition *partition,
static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
int gpio, int val)
{
struct omap_mux_entry *e;
......@@ -145,7 +145,7 @@ static int _omap_mux_init_gpio(struct omap_mux_partition *partition,
return 0;
}
int omap_mux_init_gpio(int gpio, int val)
int __init omap_mux_init_gpio(int gpio, int val)
{
struct omap_mux_partition *partition;
int ret;
......@@ -159,7 +159,7 @@ int omap_mux_init_gpio(int gpio, int val)
return -ENODEV;
}
static int _omap_mux_get_by_name(struct omap_mux_partition *partition,
static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
const char *muxname,
struct omap_mux **found_mux)
{
......@@ -218,7 +218,7 @@ static int _omap_mux_get_by_name(struct omap_mux_partition *partition,
return -ENODEV;
}
static int
static int __init
omap_mux_get_by_name(const char *muxname,
struct omap_mux_partition **found_partition,
struct omap_mux **found_mux)
......@@ -240,7 +240,7 @@ omap_mux_get_by_name(const char *muxname,
return -ENODEV;
}
int omap_mux_init_signal(const char *muxname, int val)
int __init omap_mux_init_signal(const char *muxname, int val)
{
struct omap_mux_partition *partition = NULL;
struct omap_mux *mux = NULL;
......
arch/arm/mach-omap2/mux.h
View file @ c8bc5e39
......@@ -246,7 +246,7 @@ static inline void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
{
}
static struct omap_board_mux *board_mux __initdata __maybe_unused;
static struct omap_board_mux *board_mux __maybe_unused;
#endif
......
arch/arm/mach-omap2/omap-hotplug.c
View file @ c8bc5e39
......@@ -33,7 +33,7 @@ int platform_cpu_kill(unsigned int cpu)
* platform-specific code to shutdown a CPU
* Called with IRQs disabled
*/
void platform_cpu_die(unsigned int cpu)
void __ref platform_cpu_die(unsigned int cpu)
{
unsigned int this_cpu;
......
arch/arm/mach-omap2/omap-mpuss-lowpower.c
View file @ c8bc5e39
......@@ -300,7 +300,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
* @cpu : CPU ID
* @power_state: CPU low power state.
*/
int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
{
unsigned int cpu_state = 0;
......
arch/arm/mach-omap2/omap-wakeupgen.c
View file @ c8bc5e39
......@@ -43,7 +43,6 @@
static void __iomem *wakeupgen_base;
static void __iomem *sar_base;
static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
static DEFINE_SPINLOCK(wakeupgen_lock);
static unsigned int irq_target_cpu[NR_IRQS];
......@@ -67,14 +66,6 @@ static inline void sar_writel(u32 val, u32 offset, u8 idx)
__raw_writel(val, sar_base + offset + (idx * 4));
}
static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
{
u8 i;
for (i = 0; i < NR_REG_BANKS; i++)
wakeupgen_writel(reg, i, cpu);
}
static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
{
unsigned int spi_irq;
......@@ -130,22 +121,6 @@ static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
wakeupgen_writel(val, i, cpu);
}
static void _wakeupgen_save_masks(unsigned int cpu)
{
u8 i;
for (i = 0; i < NR_REG_BANKS; i++)
per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
}
static void _wakeupgen_restore_masks(unsigned int cpu)
{
u8 i;
for (i = 0; i < NR_REG_BANKS; i++)
wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
}
/*
* Architecture specific Mask extension
*/
......@@ -170,6 +145,33 @@ static void wakeupgen_unmask(struct irq_data *d)
spin_unlock_irqrestore(&wakeupgen_lock, flags);
}
#ifdef CONFIG_HOTPLUG_CPU
static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
static void _wakeupgen_save_masks(unsigned int cpu)
{
u8 i;
for (i = 0; i < NR_REG_BANKS; i++)
per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
}
static void _wakeupgen_restore_masks(unsigned int cpu)
{
u8 i;
for (i = 0; i < NR_REG_BANKS; i++)
wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
}
static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
{
u8 i;
for (i = 0; i < NR_REG_BANKS; i++)
wakeupgen_writel(reg, i, cpu);
}
/*
* Mask or unmask all interrupts on given CPU.
* 0 = Mask all interrupts on the 'cpu'
......@@ -191,6 +193,7 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
}
spin_unlock_irqrestore(&wakeupgen_lock, flags);
}
#endif
#ifdef CONFIG_CPU_PM
/*
......
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View file @ c8bc5e39
......@@ -28,7 +28,6 @@
#include <plat/mcspi.h>
#include <plat/mcbsp.h>
#include <plat/mmc.h>
#include <plat/i2c.h>
#include <plat/dmtimer.h>
#include <plat/common.h>
......
arch/arm/mach-omap2/pm.c
View file @ c8bc5e39
......@@ -28,7 +28,7 @@
static struct omap_device_pm_latency *pm_lats;
static int _init_omap_device(char *name)
static int __init _init_omap_device(char *name)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
......@@ -49,7 +49,7 @@ static int _init_omap_device(char *name)
/*
* Build omap_devices for processors and bus.
*/
static void omap2_init_processor_devices(void)
static void __init omap2_init_processor_devices(void)
{
_init_omap_device("mpu");
if (omap3_has_iva())
......
arch/arm/mach-omap2/powerdomain-common.c
View file @ c8bc5e39
......@@ -13,6 +13,7 @@
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/bug.h>
#include "pm.h"
#include "cm.h"
#include "cm-regbits-34xx.h"
......
arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
View file @ c8bc5e39
......@@ -15,6 +15,7 @@
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/bug.h>
#include <plat/prcm.h>
......
arch/arm/mach-omap2/powerdomain44xx.c
View file @ c8bc5e39
......@@ -15,6 +15,7 @@
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/bug.h>
#include "powerdomain.h"
#include <plat/prcm.h>
......
arch/arm/mach-omap2/powerdomains3xxx_data.c
View file @ c8bc5e39
......@@ -13,6 +13,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bug.h>
#include <plat/cpu.h>
......
arch/arm/mach-omap2/smartreflex.c
View file @ c8bc5e39
......@@ -1012,7 +1012,7 @@ static int __devexit omap_sr_remove(struct platform_device *pdev)
}
static struct platform_driver smartreflex_driver = {
.remove = omap_sr_remove,
.remove = __devexit_p(omap_sr_remove),
.driver = {
.name = "smartreflex",
},
......
arch/arm/mach-omap2/sr_device.c
View file @ c8bc5e39
......@@ -69,7 +69,7 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
sr_data->nvalue_count = count;
}
static int sr_dev_init(struct omap_hwmod *oh, void *user)
static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
{
struct omap_sr_data *sr_data;
struct platform_device *pdev;
......
arch/arm/mach-omap2/vc.c
View file @ c8bc5e39
......@@ -10,6 +10,7 @@
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/bug.h>
#include <plat/cpu.h>
......
arch/arm/mach-omap2/vp.c
View file @ c8bc5e39
......@@ -61,8 +61,8 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
vddmin = voltdm->pmic->vp_vddmin;
vddmax = voltdm->pmic->vp_vddmax;
waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
sys_clk_rate) / 1000;
waittime = DIV_ROUND_UP(voltdm->pmic->step_size * sys_clk_rate,
1000 * voltdm->pmic->slew_rate);
vstepmin = voltdm->pmic->vp_vstepmin;
vstepmax = voltdm->pmic->vp_vstepmax;
......
arch/arm/mach-ux500/Kconfig
View file @ c8bc5e39
......@@ -8,47 +8,55 @@ config UX500_SOC_COMMON
select PL310_ERRATA_753970
select ARM_ERRATA_754322
select ARM_ERRATA_764369
menu "Ux500 SoC"
select CACHE_L2X0
config UX500_SOC_DB5500
bool "DB5500"
bool
select MFD_DB5500_PRCMU
config UX500_SOC_DB8500
bool "DB8500"
bool
select MFD_DB8500_PRCMU
select REGULATOR_DB8500_PRCMU
endmenu
select CPU_FREQ_TABLE if CPU_FREQ
menu "Ux500 target platform (boards)"
config MACH_U8500
bool "U8500 Development platform"
depends on UX500_SOC_DB8500
select TPS6105X
config MACH_MOP500
bool "U8500 Development platform, MOP500 versions"
select UX500_SOC_DB8500
select I2C
select I2C_NOMADIK
help
Include support for the mop500 development platform.
Include support for the MOP500 development platform.
config MACH_HREFV60
bool "U85000 Development platform, HREFv60 version"
depends on UX500_SOC_DB8500
bool "U8500 Development platform, HREFv60 version"
select MACH_MOP500
help
Include support for the HREFv60 new development platform.
Includes HREFv70, v71 etc.
config MACH_SNOWBALL
bool "U8500 Snowball platform"
depends on UX500_SOC_DB8500
select MACH_U8500
select MACH_MOP500
help
Include support for the snowball development platform.
config MACH_U5500
bool "U5500 Development platform"
depends on UX500_SOC_DB5500
select UX500_SOC_DB5500
help
Include support for the U5500 development platform.
config UX500_AUTO_PLATFORM
def_bool y
depends on !MACH_U5500
select MACH_MOP500
help
At least one platform needs to be selected in order to build
a working kernel. If everything else is disabled, this
automatically enables MACH_MOP500.
endmenu
config UX500_DEBUG_UART
......
arch/arm/mach-ux500/Makefile
View file @ c8bc5e39
......@@ -7,7 +7,7 @@ obj-y := clock.o cpu.o devices.o devices-common.o \
obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o
obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o
obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \
obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \
board-mop500-regulators.o \
board-mop500-uib.o board-mop500-stuib.o \
board-mop500-u8500uib.o \
......
arch/arm/mach-ux500/board-mop500-regulators.c
View file @ c8bc5e39
......@@ -74,6 +74,26 @@ static struct regulator_consumer_supply ab8500_vtvout_consumers[] = {
REGULATOR_SUPPLY("vddadc", "ab8500-gpadc.0"),
};
static struct regulator_consumer_supply ab8500_vaud_consumers[] = {
/* AB8500 audio-codec main supply */
REGULATOR_SUPPLY("vaud", "ab8500-codec.0"),
};
static struct regulator_consumer_supply ab8500_vamic1_consumers[] = {
/* AB8500 audio-codec Mic1 supply */
REGULATOR_SUPPLY("vamic1", "ab8500-codec.0"),
};
static struct regulator_consumer_supply ab8500_vamic2_consumers[] = {
/* AB8500 audio-codec Mic2 supply */
REGULATOR_SUPPLY("vamic2", "ab8500-codec.0"),
};
static struct regulator_consumer_supply ab8500_vdmic_consumers[] = {
/* AB8500 audio-codec DMic supply */
REGULATOR_SUPPLY("vdmic", "ab8500-codec.0"),
};
static struct regulator_consumer_supply ab8500_vintcore_consumers[] = {
/* SoC core supply, no device */
REGULATOR_SUPPLY("v-intcore", NULL),
......@@ -323,6 +343,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
.name = "V-AUD",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(ab8500_vaud_consumers),
.consumer_supplies = ab8500_vaud_consumers,
},
/* supply for v-anamic1 VAMic1-LDO */
[AB8500_LDO_ANAMIC1] = {
......@@ -330,6 +352,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
.name = "V-AMIC1",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(ab8500_vamic1_consumers),
.consumer_supplies = ab8500_vamic1_consumers,
},
/* supply for v-amic2, VAMIC2 LDO, reuse constants for AMIC1 */
[AB8500_LDO_ANAMIC2] = {
......@@ -337,6 +361,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
.name = "V-AMIC2",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(ab8500_vamic2_consumers),
.consumer_supplies = ab8500_vamic2_consumers,
},
/* supply for v-dmic, VDMIC LDO */
[AB8500_LDO_DMIC] = {
......@@ -344,6 +370,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
.name = "V-DMIC",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(ab8500_vdmic_consumers),
.consumer_supplies = ab8500_vdmic_consumers,
},
/* supply for v-intcore12, VINTCORE12 LDO */
[AB8500_LDO_INTCORE] = {
......
arch/arm/mach-ux500/board-mop500-u8500uib.c
View file @ c8bc5e39
......@@ -8,7 +8,6 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/mfd/tc3589x.h>
#include <linux/input/matrix_keypad.h>
......
arch/arm/mach-ux500/board-mop500.c
View file @ c8bc5e39
......@@ -72,7 +72,7 @@ static struct platform_device snowball_led_dev = {
};
static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
.gpio_base = MOP500_AB8500_GPIO(0),
.gpio_base = MOP500_AB8500_PIN_GPIO(1),
.irq_base = MOP500_AB8500_VIR_GPIO_IRQ_BASE,
/* config_reg is the initial configuration of ab8500 pins.
* The pins can be configured as GPIO or alt functions based
......
arch/arm/mach-ux500/board-mop500.h
View file @ c8bc5e39
......@@ -63,7 +63,7 @@
* because the AB8500 GPIO pins are enumbered starting from 1, so the value in
* parens matches the GPIO pin number in the data sheet.
*/
#define MOP500_AB8500_GPIO(x) (MOP500_EGPIO_END + (x) - 1)
#define MOP500_AB8500_PIN_GPIO(x) (MOP500_EGPIO_END + (x) - 1)
/*Snowball AB8500 GPIO */
#define SNOWBALL_VSMPS2_1V8_GPIO MOP500_AB8500_PIN_GPIO(1) /* SYSCLKREQ2/GPIO1 */
#define SNOWBALL_PM_GPIO1_GPIO MOP500_AB8500_PIN_GPIO(2) /* SYSCLKREQ3/GPIO2 */
......
arch/arm/mach-ux500/clock.c
View file @ c8bc5e39
......@@ -223,6 +223,13 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
}
EXPORT_SYMBOL(clk_set_rate);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
/*TODO*/
return -ENOSYS;
}
EXPORT_SYMBOL(clk_set_parent);
static void clk_prcmu_enable(struct clk *clk)
{
void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
......
arch/arm/mach-ux500/clock.h
View file @ c8bc5e39
......@@ -21,6 +21,7 @@ struct clkops {
void (*enable) (struct clk *);
void (*disable) (struct clk *);
unsigned long (*get_rate) (struct clk *);
int (*set_parent)(struct clk *, struct clk *);
};
/**
......
arch/arm/mach-ux500/devices-db8500.c
View file @ c8bc5e39
......@@ -101,6 +101,9 @@ static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
[DB8500_DMA_DEV41_SD_MM3_TX] = -1,
[DB8500_DMA_DEV42_SD_MM4_TX] = -1,
[DB8500_DMA_DEV43_SD_MM5_TX] = -1,
[DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
};
/* Mapping between source event lines and physical device address */
......@@ -133,6 +136,9 @@ static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
[DB8500_DMA_DEV41_SD_MM3_RX] = -1,
[DB8500_DMA_DEV42_SD_MM4_RX] = -1,
[DB8500_DMA_DEV43_SD_MM5_RX] = -1,
[DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
};
/* Reserved event lines for memcpy only */
......
arch/arm/mach-ux500/include/mach/hardware.h
View file @ c8bc5e39
......@@ -30,6 +30,8 @@
#include <mach/db8500-regs.h>
#include <mach/db5500-regs.h>
#define MSP_TX_RX_REG_OFFSET 0
#ifndef __ASSEMBLY__
#include <mach/id.h>
......
arch/arm/mach-ux500/include/mach/irqs.h
View file @ c8bc5e39
......@@ -43,7 +43,7 @@
/* This will be overridden by board-specific irq headers */
#define IRQ_BOARD_END IRQ_BOARD_START
#ifdef CONFIG_MACH_U8500
#ifdef CONFIG_MACH_MOP500
#include <mach/irqs-board-mop500.h>
#endif
......
arch/arm/plat-mxc/include/mach/iomux-mx25.h
View file @ c8bc5e39
......@@ -139,15 +139,15 @@
#define MX25_PAD_NFRB__GPIO_3_31 IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D15__D15 IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D15__LD16 IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D15__LD16 IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_D15__GPIO_4_5 IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D14__D14 IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D14__LD17 IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D14__LD17 IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_D14__GPIO_4_6 IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D13__D13 IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D13__LD18 IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D13__LD18 IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_D13__GPIO_4_7 IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D12__D12 IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
......@@ -192,54 +192,54 @@
#define MX25_PAD_D0__D0 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D0__GPIO_4_20 IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD0__LD0 IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD0__LD0 IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD0__CSI_D0 IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
#define MX25_PAD_LD0__GPIO_2_15 IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD1__LD1 IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD1__LD1 IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD1__CSI_D1 IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
#define MX25_PAD_LD1__GPIO_2_16 IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD2__LD2 IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD2__LD2 IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD2__GPIO_2_17 IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD3__LD3 IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD3__LD3 IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD3__GPIO_2_18 IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD4__LD4 IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD4__LD4 IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD4__GPIO_2_19 IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD5__LD5 IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD5__LD5 IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD5__GPIO_1_19 IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD6__LD6 IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD6__LD6 IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD6__GPIO_1_20 IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD7__LD7 IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD7__LD7 IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
......@@ -468,11 +468,11 @@
#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST)
#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
......
arch/arm/plat-omap/clock.c
View file @ c8bc5e39
......@@ -20,7 +20,6 @@
#include <linux/clk.h>
#include <linux/mutex.h>
#include <linux/cpufreq.h>
#include <linux/debugfs.h>
#include <linux/io.h>
#include <plat/clock.h>
......
arch/arm/plat-omap/dma.c
View file @ c8bc5e39
......@@ -2125,7 +2125,7 @@ static int __devexit omap_system_dma_remove(struct platform_device *pdev)
static struct platform_driver omap_system_dma_driver = {
.probe = omap_system_dma_probe,
.remove = omap_system_dma_remove,
.remove = __devexit_p(omap_system_dma_remove),
.driver = {
.name = "omap_dma_system"
},
......
arch/arm/plat-omap/dmtimer.c
View file @ c8bc5e39
......@@ -80,9 +80,9 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
static void omap_timer_restore_context(struct omap_dm_timer *timer)
{
omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_OFFSET,
timer->context.tiocp_cfg);
if (timer->revision > 1)
__raw_writel(timer->context.tiocp_cfg,
timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
if (timer->revision == 1)
__raw_writel(timer->context.tistat, timer->sys_stat);
__raw_writel(timer->context.tisr, timer->irq_stat);
......@@ -357,6 +357,19 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer)
__omap_dm_timer_stop(timer, timer->posted, rate);
if (timer->loses_context && timer->get_context_loss_count)
timer->ctx_loss_count =
timer->get_context_loss_count(&timer->pdev->dev);
/*
* Since the register values are computed and written within
* __omap_dm_timer_stop, we need to use read to retrieve the
* context.
*/
timer->context.tclr =
omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
timer->context.tisr = __raw_readl(timer->irq_stat);
omap_dm_timer_disable(timer);
return 0;
}
EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
......
arch/arm/plat-omap/include/plat/cpu.h
View file @ c8bc5e39
......@@ -250,7 +250,6 @@ IS_AM_SUBCLASS(335x, 0x335)
* cpu_is_omap2423(): True for OMAP2423
* cpu_is_omap2430(): True for OMAP2430
* cpu_is_omap3430(): True for OMAP3430
* cpu_is_omap4430(): True for OMAP4430
* cpu_is_omap3505(): True for OMAP3505
* cpu_is_omap3517(): True for OMAP3517
*/
......@@ -299,7 +298,6 @@ IS_OMAP_TYPE(3517, 0x3517)
#define cpu_is_omap3505() 0
#define cpu_is_omap3517() 0
#define cpu_is_omap3430() 0
#define cpu_is_omap4430() 0
#define cpu_is_omap3630() 0
/*
......
arch/arm/plat-omap/include/plat/omap_device.h
View file @ c8bc5e39
......@@ -100,6 +100,13 @@ struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
struct omap_device_pm_latency *pm_lats,
int pm_lats_cnt, int is_early_device);
struct omap_device *omap_device_alloc(struct platform_device *pdev,
struct omap_hwmod **ohs, int oh_cnt,
struct omap_device_pm_latency *pm_lats,
int pm_lats_cnt);
void omap_device_delete(struct omap_device *od);
int omap_device_register(struct platform_device *pdev);
void __iomem *omap_device_get_rt_va(struct omap_device *od);
struct device *omap_device_get_by_hwmod_name(const char *oh_name);
......
arch/arm/plat-omap/include/plat/sram.h
View file @ c8bc5e39
......@@ -101,4 +101,5 @@ static inline void omap_push_sram_idle(void) {}
#else
#define OMAP4_SRAM_PA 0x40300000
#endif
#define AM33XX_SRAM_PA 0x40300000
#endif
arch/arm/plat-omap/omap_device.c
View file @ c8bc5e39
/*
* omap_device implementation
*
......@@ -97,14 +98,7 @@
#define USE_WAKEUP_LAT 0
#define IGNORE_WAKEUP_LAT 1
static int omap_device_register(struct platform_device *pdev);
static int omap_early_device_register(struct platform_device *pdev);
static struct omap_device *omap_device_alloc(struct platform_device *pdev,
struct omap_hwmod **ohs, int oh_cnt,
struct omap_device_pm_latency *pm_lats,
int pm_lats_cnt);
static void omap_device_delete(struct omap_device *od);
static struct omap_device_pm_latency omap_default_latency[] = {
{
......@@ -509,7 +503,7 @@ static int omap_device_fill_resources(struct omap_device *od,
*
* Returns an struct omap_device pointer or ERR_PTR() on error;
*/
static struct omap_device *omap_device_alloc(struct platform_device *pdev,
struct omap_device *omap_device_alloc(struct platform_device *pdev,
struct omap_hwmod **ohs, int oh_cnt,
struct omap_device_pm_latency *pm_lats,
int pm_lats_cnt)
......@@ -591,7 +585,7 @@ static struct omap_device *omap_device_alloc(struct platform_device *pdev,
return ERR_PTR(ret);
}
static void omap_device_delete(struct omap_device *od)
void omap_device_delete(struct omap_device *od)
{
if (!od)
return;
......@@ -619,7 +613,7 @@ static void omap_device_delete(struct omap_device *od)
* information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
* passes along the return value of omap_device_build_ss().
*/
struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
struct platform_device __init *omap_device_build(const char *pdev_name, int pdev_id,
struct omap_hwmod *oh, void *pdata,
int pdata_len,
struct omap_device_pm_latency *pm_lats,
......@@ -652,7 +646,7 @@ struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
* platform_device record. Returns an ERR_PTR() on error, or passes
* along the return value of omap_device_register().
*/
struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
struct platform_device __init *omap_device_build_ss(const char *pdev_name, int pdev_id,
struct omap_hwmod **ohs, int oh_cnt,
void *pdata, int pdata_len,
struct omap_device_pm_latency *pm_lats,
......@@ -717,7 +711,7 @@ struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
* platform_early_add_device() on the underlying platform_device.
* Returns 0 by default.
*/
static int omap_early_device_register(struct platform_device *pdev)
static int __init omap_early_device_register(struct platform_device *pdev)
{
struct platform_device *devices[1];
......@@ -817,7 +811,7 @@ static struct dev_pm_domain omap_device_pm_domain = {
* platform_device_register() on the underlying platform_device.
* Returns the return value of platform_device_register().
*/
static int omap_device_register(struct platform_device *pdev)
int omap_device_register(struct platform_device *pdev)
{
pr_debug("omap_device: %s: registering\n", pdev->name);
......
arch/arm/plat-omap/sram.c
View file @ c8bc5e39
......@@ -86,7 +86,7 @@ static int is_sram_locked(void)
__raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
__raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
}
if (cpu_is_omap34xx()) {
if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
__raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
__raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
__raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
......@@ -124,7 +124,10 @@ static void __init omap_detect_sram(void)
omap_sram_size = 0x800; /* 2K */
}
} else {
if (cpu_is_omap34xx()) {
if (cpu_is_am33xx()) {
omap_sram_start = AM33XX_SRAM_PA;
omap_sram_size = 0x10000; /* 64K */
} else if (cpu_is_omap34xx()) {
omap_sram_start = OMAP3_SRAM_PA;
omap_sram_size = 0x10000; /* 64K */
} else if (cpu_is_omap44xx()) {
......@@ -368,6 +371,11 @@ static inline int omap34xx_sram_init(void)
return 0;
}
static inline int am33xx_sram_init(void)
{
return 0;
}
int __init omap_sram_init(void)
{
omap_detect_sram();
......@@ -379,6 +387,8 @@ int __init omap_sram_init(void)
omap242x_sram_init();
else if (cpu_is_omap2430())
omap243x_sram_init();
else if (cpu_is_am33xx())
am33xx_sram_init();
else if (cpu_is_omap34xx())
omap34xx_sram_init();
......
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